[J-u-boot.git] / include / zynqmppl.h

/*
 * (C) Copyright 2015 Xilinx, Inc,
 * Michal Simek <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#ifndef _ZYNQMPPL_H_
#define _ZYNQMPPL_H_

#include <xilinx.h>

#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID		0xC2000018
#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD		0xC2000016
#define ZYNQMP_FPGA_OP_INIT			(1 << 0)
#define ZYNQMP_FPGA_OP_LOAD			(1 << 1)
#define ZYNQMP_FPGA_OP_DONE			(1 << 2)

#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT	15
#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK	(0xf << \
					ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
#define ZYNQMP_CSU_IDCODE_SVD_SHIFT	12
#define ZYNQMP_CSU_IDCODE_SVD_MASK	(0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)

extern struct xilinx_fpga_op zynqmp_op;

#define XILINX_ZYNQMP_DESC \
{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }

#endif /* _ZYNQMPPL_H_ */
Commit	Line	Data
6b245014 SDPP	1	/*
	2	* (C) Copyright 2015 Xilinx, Inc,
	3	* Michal Simek <[email protected]>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#ifndef _ZYNQMPPL_H_
	9	#define _ZYNQMPPL_H_
	10
	11	#include <xilinx.h>
	12
47e60cbd	13	#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
6b245014 SDPP	14	#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
	15	#define ZYNQMP_FPGA_OP_INIT (1 << 0)
	16	#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
	17	#define ZYNQMP_FPGA_OP_DONE (1 << 2)
	18
0cba6abb SB	19	#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
	20	#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
	21	ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
	22	#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
92687047	23	#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
0cba6abb	24
6b245014 SDPP	25	extern struct xilinx_fpga_op zynqmp_op;
	26
	27	#define XILINX_ZYNQMP_DESC \
	28	{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
	29
	30	#endif /* _ZYNQMPPL_H_ */