[J-u-boot.git] / include / configs / ti_armv7_omap.h

/*
 * ti_armv7_omap.h
 *
 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * The various ARMv7 SoCs from TI all share a number of IP blocks when
 * implementing a given feature. This is meant to isolate the features
 * that are based on OMAP architecture.
 */
#ifndef __CONFIG_TI_ARMV7_OMAP_H__
#define __CONFIG_TI_ARMV7_OMAP_H__

/* I2C IP block */

/*
 * GPMC NAND block.  We support 1 device and the physical address to
 * access CS0 at is 0x8000000.
 */
#ifdef CONFIG_NAND
#ifndef CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_NAND_BASE		0x8000000
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#endif

/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */
Commit	Line	Data
9a0f4004 NM	1	/*
	2	* ti_armv7_omap.h
	3	*
	4	* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*
	8	* The various ARMv7 SoCs from TI all share a number of IP blocks when
	9	* implementing a given feature. This is meant to isolate the features
	10	* that are based on OMAP architecture.
	11	*/
	12	#ifndef __CONFIG_TI_ARMV7_OMAP_H__
	13	#define __CONFIG_TI_ARMV7_OMAP_H__
	14
9a0f4004	15	/* I2C IP block */
9a0f4004	16
9a0f4004 NM	17	/*
	18	* GPMC NAND block. We support 1 device and the physical address to
	19	* access CS0 at is 0x8000000.
	20	*/
	21	#ifdef CONFIG_NAND
9a0f4004 NM	22	#ifndef CONFIG_SYS_NAND_BASE
	23	#define CONFIG_SYS_NAND_BASE 0x8000000
	24	#endif
	25	#define CONFIG_SYS_MAX_NAND_DEVICE 1
9a0f4004 NM	26	#endif
	27
	28	/* Now for the remaining common defines */
	29	#include <configs/ti_armv7_common.h>
	30
	31	#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */