[J-u-boot.git] / drivers / pci / pcie_mediatek.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MediaTek PCIe host controller driver.
 *
 * Copyright (c) 2017-2019 MediaTek Inc.
 * Author: Ryder Lee <[email protected]>
 *	   Honghui Zhang <[email protected]>
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <generic-phy.h>
#include <pci.h>
#include <reset.h>
#include <asm/io.h>
#include <linux/iopoll.h>
#include <linux/list.h>

/* PCIe shared registers */
#define PCIE_SYS_CFG		0x00
#define PCIE_INT_ENABLE		0x0c
#define PCIE_CFG_ADDR		0x20
#define PCIE_CFG_DATA		0x24

/* PCIe per port registers */
#define PCIE_BAR0_SETUP		0x10
#define PCIE_CLASS		0x34
#define PCIE_LINK_STATUS	0x50

#define PCIE_PORT_INT_EN(x)	BIT(20 + (x))
#define PCIE_PORT_PERST(x)	BIT(1 + (x))
#define PCIE_PORT_LINKUP	BIT(0)
#define PCIE_BAR_MAP_MAX	GENMASK(31, 16)

#define PCIE_BAR_ENABLE		BIT(0)
#define PCIE_REVISION_ID	BIT(0)
#define PCIE_CLASS_CODE		(0x60400 << 8)
#define PCIE_CONF_REG(regn)	(((regn) & GENMASK(7, 2)) | \
				((((regn) >> 8) & GENMASK(3, 0)) << 24))
#define PCIE_CONF_ADDR(regn, bdf) \
				(PCIE_CONF_REG(regn) | (bdf))

/* MediaTek specific configuration registers */
#define PCIE_FTS_NUM		0x70c
#define PCIE_FTS_NUM_MASK	GENMASK(15, 8)
#define PCIE_FTS_NUM_L0(x)	((x) & 0xff << 8)

#define PCIE_FC_CREDIT		0x73c
#define PCIE_FC_CREDIT_MASK	(GENMASK(31, 31) | GENMASK(28, 16))
#define PCIE_FC_CREDIT_VAL(x)	((x) << 16)

struct mtk_pcie_port {
	void __iomem *base;
	struct list_head list;
	struct mtk_pcie *pcie;
	struct reset_ctl reset;
	struct clk sys_ck;
	struct phy phy;
	u32 slot;
};

struct mtk_pcie {
	void __iomem *base;
	struct clk free_ck;
	struct list_head ports;
};

static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
				   uint offset, void **paddress)
{
	struct mtk_pcie *pcie = dev_get_priv(udev);

	writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
	*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);

	return 0;
}

static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
				uint offset, ulong *valuep,
				enum pci_size_t size)
{
	return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
					    bdf, offset, valuep, size);
}

static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
				 uint offset, ulong value,
				 enum pci_size_t size)
{
	return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
					     bdf, offset, value, size);
}

static const struct dm_pci_ops mtk_pcie_ops = {
	.read_config	= mtk_pcie_read_config,
	.write_config	= mtk_pcie_write_config,
};

static void mtk_pcie_port_free(struct mtk_pcie_port *port)
{
	list_del(&port->list);
	free(port);
}

static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
{
	struct mtk_pcie *pcie = port->pcie;
	u32 slot = PCI_DEV(port->slot << 11);
	u32 val;
	int err;

	/* assert port PERST_N */
	setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
	/* de-assert port PERST_N */
	clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));

	/* 100ms timeout value should be enough for Gen1/2 training */
	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
				 !!(val & PCIE_PORT_LINKUP), 100000);
	if (err)
		return -ETIMEDOUT;

	/* disable interrupt */
	clrbits_le32(pcie->base + PCIE_INT_ENABLE,
		     PCIE_PORT_INT_EN(port->slot));

	/* map to all DDR region. We need to set it before cfg operation. */
	writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
	       port->base + PCIE_BAR0_SETUP);

	/* configure class code and revision ID */
	writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);

	/* configure FC credit */
	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
	       pcie->base + PCIE_CFG_ADDR);
	clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
			PCIE_FC_CREDIT_VAL(0x806c));

	/* configure RC FTS number to 250 when it leaves L0s */
	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
	clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
			PCIE_FTS_NUM_L0(0x50));

	return 0;
}

static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
{
	int err;

	err = clk_enable(&port->sys_ck);
	if (err)
		goto exit;

	err = reset_assert(&port->reset);
	if (err)
		goto exit;

	err = reset_deassert(&port->reset);
	if (err)
		goto exit;

	err = generic_phy_init(&port->phy);
	if (err)
		goto exit;

	err = generic_phy_power_on(&port->phy);
	if (err)
		goto exit;

	if (!mtk_pcie_startup_port(port))
		return;

	pr_err("Port%d link down\n", port->slot);
exit:
	mtk_pcie_port_free(port);
}

static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
{
	struct mtk_pcie *pcie = dev_get_priv(dev);
	struct mtk_pcie_port *port;
	char name[10];
	int err;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	snprintf(name, sizeof(name), "port%d", slot);
	port->base = dev_remap_addr_name(dev, name);
	if (!port->base)
		return -ENOENT;

	snprintf(name, sizeof(name), "sys_ck%d", slot);
	err = clk_get_by_name(dev, name, &port->sys_ck);
	if (err)
		return err;

	err = reset_get_by_index(dev, slot, &port->reset);
	if (err)
		return err;

	err = generic_phy_get_by_index(dev, slot, &port->phy);
	if (err)
		return err;

	port->slot = slot;
	port->pcie = pcie;

	INIT_LIST_HEAD(&port->list);
	list_add_tail(&port->list, &pcie->ports);

	return 0;
}

static int mtk_pcie_probe(struct udevice *dev)
{
	struct mtk_pcie *pcie = dev_get_priv(dev);
	struct mtk_pcie_port *port, *tmp;
	ofnode subnode;
	int err;

	INIT_LIST_HEAD(&pcie->ports);

	pcie->base = dev_remap_addr_name(dev, "subsys");
	if (!pcie->base)
		return -ENOENT;

	err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
	if (err)
		return err;

	/* enable top level clock */
	err = clk_enable(&pcie->free_ck);
	if (err)
		return err;

	dev_for_each_subnode(subnode, dev) {
		struct fdt_pci_addr addr;
		u32 slot = 0;

		if (!ofnode_is_available(subnode))
			continue;

		err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
		if (err)
			return err;

		slot = PCI_DEV(addr.phys_hi);

		err = mtk_pcie_parse_port(dev, slot);
		if (err)
			return err;
	}

	/* enable each port, and then check link status */
	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
		mtk_pcie_enable_port(port);

	return 0;
}

static const struct udevice_id mtk_pcie_ids[] = {
	{ .compatible = "mediatek,mt7623-pcie", },
	{ }
};

U_BOOT_DRIVER(pcie_mediatek) = {
	.name	= "pcie_mediatek",
	.id	= UCLASS_PCI,
	.of_match = mtk_pcie_ids,
	.ops	= &mtk_pcie_ops,
	.probe	= mtk_pcie_probe,
	.priv_auto_alloc_size = sizeof(struct mtk_pcie),
};
Commit	Line	Data
42d37450 RL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* MediaTek PCIe host controller driver.
	4	*
	5	* Copyright (c) 2017-2019 MediaTek Inc.
	6	* Author: Ryder Lee <[email protected]>
	7	* Honghui Zhang <[email protected]>
	8	*/
	9
	10	#include <common.h>
	11	#include <clk.h>
	12	#include <dm.h>
	13	#include <generic-phy.h>
	14	#include <pci.h>
	15	#include <reset.h>
	16	#include <asm/io.h>
	17	#include <linux/iopoll.h>
	18	#include <linux/list.h>
	19
	20	/* PCIe shared registers */
	21	#define PCIE_SYS_CFG 0x00
	22	#define PCIE_INT_ENABLE 0x0c
	23	#define PCIE_CFG_ADDR 0x20
	24	#define PCIE_CFG_DATA 0x24
	25
	26	/* PCIe per port registers */
	27	#define PCIE_BAR0_SETUP 0x10
	28	#define PCIE_CLASS 0x34
	29	#define PCIE_LINK_STATUS 0x50
	30
	31	#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
	32	#define PCIE_PORT_PERST(x) BIT(1 + (x))
	33	#define PCIE_PORT_LINKUP BIT(0)
	34	#define PCIE_BAR_MAP_MAX GENMASK(31, 16)
	35
	36	#define PCIE_BAR_ENABLE BIT(0)
	37	#define PCIE_REVISION_ID BIT(0)
	38	#define PCIE_CLASS_CODE (0x60400 << 8)
	39	#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) \| \
	40	((((regn) >> 8) & GENMASK(3, 0)) << 24))
	41	#define PCIE_CONF_ADDR(regn, bdf) \
	42	(PCIE_CONF_REG(regn) \| (bdf))
	43
	44	/* MediaTek specific configuration registers */
	45	#define PCIE_FTS_NUM 0x70c
	46	#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
	47	#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
	48
	49	#define PCIE_FC_CREDIT 0x73c
	50	#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) \| GENMASK(28, 16))
	51	#define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
	52
	53	struct mtk_pcie_port {
	54	void __iomem *base;
	55	struct list_head list;
	56	struct mtk_pcie *pcie;
	57	struct reset_ctl reset;
	58	struct clk sys_ck;
	59	struct phy phy;
	60	u32 slot;
	61	};
	62
	63	struct mtk_pcie {
	64	void __iomem *base;
65	struct clk free_ck;
66	struct list_head ports;
67	};
68
69	static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf,
70	uint offset, void **paddress)
71	{
72	struct mtk_pcie *pcie = dev_get_priv(udev);
73
74	writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
75	*paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
76
77	return 0;
78	}
79
80	static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf,
81	uint offset, ulong *valuep,
82	enum pci_size_t size)
83	{
84	return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
85	bdf, offset, valuep, size);
86	}
87
88	static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
89	uint offset, ulong value,
90	enum pci_size_t size)
91	{
92	return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
93	bdf, offset, value, size);
94	}
95
96	static const struct dm_pci_ops mtk_pcie_ops = {
97	.read_config = mtk_pcie_read_config,
98	.write_config = mtk_pcie_write_config,
99	};
100
101	static void mtk_pcie_port_free(struct mtk_pcie_port *port)
102	{
103	list_del(&port->list);
104	free(port);
105	}
106
107	static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
108	{
109	struct mtk_pcie *pcie = port->pcie;
110	u32 slot = PCI_DEV(port->slot << 11);
111	u32 val;
112	int err;
113
114	/* assert port PERST_N */
115	setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
116	/* de-assert port PERST_N */
117	clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
118
119	/* 100ms timeout value should be enough for Gen1/2 training */
120	err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
121	!!(val & PCIE_PORT_LINKUP), 100000);
122	if (err)
123	return -ETIMEDOUT;
124
125	/* disable interrupt */
126	clrbits_le32(pcie->base + PCIE_INT_ENABLE,
127	PCIE_PORT_INT_EN(port->slot));
128
129	/* map to all DDR region. We need to set it before cfg operation. */
130	writel(PCIE_BAR_MAP_MAX \| PCIE_BAR_ENABLE,
131	port->base + PCIE_BAR0_SETUP);
132
133	/* configure class code and revision ID */
134	writel(PCIE_CLASS_CODE \| PCIE_REVISION_ID, port->base + PCIE_CLASS);
135
136	/* configure FC credit */
137	writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
138	pcie->base + PCIE_CFG_ADDR);
139	clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
140	PCIE_FC_CREDIT_VAL(0x806c));
141
142	/* configure RC FTS number to 250 when it leaves L0s */
143	writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
144	clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
145	PCIE_FTS_NUM_L0(0x50));
146
147	return 0;
148	}
149
150	static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
151	{
152	int err;
153
154	err = clk_enable(&port->sys_ck);
155	if (err)
156	goto exit;
157
158	err = reset_assert(&port->reset);
159	if (err)
160	goto exit;
161
162	err = reset_deassert(&port->reset);
163	if (err)
164	goto exit;
165
166	err = generic_phy_init(&port->phy);
167	if (err)
168	goto exit;
169
170	err = generic_phy_power_on(&port->phy);
171	if (err)
172	goto exit;
173
174	if (!mtk_pcie_startup_port(port))
175	return;
176
177	pr_err("Port%d link down\n", port->slot);
178	exit:
179	mtk_pcie_port_free(port);
180	}
181
182	static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
183	{
184	struct mtk_pcie *pcie = dev_get_priv(dev);
185	struct mtk_pcie_port *port;
186	char name[10];
187	int err;
188
189	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
190	if (!port)
191	return -ENOMEM;
192
193	snprintf(name, sizeof(name), "port%d", slot);
194	port->base = dev_remap_addr_name(dev, name);
195	if (!port->base)
196	return -ENOENT;
197
198	snprintf(name, sizeof(name), "sys_ck%d", slot);
199	err = clk_get_by_name(dev, name, &port->sys_ck);
200	if (err)
201	return err;
202
203	err = reset_get_by_index(dev, slot, &port->reset);
204	if (err)
205	return err;
206
207	err = generic_phy_get_by_index(dev, slot, &port->phy);
208	if (err)
209	return err;
210
211	port->slot = slot;
212	port->pcie = pcie;
213
214	INIT_LIST_HEAD(&port->list);
215	list_add_tail(&port->list, &pcie->ports);
216
217	return 0;
218	}
219
220	static int mtk_pcie_probe(struct udevice *dev)
221	{
222	struct mtk_pcie *pcie = dev_get_priv(dev);
223	struct mtk_pcie_port port, tmp;
224	ofnode subnode;
225	int err;
226
227	INIT_LIST_HEAD(&pcie->ports);
228
229	pcie->base = dev_remap_addr_name(dev, "subsys");
230	if (!pcie->base)
231	return -ENOENT;
232
233	err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
234	if (err)
235	return err;
236
237	/* enable top level clock */
238	err = clk_enable(&pcie->free_ck);
239	if (err)
240	return err;
241
242	dev_for_each_subnode(subnode, dev) {
243	struct fdt_pci_addr addr;
244	u32 slot = 0;
245
246	if (!ofnode_is_available(subnode))
247	continue;
248
249	err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
250	if (err)
251	return err;
252
253	slot = PCI_DEV(addr.phys_hi);
254
255	err = mtk_pcie_parse_port(dev, slot);
256	if (err)
257	return err;
258	}
259
260	/* enable each port, and then check link status */
261	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
262	mtk_pcie_enable_port(port);
263
264	return 0;
265	}
266
267	static const struct udevice_id mtk_pcie_ids[] = {
268	{ .compatible = "mediatek,mt7623-pcie", },
269	{ }
270	};
271
272	U_BOOT_DRIVER(pcie_mediatek) = {
273	.name = "pcie_mediatek",
274	.id = UCLASS_PCI,
275	.of_match = mtk_pcie_ids,
276	.ops = &mtk_pcie_ops,
277	.probe = mtk_pcie_probe,
278	.priv_auto_alloc_size = sizeof(struct mtk_pcie),
279	};