[J-u-boot.git] / include / configs / T4240RDB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2014 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T4240 RDB board configuration file
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <linux/stringify.h>

#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */

#ifdef CONFIG_RAMBOOT_PBL
#ifndef CONFIG_SDCARD
#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
#else
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef	CONFIG_SDCARD
#define CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif
#endif /* CONFIG_RAMBOOT_PBL */

/* High Level Configuration Options */

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 *  Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define CONFIG_SYS_L3_SIZE		(512 << 10)
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#define CONFIG_SYS_DCSRBAR		0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE	0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

/* I2C */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull

/*
 * Environment
 */
#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/

#define HVBOOT					\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

/*
 * DDR Setup
 */
#define SPD_EEPROM_ADDRESS1	0x52
#define SPD_EEPROM_ADDRESS2	0x54
#define SPD_EEPROM_ADDRESS3	0x56
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */

/*
 * IFC Definitions
 */
#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_DDR_LAW		11
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3

/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE	0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR3_EXT	(0xf)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3	0x0

/* CPLD Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
					FTIM1_GPCM_TRAD(0x1f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3		0x0

/* I2C */
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */

#define I2C_MUX_CH_DEFAULT	0x8
#define I2C_MUX_CH_VOL_MONITOR	0xa
#define I2C_MUX_CH_VSC3316_FS	0xc
#define I2C_MUX_CH_VSC3316_BS	0xd

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR		0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT	3

/* The lowest and highest voltage allowed for T4240RDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * eSPI - Enhanced SPI
 */

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	50
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	50
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_INTERLAKEN

#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#define SGMII_PHY_ADDR1 0x0
#define SGMII_PHY_ADDR2 0x1
#define SGMII_PHY_ADDR3 0x2
#define SGMII_PHY_ADDR4 0x3
#define SGMII_PHY_ADDR5 0x4
#define SGMII_PHY_ADDR6 0x5
#define SGMII_PHY_ADDR7 0x6
#define SGMII_PHY_ADDR8 0x7
#define FM1_10GEC1_PHY_ADDR	0x10
#define FM1_10GEC2_PHY_ADDR	0x11
#define FM2_10GEC1_PHY_ADDR	0x12
#define FM2_10GEC2_PHY_ADDR	0x13
#define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
#define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
#define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
#define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
#endif

/*
* USB
*/

#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
#endif


#define __USB_PHY_TYPE	utmi

/*
 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 * interleaving. It can be cacheline, page, bank, superbank.
 * See doc/README.fsl-ddr for details.
 */
#ifdef CONFIG_ARCH_T4240
#define CTRL_INTLV_PREFERED 3way_4KB
#else
#define CTRL_INTLV_PREFERED cacheline
#endif

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:"					\
	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
	"bank_intlv=auto;"					\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
	"bdev=sda3\0"

#define HVBOOT					\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

#include <asm/fsl_secure_boot.h>

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
0b2e13d9 CL	2	/*
0b2e13d9 CL	3	* Copyright 2014 Freescale Semiconductor, Inc.
34f39ce8	4	* Copyright 2020-2021 NXP
0b2e13d9 CL	5	*/
	6
	7	/*
	8	* T4240 RDB board configuration file
	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
1af3c7f4 SG	13	#include <linux/stringify.h>
1af3c7f4 SG	14
0b2e13d9 CL	15	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
	16
	17	#ifdef CONFIG_RAMBOOT_PBL
373762c3 CL	18	#ifndef CONFIG_SDCARD
	19	#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
	20	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
	21	#else
373762c3 CL	22	#define RESET_VECTOR_OFFSET 0x27FFC
	23	#define BOOT_PAGE_OFFSET 0x27000
	24
	25	#ifdef CONFIG_SDCARD
	26	#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
373762c3 CL	27	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	28	#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
	29	#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
	30	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
373762c3 CL	31	#endif
373762c3 CL	32
0b2e13d9	33	#endif
373762c3	34	#endif /* CONFIG_RAMBOOT_PBL */
0b2e13d9	35
0b2e13d9	36	/* High Level Configuration Options */
0b2e13d9	37
0b2e13d9 CL	38	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	39	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	40	#endif
	41
51370d56	42	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
0b2e13d9	43
0b2e13d9 CL	44	/*
	45	* These can be toggled for performance analysis, otherwise use default.
	46	*/
0b2e13d9	47	#ifdef CONFIG_DDR_ECC
0b2e13d9 CL	48	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	49	#endif
	50
0b2e13d9 CL	51	/*
	52	* Config the L3 Cache as L3 SRAM
	53	*/
373762c3 CL	54	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
373762c3 CL	55	#define CONFIG_SYS_L3_SIZE (512 << 10)
a09fea1d	56	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
0b2e13d9 CL	57
	58	#define CONFIG_SYS_DCSRBAR 0xf0000000
	59	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	60
	61	/*
	62	* DDR Setup
	63	*/
	64	#define CONFIG_VERY_BIG_RAM
	65	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	66	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	67
0b2e13d9 CL	68	/*
	69	* IFC Definitions
	70	*/
	71	#define CONFIG_SYS_FLASH_BASE 0xe0000000
	72	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	73
0b2e13d9 CL	74	#define CONFIG_HWCONFIG
	75
	76	/* define to use L1 as initial stack */
	77	#define CONFIG_L1_INIT_RAM
	78	#define CONFIG_SYS_INIT_RAM_LOCK
	79	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	80	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	81	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
0b2e13d9 CL	82	/* The assembler doesn't like typecast */
	83	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	84	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	85	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	86	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
	87
4c97c8cd	88	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
0b2e13d9	89
373762c3	90	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
0b2e13d9 CL	91
	92	/* Serial Port - controlled on board with jumper J8
	93	* open - index 2
	94	* shorted - index 1
	95	*/
0b2e13d9 CL	96	#define CONFIG_SYS_NS16550_SERIAL
	97	#define CONFIG_SYS_NS16550_REG_SIZE 1
	98	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	99
	100	#define CONFIG_SYS_BAUDRATE_TABLE \
	101	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	102
	103	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	104	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	105	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	106	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	107
0b2e13d9	108	/* I2C */
e6bd72f8	109
0b2e13d9 CL	110	/*
	111	* General PCI
	112	* Memory space is mapped 1-1, but I/O space must start from 0.
	113	*/
	114
	115	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	116	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
0b2e13d9	117	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
0b2e13d9	118	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
0b2e13d9	119	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
0b2e13d9 CL	120
	121	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	122	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
0b2e13d9	123	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
0b2e13d9	124	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
0b2e13d9	125	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
0b2e13d9 CL	126
	127	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	128	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
0b2e13d9	129	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
0b2e13d9	130	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
0b2e13d9	131	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
0b2e13d9 CL	132
	133	/* controller 4, Base address 203000 */
	134	#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
	135	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
0b2e13d9	136	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
0b2e13d9	137
0b2e13d9 CL	138	/*
	139	* Environment
	140	*/
	141	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	142	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	143
0b2e13d9 CL	144	/*
	145	* Miscellaneous configurable options
	146	*/
0b2e13d9 CL	147
	148	/*
	149	* For booting Linux, the board info and command line data
	150	* have to be in the first 64 MB of memory, since this is
	151	* the maximum mapped by the Linux kernel during initialization.
	152	*/
	153	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
0b2e13d9	154
0b2e13d9 CL	155	/*
	156	* Environment Configuration
	157	*/
	158	#define CONFIG_ROOTPATH "/opt/nfsroot"
0b2e13d9 CL	159	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
0b2e13d9 CL	160
7ae1b080	161	#define HVBOOT \
0b2e13d9 CL	162	"setenv bootargs config-addr=0x60000000; " \
	163	"bootm 0x01000000 - 0x00f00000"
	164
0b2e13d9 CL	165	/*
	166	* DDR Setup
	167	*/
0b2e13d9 CL	168	#define SPD_EEPROM_ADDRESS1 0x52
	169	#define SPD_EEPROM_ADDRESS2 0x54
	170	#define SPD_EEPROM_ADDRESS3 0x56
	171	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
	172	#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
	173
	174	/*
	175	* IFC Definitions
	176	*/
	177	#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
	178	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	179	+ 0x8000000) \| \
	180	CSPR_PORT_SIZE_16 \| \
	181	CSPR_MSEL_NOR \| \
	182	CSPR_V)
	183	#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
	184	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	185	CSPR_PORT_SIZE_16 \| \
	186	CSPR_MSEL_NOR \| \
	187	CSPR_V)
	188	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	189	/* NOR Flash Timing Params */
	190	#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
	191
	192	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	193	FTIM0_NOR_TEADC(0x5) \| \
	194	FTIM0_NOR_TEAHC(0x5))
	195	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	196	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	197	FTIM1_NOR_TSEQRAD_NOR(0x13))
	198	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	199	FTIM2_NOR_TCH(0x4) \| \
	200	FTIM2_NOR_TWPH(0x0E) \| \
	201	FTIM2_NOR_TWP(0x1c))
	202	#define CONFIG_SYS_NOR_FTIM3 0x0
	203
0b2e13d9 CL	204	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
0b2e13d9 CL	205
0b2e13d9 CL	206	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
	207	+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
	208
	209	/* NAND Flash on IFC */
0b2e13d9 CL	210	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	211	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	212	#define CONFIG_SYS_NAND_BASE 0xff800000
	213	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	214
	215	#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
	216	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	217	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	218	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	219	\| CSPR_V)
	220	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	221
	222	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	223	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	224	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	225	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	226	\| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
	227	\| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
	228	\| CSOR_NAND_PB(128)) /Page Per Block = 128/
	229
0b2e13d9 CL	230	/* ONFI NAND Flash mode0 Timing Params */
	231	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	232	FTIM0_NAND_TWP(0x18) \| \
	233	FTIM0_NAND_TWCHT(0x07) \| \
	234	FTIM0_NAND_TWH(0x0a))
	235	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	236	FTIM1_NAND_TWBE(0x39) \| \
	237	FTIM1_NAND_TRR(0x0e) \| \
	238	FTIM1_NAND_TRP(0x18))
	239	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	240	FTIM2_NAND_TREH(0x0a) \| \
	241	FTIM2_NAND_TWHRE(0x1e))
	242	#define CONFIG_SYS_NAND_FTIM3 0x0
	243
	244	#define CONFIG_SYS_NAND_DDR_LAW 11
	245	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	246	#define CONFIG_SYS_MAX_NAND_DEVICE 1
0b2e13d9	247
88718be3	248	#if defined(CONFIG_MTD_RAW_NAND)
0b2e13d9 CL	249	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	250	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	251	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	252	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	253	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	254	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	255	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	256	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	257	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	258	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
	259	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	260	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	261	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	262	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	263	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	264	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	265	#else
	266	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	267	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	268	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	269	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	270	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	271	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	272	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	273	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	274	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
	275	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
	276	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
	277	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
	278	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
	279	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
	280	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
	281	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
	282	#endif
	283	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	284	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
	285	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	286	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	287	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	288	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	289	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	290	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	291
ab06b236 CL	292	/* CPLD on IFC */
	293	#define CONFIG_SYS_CPLD_BASE 0xffdf0000
	294	#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_CPLD_BASE)
	295	#define CONFIG_SYS_CSPR3_EXT (0xf)
	296	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
	297	\| CSPR_PORT_SIZE_8 \
	298	\| CSPR_MSEL_GPCM \
	299	\| CSPR_V)
	300
088d52cf	301	#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
ab06b236 CL	302	#define CONFIG_SYS_CSOR3 0x0
	303
	304	/* CPLD Timing parameters for IFC CS3 */
	305	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	306	FTIM0_GPCM_TEADC(0x0e) \| \
	307	FTIM0_GPCM_TEAHC(0x0e))
	308	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) \| \
	309	FTIM1_GPCM_TRAD(0x1f))
	310	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
1b5c2b51	311	FTIM2_GPCM_TCH(0x8) \| \
ab06b236 CL	312	FTIM2_GPCM_TWP(0x1f))
	313	#define CONFIG_SYS_CS3_FTIM3 0x0
	314
0b2e13d9	315	/* I2C */
0b2e13d9 CL	316	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
	317	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
	318
	319	#define I2C_MUX_CH_DEFAULT 0x8
	320	#define I2C_MUX_CH_VOL_MONITOR 0xa
	321	#define I2C_MUX_CH_VSC3316_FS 0xc
	322	#define I2C_MUX_CH_VSC3316_BS 0xd
	323
	324	/* Voltage monitor on channel 2*/
	325	#define I2C_VOL_MONITOR_ADDR 0x40
	326	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	327	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	328	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
	329
2f66a828 YZ	330	/* The lowest and highest voltage allowed for T4240RDB */
	331	#define VDD_MV_MIN 819
	332	#define VDD_MV_MAX 1212
	333
0b2e13d9 CL	334	/*
	335	* eSPI - Enhanced SPI
	336	*/
0b2e13d9	337
0b2e13d9 CL	338	/* Qman/Bman */
0b2e13d9 CL	339	#ifndef CONFIG_NOBQFMAN
0b2e13d9 CL	340	#define CONFIG_SYS_BMAN_NUM_PORTALS 50
	341	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	342	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	343	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	344	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	345	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	346	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	347	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	348	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	349	CONFIG_SYS_BMAN_CENA_SIZE)
	350	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	351	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
0b2e13d9 CL	352	#define CONFIG_SYS_QMAN_NUM_PORTALS 50
	353	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	354	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	355	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	356	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	357	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	358	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	359	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	360	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	361	CONFIG_SYS_QMAN_CENA_SIZE)
	362	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	363	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
0b2e13d9 CL	364
	365	#define CONFIG_SYS_DPAA_FMAN
	366	#define CONFIG_SYS_DPAA_PME
	367	#define CONFIG_SYS_PMAN
	368	#define CONFIG_SYS_DPAA_DCE
	369	#define CONFIG_SYS_DPAA_RMAN
	370	#define CONFIG_SYS_INTERLAKEN
	371
0b2e13d9 CL	372	#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
	373	#endif /* CONFIG_NOBQFMAN */
	374
	375	#ifdef CONFIG_SYS_DPAA_FMAN
0b2e13d9 CL	376	#define SGMII_PHY_ADDR1 0x0
	377	#define SGMII_PHY_ADDR2 0x1
	378	#define SGMII_PHY_ADDR3 0x2
	379	#define SGMII_PHY_ADDR4 0x3
	380	#define SGMII_PHY_ADDR5 0x4
	381	#define SGMII_PHY_ADDR6 0x5
	382	#define SGMII_PHY_ADDR7 0x6
	383	#define SGMII_PHY_ADDR8 0x7
	384	#define FM1_10GEC1_PHY_ADDR 0x10
	385	#define FM1_10GEC2_PHY_ADDR 0x11
	386	#define FM2_10GEC1_PHY_ADDR 0x12
	387	#define FM2_10GEC2_PHY_ADDR 0x13
	388	#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
	389	#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
	390	#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
	391	#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
	392	#endif
	393
0b2e13d9 CL	394	/*
	395	* USB
	396	*/
0b2e13d9	397
0b2e13d9	398	#ifdef CONFIG_MMC
0b2e13d9 CL	399	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
0b2e13d9 CL	400	#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
0b2e13d9 CL	401	#endif
0b2e13d9 CL	402
0b2e13d9 CL	403
	404	#define __USB_PHY_TYPE utmi
	405
	406	/*
	407	* T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
	408	* 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
	409	* interleaving. It can be cacheline, page, bank, superbank.
	410	* See doc/README.fsl-ddr for details.
	411	*/
26bc57da	412	#ifdef CONFIG_ARCH_T4240
0b2e13d9	413	#define CTRL_INTLV_PREFERED 3way_4KB
1a344456 CL	414	#else
	415	#define CTRL_INTLV_PREFERED cacheline
	416	#endif
0b2e13d9 CL	417
	418	#define CONFIG_EXTRA_ENV_SETTINGS \
	419	"hwconfig=fsl_ddr:" \
	420	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
	421	"bank_intlv=auto;" \
	422	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	423	"netdev=eth0\0" \
	424	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	425	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	426	"tftpflash=tftpboot $loadaddr $uboot && " \
	427	"protect off $ubootaddr +$filesize && " \
	428	"erase $ubootaddr +$filesize && " \
	429	"cp.b $loadaddr $ubootaddr $filesize && " \
	430	"protect on $ubootaddr +$filesize && " \
	431	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	432	"consoledev=ttyS0\0" \
	433	"ramdiskaddr=2000000\0" \
	434	"ramdiskfile=t4240rdb/ramdisk.uboot\0" \
b24a4f62	435	"fdtaddr=1e00000\0" \
0b2e13d9 CL	436	"fdtfile=t4240rdb/t4240rdb.dtb\0" \
	437	"bdev=sda3\0"
	438
7ae1b080	439	#define HVBOOT \
0b2e13d9 CL	440	"setenv bootargs config-addr=0x60000000; " \
	441	"bootm 0x01000000 - 0x00f00000"
	442
0b2e13d9 CL	443	#include <asm/fsl_secure_boot.h>
0b2e13d9 CL	444
0b2e13d9	445	#endif /* __CONFIG_H */