[J-u-boot.git] / include / configs / ls2080aqds.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017, 2019-2021 NXP
 * Copyright 2015 Freescale Semiconductor
 */

#ifndef __LS2_QDS_H
#define __LS2_QDS_H

#include "ls2080a_common.h"

#ifdef CONFIG_FSL_QSPI
#define CONFIG_QIXIS_I2C_ACCESS
#define CONFIG_SYS_I2C_IFDR_DIV		0x7e
#endif

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk()/4)

#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS3	0x53
#define SPD_EEPROM_ADDRESS4	0x54
#define SPD_EEPROM_ADDRESS5	0x55
#define SPD_EEPROM_ADDRESS6	0x56	/* dummy address */
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR		2
#define CONFIG_CHIP_SELECTS_PER_CTRL		4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR	1
#endif

/* SATA */
#define CONFIG_SCSI_AHCI_PLAT

#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
#define CONFIG_SYS_SATA2			AHCI_BASE_ADDR2

#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
#define CONFIG_SYS_SCSI_MAX_LUN			1
#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
						CONFIG_SYS_SCSI_MAX_LUN)

#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128*1024*1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64*1024*1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(12)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1a) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifdef CONFIG_MTD_NOR_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
					 CONFIG_SYS_FLASH_BASE + 0x40000000}
#endif

#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
#define QIXIS_LBMAP_SWITCH		0x06
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_QSPI		0x0f
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_RCW_SRC_NAND		0x107
#define QIXIS_RCW_SRC_SD		0x40
#define QIXIS_RCW_SRC_QSPI		0x62
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_CSPR3_EXT	(0x0)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_CSPR3_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)

#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
#define CONFIG_SYS_CSOR3	CSOR_GPCM_ADM_SHIFT(12)
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define CONFIG_SYS_CS3_FTIM3		0x0

#if defined(CONFIG_SPL)
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR2_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK2_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SPL_PAD_TO		0x20000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 * 1024)
#endif
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR_EARLY
#define CONFIG_SYS_CSPR1_FINAL		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK_EARLY
#define CONFIG_SYS_AMASK1_FINAL		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

/* Debug Server firmware */
#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580D00000ULL

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

/*
 * I2C
 */
#define I2C_MUX_PCA_ADDR		0x77
#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/

/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT      0x8

/* SPI */

/*
 * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
 * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
 * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
 */
#define FSL_QIXIS_BRDCFG9_QSPI		0x1

/*
 * MMC
 */
#ifdef CONFIG_MMC
#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
#endif

/*
 * RTC configuration
 */
#define RTC
#define CONFIG_RTC_DS3231               1
#define CONFIG_SYS_I2C_RTC_ADDR         0x68

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM	0

#define CONFIG_FSL_MEMAC

#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=esbc_validate 0x580640000;"  \
	"esbc_validate 0x580680000;"            \
	"fsl_mc start mc 0x580a00000"           \
	" 0x580e00000 \0"
#else
#ifdef CONFIG_TFABOOT
#define SD_MC_INIT_CMD				\
	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define IFC_MC_INIT_CMD				\
	"fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x80100000\0"                 \
	"loadaddr_sd=0x90100000\0"                 \
	"kernel_addr=0x581000000\0"		          \
	"kernel_addr_sd=0x8000\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x581000000\0"            \
	"kernel_start_sd=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x2800000\0"               \
	"kernel_size_sd=0x14000\0"               \
	"load_addr=0xa0000000\0"		            \
	"kernelheader_addr=0x580600000\0"	\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernelheader_size=0x40000\0"		\
	"BOARD=ls2088aqds\0" \
	"mcmemsize=0x70000000 \0" \
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	IFC_MC_INIT_CMD				\
	BOOTENV					\
	"boot_scripts=ls2088aqds_boot.scr\0"	\
	"boot_script_hdr=hdr_ls2088aqds_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} "	\
			"${scriptaddr} ${prefix}${script}; "	\
		"env exists secureboot && load ${devtype} "	\
			"${devnum}:${distro_bootpart} "		\
			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
			"&& esbc_validate ${scripthdraddr};"	\
		"source ${scriptaddr}\0"			\
	"nor_bootcmd=echo Trying load from nor..;"		\
		"cp.b $kernel_addr $load_addr "			\
		"$kernel_size ; env exists secureboot && "	\
		"cp.b $kernelheader_addr $kernelheader_addr_r "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$BOARD\0"	\
	"sd_bootcmd=echo Trying load from SD ..;" \
	"mmcinfo; mmc read $load_addr "		\
	"$kernel_addr_sd $kernel_size_sd && "	\
	"bootm $load_addr#$BOARD\0"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"    \
	"loadaddr=0x90100000\0"                 \
	"kernel_addr=0x800\0"                \
	"ramdisk_addr=0x800000\0"               \
	"ramdisk_size=0x2000000\0"              \
	"fdt_high=0xa0000000\0"                 \
	"initrd_high=0xffffffffffffffff\0"      \
	"kernel_start=0x8000\0"              \
	"kernel_load=0xa0000000\0"              \
	"kernel_size=0x14000\0"               \
	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"  \
	"mmc read 0x80e00000 0x7000 0x800;" \
	"fsl_mc start mc 0x80a00000 0x80e00000\0"       \
	"mcmemsize=0x70000000 \0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"loadaddr=0x80100000\0"			\
	"kernel_addr=0x100000\0"		\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"kernel_start=0x581000000\0"		\
	"kernel_load=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"mcmemsize=0x40000000\0"		\
	"mcinitcmd=fsl_mc start mc 0x580a00000" \
	" 0x580e00000 \0"
#endif /* CONFIG_TFABOOT */
#endif /* CONFIG_NXP_ESBC */

#ifdef CONFIG_TFABOOT
#define BOOT_TARGET_DEVICES(func) \
	func(USB, usb, 0) \
	func(MMC, mmc, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>

#define SD_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
			"&& esbc_validate $load_addr; "			\
			"env exists mcinitcmd && run mcinitcmd "	\
			"&& mmc read 0x80d00000 0x6800 0x800 "		\
			"&& fsl_mc lazyapply dpl 0x80d00000; "		\
			"run distro_bootcmd;run sd_bootcmd; "		\
			"env exists secureboot && esbc_halt;"

#define IFC_NOR_BOOTCOMMAND						\
			"env exists mcinitcmd && env exists secureboot "\
			"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
			"&& fsl_mc lazyapply dpl 0x580d00000;"		\
			"run distro_bootcmd;run nor_bootcmd; "		\
			"env exists secureboot && esbc_halt;"
#endif

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F

#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf

#define CONFIG_ETHPRIME		"DPMAC1@xgmii"

#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS2_QDS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
7288c2c2	2	/*
34f39ce8	3	* Copyright 2017, 2019-2021 NXP
7288c2c2	4	* Copyright 2015 Freescale Semiconductor
7288c2c2 YS	5	*/
	6
	7	#ifndef __LS2_QDS_H
	8	#define __LS2_QDS_H
	9
44937214	10	#include "ls2080a_common.h"
7288c2c2	11
8c77ef85	12	#ifdef CONFIG_FSL_QSPI
8c77ef85	13	#define CONFIG_QIXIS_I2C_ACCESS
8c77ef85 YY	14	#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
	15	#endif
	16
	17	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
2f8a6db5	18	#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
7288c2c2	19
7288c2c2 YS	20	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	21	#define SPD_EEPROM_ADDRESS1 0x51
	22	#define SPD_EEPROM_ADDRESS2 0x52
	23	#define SPD_EEPROM_ADDRESS3 0x53
	24	#define SPD_EEPROM_ADDRESS4 0x54
	25	#define SPD_EEPROM_ADDRESS5 0x55
	26	#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
	27	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	28	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	29	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	30	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214	31	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
7288c2c2	32	#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214	33	#endif
7288c2c2	34
989c5f0a	35	/* SATA */
989c5f0a	36	#define CONFIG_SCSI_AHCI_PLAT
989c5f0a TY	37
	38	#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
	39	#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
	40
	41	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	42	#define CONFIG_SYS_SCSI_MAX_LUN 1
	43	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	44	CONFIG_SYS_SCSI_MAX_LUN)
	45
7288c2c2 YS	46	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	47	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	48	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(6410241024)
	49
	50	#define CONFIG_SYS_NOR0_CSPR \
	51	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	52	CSPR_PORT_SIZE_16 \| \
	53	CSPR_MSEL_NOR \| \
	54	CSPR_V)
	55	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	56	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	57	CSPR_PORT_SIZE_16 \| \
	58	CSPR_MSEL_NOR \| \
	59	CSPR_V)
	60	#define CONFIG_SYS_NOR1_CSPR \
	61	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) \| \
	62	CSPR_PORT_SIZE_16 \| \
	63	CSPR_MSEL_NOR \| \
	64	CSPR_V)
	65	#define CONFIG_SYS_NOR1_CSPR_EARLY \
	66	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) \| \
	67	CSPR_PORT_SIZE_16 \| \
	68	CSPR_MSEL_NOR \| \
	69	CSPR_V)
	70	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
	71	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	72	FTIM0_NOR_TEADC(0x5) \| \
	73	FTIM0_NOR_TEAHC(0x5))
	74	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	75	FTIM1_NOR_TRAD_NOR(0x1a) \|\
	76	FTIM1_NOR_TSEQRAD_NOR(0x13))
	77	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	78	FTIM2_NOR_TCH(0x4) \| \
	79	FTIM2_NOR_TWPH(0x0E) \| \
	80	FTIM2_NOR_TWP(0x1c))
	81	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	82	#define CONFIG_SYS_IFC_CCR 0x01000000
	83
e856bdcf	84	#ifdef CONFIG_MTD_NOR_FLASH
7288c2c2 YS	85	#define CONFIG_SYS_FLASH_QUIET_TEST
	86	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	87
7288c2c2 YS	88	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	89	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	90	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	91
	92	#define CONFIG_SYS_FLASH_EMPTY_INFO
	93	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
	94	CONFIG_SYS_FLASH_BASE + 0x40000000}
	95	#endif
	96
7288c2c2 YS	97	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	98	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	99
7288c2c2 YS	100	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	101	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	102	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	103	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	104	\| CSPR_V)
	105	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	106
	107	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	108	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	109	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	110	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	111	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	112	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	113	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	114
7288c2c2 YS	115	/* ONFI NAND Flash mode0 Timing Params */
	116	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	117	FTIM0_NAND_TWP(0x18) \| \
	118	FTIM0_NAND_TWCHT(0x07) \| \
	119	FTIM0_NAND_TWH(0x0a))
	120	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	121	FTIM1_NAND_TWBE(0x39) \| \
	122	FTIM1_NAND_TRR(0x0e) \| \
	123	FTIM1_NAND_TRP(0x18))
	124	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	125	FTIM2_NAND_TREH(0x0a) \| \
	126	FTIM2_NAND_TWHRE(0x1e))
	127	#define CONFIG_SYS_NAND_FTIM3 0x0
	128
	129	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	130	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	131	#define CONFIG_MTD_NAND_VERIFY_WRITE
7288c2c2	132
7288c2c2 YS	133	#define CONFIG_FSL_QIXIS /* use common QIXIS code */
	134	#define QIXIS_LBMAP_SWITCH 0x06
	135	#define QIXIS_LBMAP_MASK 0x0f
	136	#define QIXIS_LBMAP_SHIFT 0
	137	#define QIXIS_LBMAP_DFLTBANK 0x00
	138	#define QIXIS_LBMAP_ALTBANK 0x04
b2d5ac59	139	#define QIXIS_LBMAP_NAND 0x09
1f55a938	140	#define QIXIS_LBMAP_SD 0x00
a646f669	141	#define QIXIS_LBMAP_QSPI 0x0f
7288c2c2 YS	142	#define QIXIS_RST_CTL_RESET 0x31
	143	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	144	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	145	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
b2d5ac59	146	#define QIXIS_RCW_SRC_NAND 0x107
1f55a938	147	#define QIXIS_RCW_SRC_SD 0x40
a646f669	148	#define QIXIS_RCW_SRC_QSPI 0x62
7288c2c2 YS	149	#define QIXIS_RST_FORCE_MEM 0x01
	150
	151	#define CONFIG_SYS_CSPR3_EXT (0x0)
	152	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	153	\| CSPR_PORT_SIZE_8 \
	154	\| CSPR_MSEL_GPCM \
	155	\| CSPR_V)
	156	#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	157	\| CSPR_PORT_SIZE_8 \
	158	\| CSPR_MSEL_GPCM \
	159	\| CSPR_V)
	160
	161	#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
	162	#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
	163	/* QIXIS Timing parameters for IFC CS3 */
	164	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	165	FTIM0_GPCM_TEADC(0x0e) \| \
	166	FTIM0_GPCM_TEAHC(0x0e))
	167	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	168	FTIM1_GPCM_TRAD(0x3f))
	169	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	170	FTIM2_GPCM_TCH(0xf) \| \
	171	FTIM2_GPCM_TWP(0x3E))
	172	#define CONFIG_SYS_CS3_FTIM3 0x0
	173
faed6bde SK	174	#if defined(CONFIG_SPL)
faed6bde SK	175	#if defined(CONFIG_NAND_BOOT)
b2d5ac59 SW	176	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	177	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
	178	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
	179	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	180	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	181	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	182	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	183	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	184	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	185	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
	186	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
	187	#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
	188	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
	189	#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
	190	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	191	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	192	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	193	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	194	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	195	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	196	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	197	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	198	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	199	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	200	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	201	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	202	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	203
b2d5ac59	204	#define CONFIG_SPL_PAD_TO 0x20000
74cac00c	205	#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
faed6bde	206	#endif
b2d5ac59	207	#else
7288c2c2 YS	208	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	209	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	210	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	211	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	212	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	213	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	214	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	215	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	216	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	217	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	218	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
	219	#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
	220	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
	221	#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
	222	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	223	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	224	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	225	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	226	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	227	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	228	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	229	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	230	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	231	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	232	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	233	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	234	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
a646f669	235	#endif
b2d5ac59	236
7288c2c2 YS	237	/* Debug Server firmware */
	238	#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
	239	#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
	240
7288c2c2 YS	241	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
	242
	243	/*
	244	* I2C
	245	*/
	246	#define I2C_MUX_PCA_ADDR 0x77
	247	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
	248
	249	/* I2C bus multiplexer */
	250	#define I2C_MUX_CH_DEFAULT 0x8
	251
b7774b05	252	/* SPI */
b718d371	253
453418f2 YY	254	/*
	255	* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
	256	* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
	257	* If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
	258	*/
	259	#define FSL_QIXIS_BRDCFG9_QSPI 0x1
b718d371	260
8b06460e YL	261	/*
	262	* MMC
	263	*/
	264	#ifdef CONFIG_MMC
	265	#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
	266	QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
	267	#endif
	268
7288c2c2 YS	269	/*
	270	* RTC configuration
	271	*/
	272	#define RTC
	273	#define CONFIG_RTC_DS3231 1
	274	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	275
	276	/* EEPROM */
7288c2c2 YS	277	#define CONFIG_SYS_I2C_EEPROM_NXID
7288c2c2 YS	278	#define CONFIG_SYS_EEPROM_BUS_NUM 0
7288c2c2	279
7288c2c2	280	#define CONFIG_FSL_MEMAC
7288c2c2 YS	281
7288c2c2 YS	282	#ifdef CONFIG_PCI
7288c2c2	283	#define CONFIG_PCI_SCAN_SHOW
7288c2c2 YS	284	#endif
7288c2c2 YS	285
7288c2c2 YS	286	/* Initial environment variables */
7288c2c2 YS	287	#undef CONFIG_EXTRA_ENV_SETTINGS
5536c3c9	288	#ifdef CONFIG_NXP_ESBC
7288c2c2 YS	289	#define CONFIG_EXTRA_ENV_SETTINGS \
	290	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	291	"loadaddr=0x80100000\0" \
	292	"kernel_addr=0x100000\0" \
	293	"ramdisk_addr=0x800000\0" \
	294	"ramdisk_size=0x2000000\0" \
	295	"fdt_high=0xa0000000\0" \
	296	"initrd_high=0xffffffffffffffff\0" \
7676074a	297	"kernel_start=0x581000000\0" \
7288c2c2	298	"kernel_load=0xa0000000\0" \
16ed8560	299	"kernel_size=0x2800000\0" \
6d7b9e78	300	"mcmemsize=0x40000000\0" \
8526a58a PS	301	"mcinitcmd=esbc_validate 0x580640000;" \
8526a58a PS	302	"esbc_validate 0x580680000;" \
7676074a UA	303	"fsl_mc start mc 0x580a00000" \
7676074a UA	304	" 0x580e00000 \0"
1908201c RB	305	#else
	306	#ifdef CONFIG_TFABOOT
	307	#define SD_MC_INIT_CMD \
f1898997	308	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
c3d141e0 WK	309	"mmc read 0x80e00000 0x7000 0x800;" \
c3d141e0 WK	310	"fsl_mc start mc 0x80a00000 0x80e00000\0"
1908201c RB	311	#define IFC_MC_INIT_CMD \
	312	"fsl_mc start mc 0x580a00000" \
	313	" 0x580e00000 \0"
	314	#define CONFIG_EXTRA_ENV_SETTINGS \
	315	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	316	"loadaddr=0x80100000\0" \
	317	"loadaddr_sd=0x90100000\0" \
d7a4ddd3 WK	318	"kernel_addr=0x581000000\0" \
d7a4ddd3 WK	319	"kernel_addr_sd=0x8000\0" \
1908201c RB	320	"ramdisk_addr=0x800000\0" \
	321	"ramdisk_size=0x2000000\0" \
	322	"fdt_high=0xa0000000\0" \
	323	"initrd_high=0xffffffffffffffff\0" \
	324	"kernel_start=0x581000000\0" \
	325	"kernel_start_sd=0x8000\0" \
	326	"kernel_load=0xa0000000\0" \
	327	"kernel_size=0x2800000\0" \
	328	"kernel_size_sd=0x14000\0" \
d7a4ddd3	329	"load_addr=0xa0000000\0" \
8526a58a	330	"kernelheader_addr=0x580600000\0" \
d7a4ddd3 WK	331	"kernelheader_addr_r=0x80200000\0" \
	332	"kernelheader_size=0x40000\0" \
	333	"BOARD=ls2088aqds\0" \
	334	"mcmemsize=0x70000000 \0" \
1a9ce6e0 BL	335	"scriptaddr=0x80000000\0" \
1a9ce6e0 BL	336	"scripthdraddr=0x80080000\0" \
d7a4ddd3	337	IFC_MC_INIT_CMD \
1a9ce6e0 BL	338	BOOTENV \
	339	"boot_scripts=ls2088aqds_boot.scr\0" \
	340	"boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
	341	"scan_dev_for_boot_part=" \
	342	"part list ${devtype} ${devnum} devplist; " \
	343	"env exists devplist \|\| setenv devplist 1; " \
	344	"for distro_bootpart in ${devplist}; do " \
	345	"if fstype ${devtype} " \
	346	"${devnum}:${distro_bootpart} " \
	347	"bootfstype; then " \
	348	"run scan_dev_for_boot; " \
	349	"fi; " \
	350	"done\0" \
	351	"boot_a_script=" \
	352	"load ${devtype} ${devnum}:${distro_bootpart} " \
	353	"${scriptaddr} ${prefix}${script}; " \
	354	"env exists secureboot && load ${devtype} " \
	355	"${devnum}:${distro_bootpart} " \
	356	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	357	"&& esbc_validate ${scripthdraddr};" \
	358	"source ${scriptaddr}\0" \
d7a4ddd3 WK	359	"nor_bootcmd=echo Trying load from nor..;" \
	360	"cp.b $kernel_addr $load_addr " \
	361	"$kernel_size ; env exists secureboot && " \
	362	"cp.b $kernelheader_addr $kernelheader_addr_r " \
	363	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	364	"bootm $load_addr#$BOARD\0" \
	365	"sd_bootcmd=echo Trying load from SD ..;" \
	366	"mmcinfo; mmc read $load_addr " \
	367	"$kernel_addr_sd $kernel_size_sd && " \
	368	"bootm $load_addr#$BOARD\0"
1f55a938 SK	369	#elif defined(CONFIG_SD_BOOT)
	370	#define CONFIG_EXTRA_ENV_SETTINGS \
	371	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	372	"loadaddr=0x90100000\0" \
	373	"kernel_addr=0x800\0" \
	374	"ramdisk_addr=0x800000\0" \
	375	"ramdisk_size=0x2000000\0" \
	376	"fdt_high=0xa0000000\0" \
	377	"initrd_high=0xffffffffffffffff\0" \
	378	"kernel_start=0x8000\0" \
	379	"kernel_load=0xa0000000\0" \
	380	"kernel_size=0x14000\0" \
f1898997 PJ	381	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
	382	"mmc read 0x80e00000 0x7000 0x800;" \
	383	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
1f55a938	384	"mcmemsize=0x70000000 \0"
9ed44787 UA	385	#else
	386	#define CONFIG_EXTRA_ENV_SETTINGS \
	387	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	388	"loadaddr=0x80100000\0" \
	389	"kernel_addr=0x100000\0" \
	390	"ramdisk_addr=0x800000\0" \
	391	"ramdisk_size=0x2000000\0" \
	392	"fdt_high=0xa0000000\0" \
	393	"initrd_high=0xffffffffffffffff\0" \
f5bf23d8	394	"kernel_start=0x581000000\0" \
9ed44787 UA	395	"kernel_load=0xa0000000\0" \
9ed44787 UA	396	"kernel_size=0x2800000\0" \
6d7b9e78	397	"mcmemsize=0x40000000\0" \
f5bf23d8 SK	398	"mcinitcmd=fsl_mc start mc 0x580a00000" \
f5bf23d8 SK	399	" 0x580e00000 \0"
1908201c	400	#endif /* CONFIG_TFABOOT */
5536c3c9	401	#endif /* CONFIG_NXP_ESBC */
9ed44787	402
d7a4ddd3	403	#ifdef CONFIG_TFABOOT
1a9ce6e0 BL	404	#define BOOT_TARGET_DEVICES(func) \
	405	func(USB, usb, 0) \
	406	func(MMC, mmc, 0) \
	407	func(SCSI, scsi, 0) \
	408	func(DHCP, dhcp, na)
	409	#include <config_distro_bootcmd.h>
	410
d7a4ddd3 WK	411	#define SD_BOOTCOMMAND \
d7a4ddd3 WK	412	"env exists mcinitcmd && env exists secureboot "\
8526a58a	413	"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
d7a4ddd3 WK	414	"&& esbc_validate $load_addr; " \
d7a4ddd3 WK	415	"env exists mcinitcmd && run mcinitcmd " \
c3d141e0 WK	416	"&& mmc read 0x80d00000 0x6800 0x800 " \
c3d141e0 WK	417	"&& fsl_mc lazyapply dpl 0x80d00000; " \
1a9ce6e0	418	"run distro_bootcmd;run sd_bootcmd; " \
d7a4ddd3 WK	419	"env exists secureboot && esbc_halt;"
	420
	421	#define IFC_NOR_BOOTCOMMAND \
	422	"env exists mcinitcmd && env exists secureboot "\
8526a58a	423	"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
d7a4ddd3	424	"&& fsl_mc lazyapply dpl 0x580d00000;" \
1a9ce6e0	425	"run distro_bootcmd;run nor_bootcmd; " \
d7a4ddd3 WK	426	"env exists secureboot && esbc_halt;"
	427	#endif
	428
1f55a938	429	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
e60476a0	430	#define CONFIG_FSL_MEMAC
e60476a0 PK	431	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	432	#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
	433	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	434	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	435
cf7ee6c4 PK	436	#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
	437	#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
	438	#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
	439	#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
	440	#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
	441	#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
	442	#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
	443	#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
	444	#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
	445	#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
	446	#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
	447	#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
	448	#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
	449	#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
	450	#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
	451	#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
	452
7ad9cc96	453	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
e60476a0 PK	454
	455	#endif
	456
fcfdb6d5 SJ	457	#include <asm/fsl_secure_boot.h>
fcfdb6d5 SJ	458
7288c2c2	459	#endif /* __LS2_QDS_H */