[J-u-boot.git] / include / configs / ls1088ardb.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2017, 2020-2021 NXP
 */

#ifndef __LS1088A_RDB_H
#define __LS1088A_RDB_H

#include "ls1088a_common.h"

#if defined(CONFIG_TFABOOT) || \
	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define SYS_NO_FLASH
#endif

#define COUNTER_FREQUENCY_REAL		25000000	/* 25MHz */
#define COUNTER_FREQUENCY		25000000	/* 25MHz */

#ifdef CONFIG_EMU
#define CONFIG_SYS_FSL_DDR_EMU
#else
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif
#define SPD_EEPROM_ADDRESS	0x51
#define CONFIG_SYS_SPD_BUS_NUM	0	/* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR	1


#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
#define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
#define CONFIG_SYS_NOR_AMASK_EARLY	IFC_AMASK(64 * 1024 * 1024)

#define CONFIG_SYS_NOR0_CSPR					\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)		| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR0_CSPR_EARLY				\
	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)	| \
	CSPR_PORT_SIZE_16					| \
	CSPR_MSEL_NOR						| \
	CSPR_V)
#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(6)
#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
				FTIM0_NOR_TEADC(0x1) | \
				FTIM0_NOR_TEAHC(0x1))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
				FTIM1_NOR_TRAD_NOR(0x1))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
				FTIM2_NOR_TCH(0x0) | \
				FTIM2_NOR_TWP(0x1))
#define CONFIG_SYS_NOR_FTIM3	0x04000000
#define CONFIG_SYS_IFC_CCR	0x01000000

#ifndef SYS_NO_FLASH
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif
#endif

#define CONFIG_SYS_NAND_MAX_ECCPOS	256
#define CONFIG_SYS_NAND_MAX_OOBFREE	2

#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)   | \
					FTIM0_NAND_TWCHT(0x07) | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)  | \
					FTIM1_NAND_TRR(0x0e)   | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
					FTIM2_NAND_TREH(0x0a) | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#ifndef SPL_NO_QIXIS
#define CONFIG_FSL_QIXIS
#endif

#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
#define QIXIS_BRDCFG4_OFFSET            0x54
#define QIXIS_LBMAP_SWITCH		2
#define QIXIS_QMAP_MASK			0xe0
#define QIXIS_QMAP_SHIFT		5
#define QIXIS_LBMAP_MASK		0x1f
#define QIXIS_LBMAP_SHIFT		5
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x20
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_LBMAP_EMMC		0x00
#define QIXIS_LBMAP_SD_QSPI		0x00
#define QIXIS_LBMAP_QSPI		0x00
#define QIXIS_RCW_SRC_SD		0x40
#define QIXIS_RCW_SRC_EMMC		0x41
#define QIXIS_RCW_SRC_QSPI		0x62
#define QIXIS_RST_CTL_RESET		0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define	QIXIS_RST_FORCE_MEM		0x01

#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
					| CSPR_PORT_SIZE_8 \
					| CSPR_MSEL_GPCM \
					| CSPR_V)
#define SYS_FPGA_CSPR_FINAL	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
					| CSPR_PORT_SIZE_8 \
					| CSPR_MSEL_GPCM \
					| CSPR_V)

#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64*1024)
#define CONFIG_SYS_FPGA_CSOR		CSOR_GPCM_ADM_SHIFT(0)
/* QIXIS Timing parameters*/
#define SYS_FPGA_CS_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define SYS_FPGA_CS_FTIM1	(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define SYS_FPGA_CS_FTIM2	(FTIM2_GPCM_TCS(0xf) | \
					FTIM2_GPCM_TCH(0xf) | \
					FTIM2_GPCM_TWP(0x3E))
#define SYS_FPGA_CS_FTIM3	0x0

#if defined(CONFIG_TFABOOT) || \
	defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_CSPR2_FINAL		SYS_FPGA_CSPR_FINAL
#define CONFIG_SYS_AMASK2		CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS2_FTIM0		SYS_FPGA_CS_FTIM0
#define CONFIG_SYS_CS2_FTIM1		SYS_FPGA_CS_FTIM1
#define CONFIG_SYS_CS2_FTIM2		SYS_FPGA_CS_FTIM2
#define CONFIG_SYS_CS2_FTIM3		SYS_FPGA_CS_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
#define CONFIG_SYS_CSPR0_FINAL		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#endif

#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000

#define I2C_MUX_CH_VOL_MONITOR         0xA
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x63
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
#define I2C_SVDD_MONITOR_ADDR		0x4F

/* The lowest and highest voltage allowed for LS1088ARDB */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

#define PWM_CHANNEL0                    0x0

/*
 * I2C bus multiplexer
 */
#define I2C_MUX_PCA_ADDR_PRI		0x77
#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
#define I2C_RETIMER_ADDR		0x18
#define I2C_MUX_CH_DEFAULT		0x8
#define I2C_MUX_CH5			0xD

#ifndef SPL_NO_RTC
/*
* RTC configuration
*/
#define RTC
#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
#endif

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM		0

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif

#define CONFIG_FSL_MEMAC

#ifndef SPL_NO_ENV
/* Initial environment variables */
#ifdef CONFIG_TFABOOT
#define QSPI_MC_INIT_CMD				\
	"sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"	\
	"sf read 0x80e00000 0xE00000 0x100000;"				\
	"env exists secureboot && "			\
	"sf read 0x80640000 0x640000 0x40000 && "	\
	"sf read 0x80680000 0x680000 0x40000 && "	\
	"esbc_validate 0x80640000 && "			\
	"esbc_validate 0x80680000 ;"			\
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#define SD_MC_INIT_CMD				\
	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"		\
	"mmc read 0x80e00000 0x7000 0x800;"				\
	"env exists secureboot && "			\
	"mmc read 0x80640000 0x3200 0x20 && "		\
	"mmc read 0x80680000 0x3400 0x20 && "		\
	"esbc_validate 0x80640000 && "			\
	"esbc_validate 0x80680000 ;"			\
	"fsl_mc start mc 0x80a00000 0x80e00000\0"
#else
#if defined(CONFIG_QSPI_BOOT)
#define MC_INIT_CMD				\
	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"	\
	"sf read 0x80e00000 0xE00000 0x100000;"				\
	"env exists secureboot && "			\
	"sf read 0x80640000 0x640000 0x40000 && "	\
	"sf read 0x80680000 0x680000 0x40000 && "	\
	"esbc_validate 0x80640000 && "			\
	"esbc_validate 0x80680000 ;"			\
	"fsl_mc start mc 0x80a00000 0x80e00000\0"	\
	"mcmemsize=0x70000000\0"
#elif defined(CONFIG_SD_BOOT)
#define MC_INIT_CMD				\
	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"		\
	"mmc read 0x80e00000 0x7000 0x800;"				\
	"env exists secureboot && "			\
	"mmc read 0x80640000 0x3200 0x20 && "		\
	"mmc read 0x80680000 0x3400 0x20 && "		\
	"esbc_validate 0x80640000 && "			\
	"esbc_validate 0x80680000 ;"			\
	"fsl_mc start mc 0x80a00000 0x80e00000\0"	\
	"mcmemsize=0x70000000\0"
#endif
#endif /* CONFIG_TFABOOT */

#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_TFABOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"BOARD=ls1088ardb\0"			\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"			\
	"kernel_addr=0x1000000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernelhdr_addr_sd=0x3000\0"		\
	"kernel_start=0x580100000\0"		\
	"kernelheader_start=0x580600000\0"	\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr=0x600000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"kernelheader_size=0x40000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_size_sd=0x20\0"		\
	QSPI_MC_INIT_CMD			\
	"mcmemsize=0x70000000\0"		\
	BOOTENV					\
	"boot_scripts=ls1088ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1088ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} " \
		"${scriptaddr} ${prefix}${script}; "		\
	"env exists secureboot && load ${devtype} "		\
		"${devnum}:${distro_bootpart} "			\
		"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
		"env exists secureboot "			\
		"&& esbc_validate ${scripthdraddr};"		\
		"source ${scriptaddr}\0"			\
	"installer=load mmc 0:2 $load_addr "			\
		"/flex_installer_arm64.itb; "			\
		"env exists mcinitcmd && run mcinitcmd && "	\
		"mmc read 0x80001000 0x6800 0x800;"		\
		"fsl_mc lazyapply dpl 0x80001000;"			\
		"bootm $load_addr#ls1088ardb\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"		\
		"sf probe && sf read $load_addr "		\
		"$kernel_addr $kernel_size ; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$BOARD\0"			\
		"sd_bootcmd=echo Trying load from sd card..;"		\
		"mmcinfo; mmc read $load_addr "			\
		"$kernel_addr_sd $kernel_size_sd ;"		\
		"env exists secureboot && mmc read $kernelheader_addr_r "\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$BOARD\0"
#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"BOARD=ls1088ardb\0"			\
	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
	"ramdisk_addr=0x800000\0"		\
	"ramdisk_size=0x2000000\0"		\
	"fdt_high=0xa0000000\0"			\
	"initrd_high=0xffffffffffffffff\0"	\
	"fdt_addr=0x64f00000\0"			\
	"kernel_addr=0x1000000\0"		\
	"kernel_addr_sd=0x8000\0"		\
	"kernelhdr_addr_sd=0x3000\0"		\
	"kernel_start=0x580100000\0"		\
	"kernelheader_start=0x580800000\0"	\
	"scriptaddr=0x80000000\0"		\
	"scripthdraddr=0x80080000\0"		\
	"fdtheader_addr_r=0x80100000\0"		\
	"kernelheader_addr=0x600000\0"		\
	"kernelheader_addr_r=0x80200000\0"	\
	"kernel_addr_r=0x81000000\0"		\
	"kernelheader_size=0x40000\0"		\
	"fdt_addr_r=0x90000000\0"		\
	"load_addr=0xa0000000\0"		\
	"kernel_size=0x2800000\0"		\
	"kernel_size_sd=0x14000\0"		\
	"kernelhdr_size_sd=0x20\0"		\
	MC_INIT_CMD				\
	BOOTENV					\
	"boot_scripts=ls1088ardb_boot.scr\0"	\
	"boot_script_hdr=hdr_ls1088ardb_bs.out\0"	\
	"scan_dev_for_boot_part="		\
		"part list ${devtype} ${devnum} devplist; "	\
		"env exists devplist || setenv devplist 1; "	\
		"for distro_bootpart in ${devplist}; do "	\
			"if fstype ${devtype} "			\
				"${devnum}:${distro_bootpart} "	\
				"bootfstype; then "		\
				"run scan_dev_for_boot; "	\
			"fi; "					\
		"done\0"					\
	"boot_a_script="					\
		"load ${devtype} ${devnum}:${distro_bootpart} " \
		"${scriptaddr} ${prefix}${script}; "		\
	"env exists secureboot && load ${devtype} "		\
		"${devnum}:${distro_bootpart} "			\
		"${scripthdraddr} ${prefix}${boot_script_hdr} " \
		"&& esbc_validate ${scripthdraddr};"		\
		"source ${scriptaddr}\0"			\
	"installer=load mmc 0:2 $load_addr "			\
		"/flex_installer_arm64.itb; "			\
		"env exists mcinitcmd && run mcinitcmd && "	\
		"mmc read 0x80001000 0x6800 0x800;"		\
		"fsl_mc lazyapply dpl 0x80001000;"			\
		"bootm $load_addr#ls1088ardb\0"			\
	"qspi_bootcmd=echo Trying load from qspi..;"		\
		"sf probe && sf read $load_addr "		\
		"$kernel_addr $kernel_size ; env exists secureboot "	\
		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
		"bootm $load_addr#$BOARD\0"			\
		"sd_bootcmd=echo Trying load from sd card..;"		\
		"mmcinfo; mmc read $load_addr "			\
		"$kernel_addr_sd $kernel_size_sd ;"		\
		"env exists secureboot && mmc read $kernelheader_addr_r "\
		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
		" && esbc_validate ${kernelheader_addr_r};"	\
		"bootm $load_addr#$BOARD\0"
#endif /* CONFIG_TFABOOT */

#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND					\
	"sf read 0x80001000 0xd00000 0x100000;"		\
		"env exists mcinitcmd && env exists secureboot "	\
		" && sf read 0x806C0000 0x6C0000 0x100000 "	\
		"&& esbc_validate 0x806C0000;env exists mcinitcmd "	\
		"&& fsl_mc lazyapply dpl 0x80001000;"		\
		"run distro_bootcmd;run qspi_bootcmd;"		\
		"env exists secureboot && esbc_halt;"
#define SD_BOOTCOMMAND						\
		"env exists mcinitcmd && mmcinfo; "		\
		"mmc read 0x80001000 0x6800 0x800; "		\
		"env exists mcinitcmd && env exists secureboot "	\
		" && mmc read 0x806C0000 0x3600 0x20 "		\
		"&& esbc_validate 0x806C0000;env exists mcinitcmd "	\
		"&& fsl_mc lazyapply dpl 0x80001000;"		\
		"run distro_bootcmd;run sd_bootcmd;"		\
		"env exists secureboot && esbc_halt;"
#else
#if defined(CONFIG_QSPI_BOOT)
/* Try to boot an on-QSPI kernel first, then do normal distro boot */

/* Try to boot an on-SD kernel first, then do normal distro boot */
#endif
#endif /* CONFIG_TFABOOT */

/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define AQ_PHY_ADDR1			0x00
#define AQR105_IRQ_MASK			0x00000004

#define QSGMII1_PORT1_PHY_ADDR		0x0c
#define QSGMII1_PORT2_PHY_ADDR		0x0d
#define QSGMII1_PORT3_PHY_ADDR		0x0e
#define QSGMII1_PORT4_PHY_ADDR		0x0f
#define QSGMII2_PORT1_PHY_ADDR		0x1c
#define QSGMII2_PORT2_PHY_ADDR		0x1d
#define QSGMII2_PORT3_PHY_ADDR		0x1e
#define QSGMII2_PORT4_PHY_ADDR		0x1f

#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
#endif
#endif

#ifndef SPL_NO_ENV

#define BOOT_TARGET_DEVICES(func) \
	func(MMC, mmc, 0) \
	func(USB, usb, 0) \
	func(SCSI, scsi, 0) \
	func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif

#include <asm/fsl_secure_boot.h>

#endif /* __LS1088A_RDB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
e84a324b	2	/*
34f39ce8	3	* Copyright 2017, 2020-2021 NXP
e84a324b AK	4	*/
	5
	6	#ifndef __LS1088A_RDB_H
	7	#define __LS1088A_RDB_H
	8
	9	#include "ls1088a_common.h"
	10
143af3c6 PG	11	#if defined(CONFIG_TFABOOT) \|\| \
143af3c6 PG	12	defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
10e7eaf0	13	#ifndef CONFIG_SPL_BUILD
e84a324b	14	#define CONFIG_QIXIS_I2C_ACCESS
10e7eaf0	15	#endif
e84a324b	16	#define SYS_NO_FLASH
e84a324b AK	17	#endif
e84a324b AK	18
e84a324b AK	19	#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
	20	#define COUNTER_FREQUENCY 25000000 /* 25MHz */
	21
e84a324b AK	22	#ifdef CONFIG_EMU
e84a324b AK	23	#define CONFIG_SYS_FSL_DDR_EMU
e84a324b	24	#else
e84a324b AK	25	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	26	#endif
	27	#define SPD_EEPROM_ADDRESS 0x51
	28	#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
	29	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	30
	31
	32	#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
	33	#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
	34	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
	35	#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
	36
	37	#define CONFIG_SYS_NOR0_CSPR \
	38	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	39	CSPR_PORT_SIZE_16 \| \
	40	CSPR_MSEL_NOR \| \
	41	CSPR_V)
	42	#define CONFIG_SYS_NOR0_CSPR_EARLY \
	43	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) \| \
	44	CSPR_PORT_SIZE_16 \| \
	45	CSPR_MSEL_NOR \| \
	46	CSPR_V)
	47	#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
	48	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) \| \
	49	FTIM0_NOR_TEADC(0x1) \| \
	50	FTIM0_NOR_TEAHC(0x1))
	51	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) \| \
	52	FTIM1_NOR_TRAD_NOR(0x1))
	53	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) \| \
	54	FTIM2_NOR_TCH(0x0) \| \
	55	FTIM2_NOR_TWP(0x1))
	56	#define CONFIG_SYS_NOR_FTIM3 0x04000000
	57	#define CONFIG_SYS_IFC_CCR 0x01000000
	58
	59	#ifndef SYS_NO_FLASH
e84a324b AK	60	#define CONFIG_SYS_FLASH_QUIET_TEST
	61	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	62
e84a324b AK	63	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
	64	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	65	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	66
	67	#define CONFIG_SYS_FLASH_EMPTY_INFO
	68	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	69	#endif
	70	#endif
10e7eaf0	71
e84a324b AK	72	#define CONFIG_SYS_NAND_MAX_ECCPOS 256
	73	#define CONFIG_SYS_NAND_MAX_OOBFREE 2
	74
	75	#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
	76	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	77	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	78	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	79	\| CSPR_V)
	80	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
	81
	82	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	83	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	84	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	85	\| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
	86	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	87	\| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
	88	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	89
e84a324b AK	90	/* ONFI NAND Flash mode0 Timing Params */
	91	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	92	FTIM0_NAND_TWP(0x18) \| \
	93	FTIM0_NAND_TWCHT(0x07) \| \
	94	FTIM0_NAND_TWH(0x0a))
	95	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	96	FTIM1_NAND_TWBE(0x39) \| \
	97	FTIM1_NAND_TRR(0x0e) \| \
	98	FTIM1_NAND_TRP(0x18))
	99	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	100	FTIM2_NAND_TREH(0x0a) \| \
	101	FTIM2_NAND_TWHRE(0x1e))
	102	#define CONFIG_SYS_NAND_FTIM3 0x0
	103
	104	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	105	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	106	#define CONFIG_MTD_NAND_VERIFY_WRITE
	107
10e7eaf0	108	#ifndef SPL_NO_QIXIS
e84a324b	109	#define CONFIG_FSL_QIXIS
10e7eaf0 SG	110	#endif
10e7eaf0 SG	111
e84a324b	112	#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
ef0789b7	113	#define QIXIS_BRDCFG4_OFFSET 0x54
e84a324b AK	114	#define QIXIS_LBMAP_SWITCH 2
	115	#define QIXIS_QMAP_MASK 0xe0
	116	#define QIXIS_QMAP_SHIFT 5
	117	#define QIXIS_LBMAP_MASK 0x1f
	118	#define QIXIS_LBMAP_SHIFT 5
	119	#define QIXIS_LBMAP_DFLTBANK 0x00
	120	#define QIXIS_LBMAP_ALTBANK 0x20
	121	#define QIXIS_LBMAP_SD 0x00
6c8945ec	122	#define QIXIS_LBMAP_EMMC 0x00
e84a324b AK	123	#define QIXIS_LBMAP_SD_QSPI 0x00
	124	#define QIXIS_LBMAP_QSPI 0x00
	125	#define QIXIS_RCW_SRC_SD 0x40
6c8945ec	126	#define QIXIS_RCW_SRC_EMMC 0x41
e84a324b AK	127	#define QIXIS_RCW_SRC_QSPI 0x62
	128	#define QIXIS_RST_CTL_RESET 0x31
	129	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	130	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	131	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	132	#define QIXIS_RST_FORCE_MEM 0x01
	133
	134	#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
	135	#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
	136	\| CSPR_PORT_SIZE_8 \
	137	\| CSPR_MSEL_GPCM \
	138	\| CSPR_V)
	139	#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	140	\| CSPR_PORT_SIZE_8 \
	141	\| CSPR_MSEL_GPCM \
	142	\| CSPR_V)
	143
	144	#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
	145	#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
	146	/* QIXIS Timing parameters*/
	147	#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	148	FTIM0_GPCM_TEADC(0x0e) \| \
	149	FTIM0_GPCM_TEAHC(0x0e))
	150	#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	151	FTIM1_GPCM_TRAD(0x3f))
	152	#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) \| \
	153	FTIM2_GPCM_TCH(0xf) \| \
	154	FTIM2_GPCM_TWP(0x3E))
	155	#define SYS_FPGA_CS_FTIM3 0x0
	156
143af3c6 PG	157	#if defined(CONFIG_TFABOOT) \|\| \
143af3c6 PG	158	defined(CONFIG_QSPI_BOOT) \|\| defined(CONFIG_SD_BOOT_QSPI)
e84a324b AK	159	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	160	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	161	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	162	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	163	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	164	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	165	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	166	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	167	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
	168	#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
	169	#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
	170	#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
	171	#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
	172	#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
	173	#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
	174	#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
	175	#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
	176	#else
	177	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	178	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
	179	#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
	180	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	181	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	182	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	183	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	184	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	185	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
	186	#endif
	187
e84a324b AK	188	#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
e84a324b AK	189
b5ee48c0	190	#define I2C_MUX_CH_VOL_MONITOR 0xA
23a12cb3 RB	191	/* Voltage monitor on channel 2*/
	192	#define I2C_VOL_MONITOR_ADDR 0x63
	193	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	194	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	195	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
ef0789b7 RB	196	#define I2C_SVDD_MONITOR_ADDR 0x4F
ef0789b7 RB	197
ef0789b7 RB	198	/* The lowest and highest voltage allowed for LS1088ARDB */
	199	#define VDD_MV_MIN 819
	200	#define VDD_MV_MAX 1212
	201
23a12cb3 RB	202	#define PWM_CHANNEL0 0x0
23a12cb3 RB	203
e84a324b AK	204	/*
	205	* I2C bus multiplexer
	206	*/
	207	#define I2C_MUX_PCA_ADDR_PRI 0x77
	208	#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
	209	#define I2C_RETIMER_ADDR 0x18
	210	#define I2C_MUX_CH_DEFAULT 0x8
	211	#define I2C_MUX_CH5 0xD
10e7eaf0 SG	212
10e7eaf0 SG	213	#ifndef SPL_NO_RTC
e84a324b AK	214	/*
	215	* RTC configuration
	216	*/
	217	#define RTC
e84a324b	218	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
10e7eaf0	219	#endif
e84a324b AK	220
e84a324b AK	221	/* EEPROM */
e84a324b AK	222	#define CONFIG_SYS_I2C_EEPROM_NXID
e84a324b AK	223	#define CONFIG_SYS_EEPROM_BUS_NUM 0
e84a324b	224
099f4093 AK	225	#ifdef CONFIG_SPL_BUILD
	226	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	227	#else
e84a324b	228	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
099f4093	229	#endif
e84a324b AK	230
	231	#define CONFIG_FSL_MEMAC
	232
10e7eaf0	233	#ifndef SPL_NO_ENV
e84a324b	234	/* Initial environment variables */
143af3c6 PG	235	#ifdef CONFIG_TFABOOT
143af3c6 PG	236	#define QSPI_MC_INIT_CMD \
644dc8c4 PJ	237	"sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
644dc8c4 PJ	238	"sf read 0x80e00000 0xE00000 0x100000;" \
143af3c6	239	"env exists secureboot && " \
4238e373 PS	240	"sf read 0x80640000 0x640000 0x40000 && " \
	241	"sf read 0x80680000 0x680000 0x40000 && " \
	242	"esbc_validate 0x80640000 && " \
	243	"esbc_validate 0x80680000 ;" \
644dc8c4	244	"fsl_mc start mc 0x80a00000 0x80e00000\0"
143af3c6	245	#define SD_MC_INIT_CMD \
644dc8c4 PJ	246	"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
644dc8c4 PJ	247	"mmc read 0x80e00000 0x7000 0x800;" \
143af3c6	248	"env exists secureboot && " \
4238e373 PS	249	"mmc read 0x80640000 0x3200 0x20 && " \
	250	"mmc read 0x80680000 0x3400 0x20 && " \
	251	"esbc_validate 0x80640000 && " \
	252	"esbc_validate 0x80680000 ;" \
644dc8c4	253	"fsl_mc start mc 0x80a00000 0x80e00000\0"
143af3c6	254	#else
e84a324b	255	#if defined(CONFIG_QSPI_BOOT)
d9195c62	256	#define MC_INIT_CMD \
644dc8c4 PJ	257	"mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
644dc8c4 PJ	258	"sf read 0x80e00000 0xE00000 0x100000;" \
30c41d21	259	"env exists secureboot && " \
4238e373 PS	260	"sf read 0x80640000 0x640000 0x40000 && " \
	261	"sf read 0x80680000 0x680000 0x40000 && " \
	262	"esbc_validate 0x80640000 && " \
	263	"esbc_validate 0x80680000 ;" \
644dc8c4	264	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
d9195c62	265	"mcmemsize=0x70000000\0"
099f4093	266	#elif defined(CONFIG_SD_BOOT)
d9195c62	267	#define MC_INIT_CMD \
644dc8c4 PJ	268	"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
644dc8c4 PJ	269	"mmc read 0x80e00000 0x7000 0x800;" \
30c41d21	270	"env exists secureboot && " \
4238e373 PS	271	"mmc read 0x80640000 0x3200 0x20 && " \
	272	"mmc read 0x80680000 0x3400 0x20 && " \
	273	"esbc_validate 0x80640000 && " \
	274	"esbc_validate 0x80680000 ;" \
644dc8c4	275	"fsl_mc start mc 0x80a00000 0x80e00000\0" \
d9195c62 AK	276	"mcmemsize=0x70000000\0"
d9195c62 AK	277	#endif
143af3c6	278	#endif /* CONFIG_TFABOOT */
d9195c62	279
099f4093	280	#undef CONFIG_EXTRA_ENV_SETTINGS
143af3c6 PG	281	#ifdef CONFIG_TFABOOT
	282	#define CONFIG_EXTRA_ENV_SETTINGS \
	283	"BOARD=ls1088ardb\0" \
	284	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
	285	"ramdisk_addr=0x800000\0" \
	286	"ramdisk_size=0x2000000\0" \
	287	"fdt_high=0xa0000000\0" \
	288	"initrd_high=0xffffffffffffffff\0" \
	289	"fdt_addr=0x64f00000\0" \
	290	"kernel_addr=0x1000000\0" \
	291	"kernel_addr_sd=0x8000\0" \
4238e373	292	"kernelhdr_addr_sd=0x3000\0" \
143af3c6	293	"kernel_start=0x580100000\0" \
4238e373	294	"kernelheader_start=0x580600000\0" \
143af3c6 PG	295	"scriptaddr=0x80000000\0" \
	296	"scripthdraddr=0x80080000\0" \
	297	"fdtheader_addr_r=0x80100000\0" \
4238e373	298	"kernelheader_addr=0x600000\0" \
143af3c6 PG	299	"kernelheader_addr_r=0x80200000\0" \
	300	"kernel_addr_r=0x81000000\0" \
	301	"kernelheader_size=0x40000\0" \
	302	"fdt_addr_r=0x90000000\0" \
	303	"load_addr=0xa0000000\0" \
	304	"kernel_size=0x2800000\0" \
	305	"kernel_size_sd=0x14000\0" \
d749bf99	306	"kernelhdr_size_sd=0x20\0" \
143af3c6 PG	307	QSPI_MC_INIT_CMD \
	308	"mcmemsize=0x70000000\0" \
	309	BOOTENV \
	310	"boot_scripts=ls1088ardb_boot.scr\0" \
	311	"boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
	312	"scan_dev_for_boot_part=" \
	313	"part list ${devtype} ${devnum} devplist; " \
	314	"env exists devplist \|\| setenv devplist 1; " \
	315	"for distro_bootpart in ${devplist}; do " \
	316	"if fstype ${devtype} " \
	317	"${devnum}:${distro_bootpart} " \
	318	"bootfstype; then " \
	319	"run scan_dev_for_boot; " \
	320	"fi; " \
	321	"done\0" \
143af3c6 PG	322	"boot_a_script=" \
	323	"load ${devtype} ${devnum}:${distro_bootpart} " \
	324	"${scriptaddr} ${prefix}${script}; " \
	325	"env exists secureboot && load ${devtype} " \
	326	"${devnum}:${distro_bootpart} " \
78c58082 VP	327	"${scripthdraddr} ${prefix}${boot_script_hdr}; "\
78c58082 VP	328	"env exists secureboot " \
143af3c6 PG	329	"&& esbc_validate ${scripthdraddr};" \
	330	"source ${scriptaddr}\0" \
	331	"installer=load mmc 0:2 $load_addr " \
	332	"/flex_installer_arm64.itb; " \
	333	"env exists mcinitcmd && run mcinitcmd && " \
	334	"mmc read 0x80001000 0x6800 0x800;" \
	335	"fsl_mc lazyapply dpl 0x80001000;" \
	336	"bootm $load_addr#ls1088ardb\0" \
	337	"qspi_bootcmd=echo Trying load from qspi..;" \
	338	"sf probe && sf read $load_addr " \
	339	"$kernel_addr $kernel_size ; env exists secureboot " \
	340	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	341	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
	342	"bootm $load_addr#$BOARD\0" \
	343	"sd_bootcmd=echo Trying load from sd card..;" \
	344	"mmcinfo; mmc read $load_addr " \
	345	"$kernel_addr_sd $kernel_size_sd ;" \
	346	"env exists secureboot && mmc read $kernelheader_addr_r "\
	347	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	348	" && esbc_validate ${kernelheader_addr_r};" \
	349	"bootm $load_addr#$BOARD\0"
	350	#else
099f4093	351	#define CONFIG_EXTRA_ENV_SETTINGS \
d9195c62	352	"BOARD=ls1088ardb\0" \
099f4093	353	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
099f4093 AK	354	"ramdisk_addr=0x800000\0" \
	355	"ramdisk_size=0x2000000\0" \
	356	"fdt_high=0xa0000000\0" \
	357	"initrd_high=0xffffffffffffffff\0" \
d9195c62 AK	358	"fdt_addr=0x64f00000\0" \
	359	"kernel_addr=0x1000000\0" \
	360	"kernel_addr_sd=0x8000\0" \
4238e373	361	"kernelhdr_addr_sd=0x3000\0" \
d9195c62 AK	362	"kernel_start=0x580100000\0" \
	363	"kernelheader_start=0x580800000\0" \
	364	"scriptaddr=0x80000000\0" \
	365	"scripthdraddr=0x80080000\0" \
	366	"fdtheader_addr_r=0x80100000\0" \
4238e373	367	"kernelheader_addr=0x600000\0" \
d9195c62 AK	368	"kernelheader_addr_r=0x80200000\0" \
	369	"kernel_addr_r=0x81000000\0" \
	370	"kernelheader_size=0x40000\0" \
	371	"fdt_addr_r=0x90000000\0" \
	372	"load_addr=0xa0000000\0" \
	373	"kernel_size=0x2800000\0" \
	374	"kernel_size_sd=0x14000\0" \
d749bf99	375	"kernelhdr_size_sd=0x20\0" \
d9195c62 AK	376	MC_INIT_CMD \
	377	BOOTENV \
	378	"boot_scripts=ls1088ardb_boot.scr\0" \
	379	"boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
	380	"scan_dev_for_boot_part=" \
	381	"part list ${devtype} ${devnum} devplist; " \
	382	"env exists devplist \|\| setenv devplist 1; " \
	383	"for distro_bootpart in ${devplist}; do " \
	384	"if fstype ${devtype} " \
	385	"${devnum}:${distro_bootpart} " \
	386	"bootfstype; then " \
	387	"run scan_dev_for_boot; " \
	388	"fi; " \
	389	"done\0" \
d9195c62 AK	390	"boot_a_script=" \
	391	"load ${devtype} ${devnum}:${distro_bootpart} " \
	392	"${scriptaddr} ${prefix}${script}; " \
	393	"env exists secureboot && load ${devtype} " \
	394	"${devnum}:${distro_bootpart} " \
	395	"${scripthdraddr} ${prefix}${boot_script_hdr} " \
	396	"&& esbc_validate ${scripthdraddr};" \
	397	"source ${scriptaddr}\0" \
	398	"installer=load mmc 0:2 $load_addr " \
	399	"/flex_installer_arm64.itb; " \
	400	"env exists mcinitcmd && run mcinitcmd && " \
f4ef476d JG	401	"mmc read 0x80001000 0x6800 0x800;" \
f4ef476d JG	402	"fsl_mc lazyapply dpl 0x80001000;" \
d9195c62 AK	403	"bootm $load_addr#ls1088ardb\0" \
	404	"qspi_bootcmd=echo Trying load from qspi..;" \
	405	"sf probe && sf read $load_addr " \
30c41d21 UA	406	"$kernel_addr $kernel_size ; env exists secureboot " \
	407	"&& sf read $kernelheader_addr_r $kernelheader_addr " \
	408	"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
d9195c62	409	"bootm $load_addr#$BOARD\0" \
30c41d21	410	"sd_bootcmd=echo Trying load from sd card..;" \
d9195c62 AK	411	"mmcinfo; mmc read $load_addr " \
d9195c62 AK	412	"$kernel_addr_sd $kernel_size_sd ;" \
30c41d21 UA	413	"env exists secureboot && mmc read $kernelheader_addr_r "\
	414	"$kernelhdr_addr_sd $kernelhdr_size_sd " \
	415	" && esbc_validate ${kernelheader_addr_r};" \
d9195c62	416	"bootm $load_addr#$BOARD\0"
143af3c6	417	#endif /* CONFIG_TFABOOT */
d9195c62	418
143af3c6 PG	419	#ifdef CONFIG_TFABOOT
143af3c6 PG	420	#define QSPI_NOR_BOOTCOMMAND \
d749bf99	421	"sf read 0x80001000 0xd00000 0x100000;" \
143af3c6	422	"env exists mcinitcmd && env exists secureboot " \
4238e373 PS	423	" && sf read 0x806C0000 0x6C0000 0x100000 " \
4238e373 PS	424	"&& esbc_validate 0x806C0000;env exists mcinitcmd " \
143af3c6 PG	425	"&& fsl_mc lazyapply dpl 0x80001000;" \
	426	"run distro_bootcmd;run qspi_bootcmd;" \
	427	"env exists secureboot && esbc_halt;"
	428	#define SD_BOOTCOMMAND \
	429	"env exists mcinitcmd && mmcinfo; " \
	430	"mmc read 0x80001000 0x6800 0x800; " \
	431	"env exists mcinitcmd && env exists secureboot " \
4238e373 PS	432	" && mmc read 0x806C0000 0x3600 0x20 " \
4238e373 PS	433	"&& esbc_validate 0x806C0000;env exists mcinitcmd " \
143af3c6 PG	434	"&& fsl_mc lazyapply dpl 0x80001000;" \
	435	"run distro_bootcmd;run sd_bootcmd;" \
	436	"env exists secureboot && esbc_halt;"
	437	#else
d9195c62 AK	438	#if defined(CONFIG_QSPI_BOOT)
d9195c62 AK	439	/* Try to boot an on-QSPI kernel first, then do normal distro boot */
30c41d21	440
d9195c62	441	/* Try to boot an on-SD kernel first, then do normal distro boot */
e84a324b	442	#endif
143af3c6	443	#endif /* CONFIG_TFABOOT */
e84a324b AK	444
	445	/* MAC/PHY configuration */
	446	#ifdef CONFIG_FSL_MC_ENET
e84a324b AK	447	#define AQ_PHY_ADDR1 0x00
	448	#define AQR105_IRQ_MASK 0x00000004
	449
	450	#define QSGMII1_PORT1_PHY_ADDR 0x0c
	451	#define QSGMII1_PORT2_PHY_ADDR 0x0d
	452	#define QSGMII1_PORT3_PHY_ADDR 0x0e
	453	#define QSGMII1_PORT4_PHY_ADDR 0x0f
	454	#define QSGMII2_PORT1_PHY_ADDR 0x1c
	455	#define QSGMII2_PORT2_PHY_ADDR 0x1d
	456	#define QSGMII2_PORT3_PHY_ADDR 0x1e
	457	#define QSGMII2_PORT4_PHY_ADDR 0x1f
	458
e84a324b	459	#define CONFIG_ETHPRIME "DPMAC1@xgmii"
e84a324b	460	#endif
10e7eaf0	461	#endif
e84a324b	462
10e7eaf0	463	#ifndef SPL_NO_ENV
e84a324b AK	464
e84a324b AK	465	#define BOOT_TARGET_DEVICES(func) \
e84a324b	466	func(MMC, mmc, 0) \
e08bcc0e	467	func(USB, usb, 0) \
080c951a MYK	468	func(SCSI, scsi, 0) \
080c951a MYK	469	func(DHCP, dhcp, na)
e84a324b	470	#include <config_distro_bootcmd.h>
10e7eaf0	471	#endif
e84a324b AK	472
	473	#include <asm/fsl_secure_boot.h>
	474
	475	#endif /* __LS1088A_RDB_H */