[J-u-boot.git] / include / configs / M5249EVB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the esd TASREG board.
 *
 * (C) Copyright 2004
 * Stefan Roese, esd gmbh germany, [email protected]
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5249EVB_H
#define _M5249EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFTMR

#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */

/*
 * BOOTP options
 */
#undef CONFIG_BOOTP_BOOTFILESIZE

/*
 * Clock configuration: enable only one of the following options
 */

#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define	CONFIG_SYS_MBAR2		0x80000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)

#if 0 /* test-only */
#define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(2) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */

/* CS0 - AMD Flash, address 0xffc00000 */
#define	CONFIG_SYS_CS0_BASE		0xffe00000
#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */

/* CS1 - FPGA, address 0xe0000000 */
#define	CONFIG_SYS_CS1_BASE		0xe0000000
#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */

#endif	/* M5249 */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
a605aacd TL	2	/*
	3	* Configuation settings for the esd TASREG board.
	4	*
	5	* (C) Copyright 2004
	6	* Stefan Roese, esd gmbh germany, [email protected]
a605aacd TL	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M5249EVB_H
	14	#define _M5249EVB_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
a605aacd TL	20	#define CONFIG_MCFTMR
a605aacd TL	21
6d0f6bcf	22	#define CONFIG_SYS_UART_PORT (0)
a605aacd	23
a605aacd TL	24	#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
	25
	26	/*
	27	* BOOTP options
	28	*/
	29	#undef CONFIG_BOOTP_BOOTFILESIZE
a605aacd	30
a605aacd TL	31	/*
	32	* Clock configuration: enable only one of the following options
	33	*/
	34
6d0f6bcf JCPV	35	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	36	#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
	37	#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
a605aacd TL	38
	39	/*
	40	* Low Level Configuration Settings
	41	* (address mappings, register initial values, etc.)
	42	* You should know what you are doing if you make changes here.
	43	*/
	44
6d0f6bcf JCPV	45	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	46	#define CONFIG_SYS_MBAR2 0x80000000
a605aacd TL	47
	48	/*-----------------------------------------------------------------------
	49	* Definitions for initial stack pointer and data area (in DPRAM)
	50	*/
6d0f6bcf	51	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	52	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	53	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	54	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a605aacd	55
5296cb1d	56	#define LDS_BOARD_TEXT \
0649cd0d SG	57	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	58	env/embedded.o(.text);
5296cb1d	59
a605aacd TL	60	/*-----------------------------------------------------------------------
	61	* Start addresses for the final memory configuration
	62	* (Set up by the startup code)
6d0f6bcf	63	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a605aacd	64	*/
6d0f6bcf JCPV	65	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	66	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	67	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
a605aacd TL	68
	69	#if 0 /* test-only */
	70	#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
	71	#endif
	72
6d0f6bcf	73	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a605aacd	74
6d0f6bcf	75	#define CONFIG_SYS_MONITOR_LEN 0x20000
6d0f6bcf	76	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a605aacd TL	77
	78	/*
	79	* For booting Linux, the board info and command line data
	80	* have to be in the first 8 MB of memory, since this is
	81	* the maximum mapped by the Linux kernel during initialization ??
	82	*/
6d0f6bcf	83	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
a605aacd TL	84
	85	/*-----------------------------------------------------------------------
	86	* FLASH organization
	87	*/
6d0f6bcf	88	#ifdef CONFIG_SYS_FLASH_CFI
a605aacd	89
6d0f6bcf JCPV	90	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
6d0f6bcf JCPV	91	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d0f6bcf	92	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
6d0f6bcf JCPV	93	# define CONFIG_SYS_FLASH_CHECKSUM
6d0f6bcf JCPV	94	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
a605aacd TL	95	#endif
	96
	97	/*-----------------------------------------------------------------------
	98	* Cache Configuration
	99	*/
a605aacd	100
dd9f054e	101	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	102	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	103	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	104	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	105	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	106	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	107	CF_ADDRMASK(2) \| \
	108	CF_ACR_EN \| CF_ACR_SM_ALL)
	109	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	110	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	111	CF_ACR_EN \| CF_ACR_SM_ALL)
	112	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	113	CF_CACR_DBWE)
	114
a605aacd TL	115	/*-----------------------------------------------------------------------
	116	* Memory bank definitions
	117	*/
	118
	119	/* CS0 - AMD Flash, address 0xffc00000 */
012522fe TL	120	#define CONFIG_SYS_CS0_BASE 0xffe00000
012522fe TL	121	#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
a605aacd	122	/ Note: There is a CSMR0/DRAM vector problem, need to disable C/I */
012522fe	123	#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
a605aacd TL	124
a605aacd TL	125	/* CS1 - FPGA, address 0xe0000000 */
012522fe TL	126	#define CONFIG_SYS_CS1_BASE 0xe0000000
	127	#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
	128	#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
a605aacd TL	129
	130	/*-----------------------------------------------------------------------
	131	* Port configuration
	132	*/
6d0f6bcf JCPV	133	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	134	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
	135	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	136	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	137	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	138	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	139	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a605aacd TL	140
a605aacd TL	141	#endif /* M5249 */