[J-u-boot.git] / include / configs / woodburn_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2011, Stefano Babic <[email protected]>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Configuration for the woodburn board.
 */

#ifndef __WOODBURN_COMMON_CONFIG_H
#define __WOODBURN_COMMON_CONFIG_H

#include <asm/arch/imx-regs.h>

 /* High Level Configuration Options */
#define CONFIG_MX35
#define CONFIG_MX35_HCLK_FREQ	24000000
#define CONFIG_SYS_FSL_CLK

#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3

/* This is required to setup the ESDC controller */

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)

/*
 * Hardware drivers
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
#define CONFIG_SYS_SPD_BUS_NUM		0

/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_FSL
#define CONFIG_POWER_FSL_MC13892
#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
#define CONFIG_RTC_MC13XXX

/* mmc driver */
#define CONFIG_SYS_FSL_ESDHC_ADDR	0
#define CONFIG_SYS_FSL_ESDHC_NUM	1

/*
 * UART (console)
 */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE	UART1_BASE

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/*
 * Command definition
 */

#define CONFIG_NET_RETRY_COUNT	100


#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */

/*
 * Ethernet on SOC (FEC)
 */
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE	FEC_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR	0x1

#define CONFIG_DISCOVER_PHY

#define CONFIG_ARP_TIMEOUT	200UL

/*
 * Miscellaneous configurable options
 */

#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x10000

#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR

/*
 * Physical Memory Map
 */
#define PHYS_SDRAM_1		CSD0_BASE_ADDR
#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)

#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR

#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
						IRAM_BASE_ADDR - \
						GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
					CONFIG_SYS_GBL_DATA_OFFSET)

/*
 * MTD Command for mtdparts
 */

/*
 * FLASH and environment organization
 */
#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				CONFIG_SYS_MONITOR_LEN)

/*
 * CFI FLASH driver setup
 */

/* A non-standard buffered write algorithm */

/*
 * NAND FLASH driver setup
 */
#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE

#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * Default environment and default scripts
 * to update uboot and load kernel
 */

#define CONFIG_HOSTNAME "woodburn"
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"	\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttymxc0,${baudrate}\0"			\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=80800000\0"						\
	"kernel_addr_r=80800000\0"					\
	"hostname=" CONFIG_HOSTNAME "\0"			\
	"bootfile=" CONFIG_HOSTNAME "/uImage\0"		\
	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0"	\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
	"update=protect off ${uboot_addr} +80000;"			\
		"erase ${uboot_addr} +80000;"				\
		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\
	"bootcmd=run net_nfs\0"

#endif				/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
d81b27a2 SB	2	/*
	3	* (C) Copyright 2011, Stefano Babic <[email protected]>
	4	*
	5	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	6	*
	7	* Configuration for the woodburn board.
d81b27a2 SB	8	*/
	9
	10	#ifndef __WOODBURN_COMMON_CONFIG_H
	11	#define __WOODBURN_COMMON_CONFIG_H
	12
	13	#include <asm/arch/imx-regs.h>
	14
	15	/* High Level Configuration Options */
d81b27a2 SB	16	#define CONFIG_MX35
d81b27a2 SB	17	#define CONFIG_MX35_HCLK_FREQ 24000000
18fb0e3c	18	#define CONFIG_SYS_FSL_CLK
d81b27a2	19
d81b27a2 SB	20	#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
	21
	22	/* This is required to setup the ESDC controller */
	23
	24	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	25	#define CONFIG_REVISION_TAG
	26	#define CONFIG_SETUP_MEMORY_TAGS
	27	#define CONFIG_INITRD_TAG
	28
	29	/*
	30	* Size of malloc() pool
	31	*/
	32	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
	33
	34	/*
	35	* Hardware drivers
	36	*/
b089d039	37	#define CONFIG_SYS_I2C
b089d039	38	#define CONFIG_SYS_I2C_MXC
03544c66 AA	39	#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
03544c66 AA	40	#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e	41	#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
b089d039	42	#define CONFIG_SYS_SPD_BUS_NUM 0
d81b27a2 SB	43
d81b27a2 SB	44	/* PMIC Controller */
05a860c2 SB	45	#define CONFIG_POWER
	46	#define CONFIG_POWER_I2C
	47	#define CONFIG_POWER_FSL
913702ca	48	#define CONFIG_POWER_FSL_MC13892
d81b27a2 SB	49	#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
	50	#define CONFIG_RTC_MC13XXX
	51
d81b27a2	52	/* mmc driver */
d81b27a2 SB	53	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	54	#define CONFIG_SYS_FSL_ESDHC_NUM 1
	55
	56	/*
	57	* UART (console)
	58	*/
	59	#define CONFIG_MXC_UART
	60	#define CONFIG_MXC_UART_BASE UART1_BASE
	61
	62	/* allow to overwrite serial and ethaddr */
	63	#define CONFIG_ENV_OVERWRITE
d81b27a2 SB	64
	65	/*
	66	* Command definition
	67	*/
d81b27a2	68
d81b27a2 SB	69	#define CONFIG_NET_RETRY_COUNT 100
d81b27a2 SB	70
d81b27a2 SB	71
	72	#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
	73
d81b27a2 SB	74	/*
	75	* Ethernet on SOC (FEC)
	76	*/
	77	#define CONFIG_FEC_MXC
	78	#define IMX_FEC_BASE FEC_BASE_ADDR
d81b27a2 SB	79	#define CONFIG_FEC_MXC_PHYADDR 0x1
d81b27a2 SB	80
d81b27a2 SB	81	#define CONFIG_DISCOVER_PHY
	82
	83	#define CONFIG_ARP_TIMEOUT 200UL
	84
	85	/*
	86	* Miscellaneous configurable options
	87	*/
d81b27a2 SB	88
	89	#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
	90	#define CONFIG_SYS_MEMTEST_END 0x10000
	91
d81b27a2 SB	92	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
d81b27a2 SB	93
d81b27a2 SB	94	/*
	95	* Physical Memory Map
	96	*/
d81b27a2 SB	97	#define PHYS_SDRAM_1 CSD0_BASE_ADDR
	98	#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
	99
	100	#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
	101
	102	#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
	103	IRAM_BASE_ADDR - \
	104	GENERATED_GBL_DATA_SIZE)
	105	#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
	106	CONFIG_SYS_GBL_DATA_OFFSET)
	107
	108	/*
	109	* MTD Command for mtdparts
	110	*/
d81b27a2 SB	111
	112	/*
	113	* FLASH and environment organization
	114	*/
	115	#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	117	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
	118	/* Monitor at beginning of flash */
	119	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	120	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	121
	122	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
	123	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	124
	125	/* Address and size of Redundant Environment Sector */
	126	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
	127	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	128
	129	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	130	CONFIG_SYS_MONITOR_LEN)
	131
d81b27a2 SB	132	/*
	133	* CFI FLASH driver setup
	134	*/
d81b27a2 SB	135
d81b27a2 SB	136	/* A non-standard buffered write algorithm */
d81b27a2 SB	137
	138	/*
	139	* NAND FLASH driver setup
	140	*/
d81b27a2 SB	141	#define CONFIG_NAND_MXC_V1_1
	142	#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
	143	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	144	#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
	145	#define CONFIG_MXC_NAND_HWECC
	146	#define CONFIG_SYS_NAND_LARGEPAGE
	147
d81b27a2 SB	148	#define CONFIG_SYS_NAND_ONFI_DETECTION
	149
	150	/*
	151	* Default environment and default scripts
	152	* to update uboot and load kernel
	153	*/
d81b27a2	154
5bc0543d	155	#define CONFIG_HOSTNAME "woodburn"
d81b27a2 SB	156	#define CONFIG_EXTRA_ENV_SETTINGS \
	157	"netdev=eth0\0" \
	158	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	159	"nfsroot=${serverip}:${rootpath}\0" \
	160	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	161	"addip_sta=setenv bootargs ${bootargs} " \
	162	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	163	":${hostname}:${netdev}:off panic=1\0" \
	164	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	165	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	166	"else run addip_sta;fi\0" \
	167	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	168	"addtty=setenv bootargs ${bootargs}" \
	169	" console=ttymxc0,${baudrate}\0" \
	170	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	171	"loadaddr=80800000\0" \
	172	"kernel_addr_r=80800000\0" \
5bc0543d MS	173	"hostname=" CONFIG_HOSTNAME "\0" \
	174	"bootfile=" CONFIG_HOSTNAME "/uImage\0" \
	175	"ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
d81b27a2 SB	176	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	177	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	178	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	179	"bootm ${kernel_addr}\0" \
	180	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	181	"run nfsargs addip addtty addmtd addmisc;" \
	182	"bootm ${kernel_addr_r}\0" \
	183	"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
	184	"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
	185	"net_self=if run net_self_load;then " \
	186	"run ramargs addip addtty addmtd addmisc;" \
	187	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	188	"else echo Images not loades;fi\0" \
5bc0543d	189	"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
d81b27a2	190	"load=tftp ${loadaddr} ${u-boot}\0" \
4a8c3f69	191	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
d81b27a2 SB	192	"update=protect off ${uboot_addr} +80000;" \
	193	"erase ${uboot_addr} +80000;" \
	194	"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
	195	"upd=if run load;then echo Updating u-boot;if run update;" \
	196	"then echo U-Boot updated;" \
	197	"else echo Error updating u-boot !;" \
	198	"echo Board without bootloader !!;" \
	199	"fi;" \
	200	"else echo U-Boot not downloaded..exiting;fi\0" \
	201	"bootcmd=run net_nfs\0"
	202
	203	#endif /* __CONFIG_H */