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[J-u-boot.git] / include / configs / ls2080ardb.h
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83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
e2b65ea9 2/*
89a168f7 3 * Copyright 2017 NXP
e2b65ea9 4 * Copyright 2015 Freescale Semiconductor
e2b65ea9
YS		 5 */
6
7#ifndef __LS2_RDB_H
8#define __LS2_RDB_H
9
44937214 10#include "ls2080a_common.h"
e2b65ea9 11
89a168f7 12#ifdef CONFIG_FSL_QSPI
3049a583
PJ		 13#ifdef CONFIG_TARGET_LS2081ARDB
14#define CONFIG_QIXIS_I2C_ACCESS
15#endif
89a168f7 16#define CONFIG_SYS_I2C_EARLY_INIT
89a168f7
PJ		 17#endif
18
ed2530d0
RH		 19#define I2C_MUX_CH_VOL_MONITOR 0xa
20#define I2C_VOL_MONITOR_ADDR 0x38
21#define CONFIG_VOL_MONITOR_IR36021_READ
22#define CONFIG_VOL_MONITOR_IR36021_SET
23
24#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
25#ifndef CONFIG_SPL_BUILD
26#define CONFIG_VID
27#endif
28/* step the IR regulator in 5mV increments */
29#define IR_VDD_STEP_DOWN 5
30#define IR_VDD_STEP_UP 5
31/* The lowest and highest voltage allowed for LS2080ARDB */
32#define VDD_MV_MIN 819
33#define VDD_MV_MAX 1212
34
e2b65ea9
YS		 35#ifndef __ASSEMBLY__
36unsigned long get_board_sys_clk(void);
37#endif
38
39#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
40#define CONFIG_DDR_CLK_FREQ 133333333
41#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
42
43#define CONFIG_DDR_SPD
44#define CONFIG_DDR_ECC
45#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47#define SPD_EEPROM_ADDRESS1 0x51
48#define SPD_EEPROM_ADDRESS2 0x52
fc7b3855
YS		 49#define SPD_EEPROM_ADDRESS3 0x53
50#define SPD_EEPROM_ADDRESS4 0x54
e2b65ea9
YS		 51#define SPD_EEPROM_ADDRESS5 0x55
52#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
53#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
54#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
55#define CONFIG_DIMM_SLOTS_PER_CTLR 2
56#define CONFIG_CHIP_SELECTS_PER_CTRL 4
44937214 57#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
e2b65ea9 58#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
44937214 59#endif
e2b65ea9 60
989c5f0a 61/* SATA */
989c5f0a 62#define CONFIG_SCSI_AHCI_PLAT
989c5f0a
TY		 63
64#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
65#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
66
67#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
68#define CONFIG_SYS_SCSI_MAX_LUN 1
69#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
70 CONFIG_SYS_SCSI_MAX_LUN)
9570df03
RB		 71#ifdef CONFIG_TFABOOT
72#define CONFIG_SYS_MMC_ENV_DEV 0
989c5f0a 73
9570df03
RB		 74#define CONFIG_ENV_SIZE 0x2000
75#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
76#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
77 CONFIG_ENV_OFFSET)
78#define CONFIG_ENV_SECT_SIZE 0x40000
79#endif
80
81#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
e2b65ea9
YS		 82
83#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
84#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
85#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
86
87#define CONFIG_SYS_NOR0_CSPR \
88 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
89 CSPR_PORT_SIZE_16 | \
90 CSPR_MSEL_NOR | \
91 CSPR_V)
92#define CONFIG_SYS_NOR0_CSPR_EARLY \
93 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
94 CSPR_PORT_SIZE_16 | \
95 CSPR_MSEL_NOR | \
96 CSPR_V)
97#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
98#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
99 FTIM0_NOR_TEADC(0x5) | \
100 FTIM0_NOR_TEAHC(0x5))
101#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
102 FTIM1_NOR_TRAD_NOR(0x1a) |\
103 FTIM1_NOR_TSEQRAD_NOR(0x13))
104#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
105 FTIM2_NOR_TCH(0x4) | \
106 FTIM2_NOR_TWPH(0x0E) | \
107 FTIM2_NOR_TWP(0x1c))
108#define CONFIG_SYS_NOR_FTIM3 0x04000000
109#define CONFIG_SYS_IFC_CCR 0x01000000
110
e856bdcf 111#ifdef CONFIG_MTD_NOR_FLASH
e2b65ea9
YS		 112#define CONFIG_SYS_FLASH_QUIET_TEST
113#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
114
115#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
116#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
117#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
119
120#define CONFIG_SYS_FLASH_EMPTY_INFO
121#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
122 CONFIG_SYS_FLASH_BASE + 0x40000000}
123#endif
124
125#define CONFIG_NAND_FSL_IFC
126#define CONFIG_SYS_NAND_MAX_ECCPOS 256
127#define CONFIG_SYS_NAND_MAX_OOBFREE 2
128
e2b65ea9
YS		 129#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
130#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
131 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
132 | CSPR_MSEL_NAND /* MSEL = NAND */ \
133 | CSPR_V)
134#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
135
136#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
137 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
138 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
139 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
140 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
141 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
142 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
143
144#define CONFIG_SYS_NAND_ONFI_DETECTION
145
146/* ONFI NAND Flash mode0 Timing Params */
147#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
148 FTIM0_NAND_TWP(0x30) | \
149 FTIM0_NAND_TWCHT(0x0e) | \
150 FTIM0_NAND_TWH(0x14))
151#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
152 FTIM1_NAND_TWBE(0xab) | \
153 FTIM1_NAND_TRR(0x1c) | \
154 FTIM1_NAND_TRP(0x30))
155#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
156 FTIM2_NAND_TREH(0x14) | \
157 FTIM2_NAND_TWHRE(0x3c))
158#define CONFIG_SYS_NAND_FTIM3 0x0
159
160#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
161#define CONFIG_SYS_MAX_NAND_DEVICE 1
162#define CONFIG_MTD_NAND_VERIFY_WRITE
e2b65ea9
YS		 163
164#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
e2b65ea9
YS		 165#define CONFIG_FSL_QIXIS /* use common QIXIS code */
166#define QIXIS_LBMAP_SWITCH 0x06
167#define QIXIS_LBMAP_MASK 0x0f
168#define QIXIS_LBMAP_SHIFT 0
169#define QIXIS_LBMAP_DFLTBANK 0x00
170#define QIXIS_LBMAP_ALTBANK 0x04
32eda7cc 171#define QIXIS_LBMAP_NAND 0x09
e2b65ea9
YS		 172#define QIXIS_RST_CTL_RESET 0x31
173#define QIXIS_RST_CTL_RESET_EN 0x30
174#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
175#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
176#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
32eda7cc 177#define QIXIS_RCW_SRC_NAND 0x119
e2b65ea9
YS		 178#define QIXIS_RST_FORCE_MEM 0x01
179
180#define CONFIG_SYS_CSPR3_EXT (0x0)
181#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
182 | CSPR_PORT_SIZE_8 \
183 | CSPR_MSEL_GPCM \
184 | CSPR_V)
185#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
186 | CSPR_PORT_SIZE_8 \
187 | CSPR_MSEL_GPCM \
188 | CSPR_V)
189
190#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
191#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
192/* QIXIS Timing parameters for IFC CS3 */
193#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
194 FTIM0_GPCM_TEADC(0x0e) | \
195 FTIM0_GPCM_TEAHC(0x0e))
196#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
197 FTIM1_GPCM_TRAD(0x3f))
198#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
199 FTIM2_GPCM_TCH(0xf) | \
200 FTIM2_GPCM_TWP(0x3E))
201#define CONFIG_SYS_CS3_FTIM3 0x0
202
32eda7cc
SW		 203#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
204#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
205#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
206#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
207#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
208#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
209#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
210#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
211#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
212#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
213#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
214#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
215#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
216#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
217#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
218#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
219#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
220#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
221
9570df03 222#ifndef CONFIG_TFABOOT
32eda7cc
SW		 223#define CONFIG_ENV_OFFSET (2048 * 1024)
224#define CONFIG_ENV_SECT_SIZE 0x20000
225#define CONFIG_ENV_SIZE 0x2000
9570df03 226#endif
32eda7cc
SW		 227#define CONFIG_SPL_PAD_TO 0x80000
228#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024)
229#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
230#else
e2b65ea9
YS		 231#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
232#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
233#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
234#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
235#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
236#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
237#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
238#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
239#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
240#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
241#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
242#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
243#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
244#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
245#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
246#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
247#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
248
9570df03 249#ifndef CONFIG_TFABOOT
f5bf23d8 250#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
32eda7cc
SW		 251#define CONFIG_ENV_SECT_SIZE 0x20000
252#define CONFIG_ENV_SIZE 0x2000
253#endif
9570df03 254#endif
32eda7cc 255
e2b65ea9
YS		 256/* Debug Server firmware */
257#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
258#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
89a168f7 259#endif
e2b65ea9
YS		 260#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
261
3049a583
PJ		 262#ifdef CONFIG_TARGET_LS2081ARDB
263#define CONFIG_FSL_QIXIS /* use common QIXIS code */
264#define QIXIS_QMAP_MASK 0x07
265#define QIXIS_QMAP_SHIFT 5
266#define QIXIS_LBMAP_DFLTBANK 0x00
267#define QIXIS_LBMAP_QSPI 0x00
268#define QIXIS_RCW_SRC_QSPI 0x62
269#define QIXIS_LBMAP_ALTBANK 0x20
270#define QIXIS_RST_CTL_RESET 0x31
271#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
272#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
273#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
274#define QIXIS_LBMAP_MASK 0x0f
275#define QIXIS_RST_CTL_RESET_EN 0x30
276#endif
277
e2b65ea9
YS		 278/*
279 * I2C
280 */
3049a583
PJ		 281#ifdef CONFIG_TARGET_LS2081ARDB
282#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
283#endif
4012350d
PK		 284#define I2C_MUX_PCA_ADDR 0x75
285#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
e2b65ea9
YS		 286
287/* I2C bus multiplexer */
288#define I2C_MUX_CH_DEFAULT 0x8
289
0c42a8de 290/* SPI */
89a168f7 291#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
77dc01bd 292#ifdef CONFIG_FSL_DSPI
21640db5 293#define CONFIG_SPI_FLASH_STMICRO
0c42a8de 294#endif
89a168f7
PJ		 295#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
296#define FSL_QSPI_FLASH_NUM 2
297#endif
0c42a8de 298
e2b65ea9
YS		 299/*
300 * RTC configuration
301 */
302#define RTC
3049a583
PJ		 303#ifdef CONFIG_TARGET_LS2081ARDB
304#define CONFIG_RTC_PCF8563 1
305#define CONFIG_SYS_I2C_RTC_ADDR 0x51
306#else
e2b65ea9
YS		 307#define CONFIG_RTC_DS3231 1
308#define CONFIG_SYS_I2C_RTC_ADDR 0x68
3049a583 309#endif
e2b65ea9
YS		 310
311/* EEPROM */
312#define CONFIG_ID_EEPROM
e2b65ea9
YS		 313#define CONFIG_SYS_I2C_EEPROM_NXID
314#define CONFIG_SYS_EEPROM_BUS_NUM 0
315#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
316#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
317#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
318#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
319
e2b65ea9 320#define CONFIG_FSL_MEMAC
e2b65ea9
YS		 321
322#ifdef CONFIG_PCI
e2b65ea9 323#define CONFIG_PCI_SCAN_SHOW
e2b65ea9
YS		 324#endif
325
8b06460e 326/* MMC */
8b06460e 327#ifdef CONFIG_MMC
8b06460e 328#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
8b06460e 329#endif
e2b65ea9 330
b99ebaf9
AG		 331#define BOOT_TARGET_DEVICES(func) \
332 func(USB, usb, 0) \
333 func(MMC, mmc, 0) \
e0db2f42
MYK		 334 func(SCSI, scsi, 0) \
335 func(DHCP, dhcp, na)
b99ebaf9
AG		 336#include <config_distro_bootcmd.h>
337
9570df03
RB		 338#ifdef CONFIG_TFABOOT
339#define QSPI_MC_INIT_CMD \
340 "env exists secureboot && " \
341 "esbc_validate 0x20700000 && " \
342 "esbc_validate 0x20740000;" \
343 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
344#define SD_MC_INIT_CMD \
345 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
346 "mmc read 0x80100000 0x7000 0x800;" \
347 "env exists secureboot && " \
348 "mmc read 0x80700000 0x3800 0x10 && " \
349 "mmc read 0x80740000 0x3A00 0x10 && " \
350 "esbc_validate 0x80700000 && " \
351 "esbc_validate 0x80740000 ;" \
352 "fsl_mc start mc 0x80000000 0x80100000\0"
353#define IFC_MC_INIT_CMD \
354 "env exists secureboot && " \
355 "esbc_validate 0x580700000 && " \
356 "esbc_validate 0x580740000; " \
357 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
358#else
ec85721c
VP		 359#ifdef CONFIG_QSPI_BOOT
360#define MC_INIT_CMD \
361 "mcinitcmd=env exists secureboot && " \
362 "esbc_validate 0x20700000 && " \
363 "esbc_validate 0x20740000;" \
364 "fsl_mc start mc 0x20a00000 0x20e00000 \0"
bc085549
SL		 365#elif defined(CONFIG_SD_BOOT)
366#define MC_INIT_CMD \
367 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
368 "mmc read 0x80100000 0x7000 0x800;" \
369 "env exists secureboot && " \
370 "mmc read 0x80700000 0x3800 0x10 && " \
371 "mmc read 0x80740000 0x3A00 0x10 && " \
372 "esbc_validate 0x80700000 && " \
373 "esbc_validate 0x80740000 ;" \
374 "fsl_mc start mc 0x80000000 0x80100000\0" \
375 "mcmemsize=0x70000000\0"
ec85721c
VP		 376#else
377#define MC_INIT_CMD \
378 "mcinitcmd=env exists secureboot && " \
379 "esbc_validate 0x580700000 && " \
380 "esbc_validate 0x580740000; " \
381 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
382#endif
9570df03 383#endif
ec85721c 384
e2b65ea9
YS		 385/* Initial environment variables */
386#undef CONFIG_EXTRA_ENV_SETTINGS
9570df03
RB		 387#ifdef CONFIG_TFABOOT
388#define CONFIG_EXTRA_ENV_SETTINGS \
389 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
390 "ramdisk_addr=0x800000\0" \
391 "ramdisk_size=0x2000000\0" \
392 "fdt_high=0xa0000000\0" \
393 "initrd_high=0xffffffffffffffff\0" \
394 "fdt_addr=0x64f00000\0" \
395 "kernel_addr=0x581000000\0" \
396 "kernel_start=0x1000000\0" \
397 "kernelheader_start=0x800000\0" \
398 "scriptaddr=0x80000000\0" \
399 "scripthdraddr=0x80080000\0" \
400 "fdtheader_addr_r=0x80100000\0" \
401 "kernelheader_addr_r=0x80200000\0" \
402 "kernelheader_addr=0x580800000\0" \
403 "kernel_addr_r=0x81000000\0" \
404 "kernelheader_size=0x40000\0" \
405 "fdt_addr_r=0x90000000\0" \
406 "load_addr=0xa0000000\0" \
407 "kernel_size=0x2800000\0" \
408 "kernel_addr_sd=0x8000\0" \
409 "kernel_size_sd=0x14000\0" \
410 "console=ttyAMA0,38400n8\0" \
411 "mcmemsize=0x70000000\0" \
412 "sd_bootcmd=echo Trying load from SD ..;" \
413 "mmcinfo; mmc read $load_addr " \
414 "$kernel_addr_sd $kernel_size_sd && " \
415 "bootm $load_addr#$board\0" \
416 QSPI_MC_INIT_CMD \
417 BOOTENV \
418 "boot_scripts=ls2088ardb_boot.scr\0" \
419 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
420 "scan_dev_for_boot_part=" \
421 "part list ${devtype} ${devnum} devplist; " \
422 "env exists devplist || setenv devplist 1; " \
423 "for distro_bootpart in ${devplist}; do " \
424 "if fstype ${devtype} " \
425 "${devnum}:${distro_bootpart} " \
426 "bootfstype; then " \
427 "run scan_dev_for_boot; " \
428 "fi; " \
429 "done\0" \
9570df03
RB		 430 "boot_a_script=" \
431 "load ${devtype} ${devnum}:${distro_bootpart} " \
432 "${scriptaddr} ${prefix}${script}; " \
433 "env exists secureboot && load ${devtype} " \
434 "${devnum}:${distro_bootpart} " \
435 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
436 "&& esbc_validate ${scripthdraddr};" \
437 "source ${scriptaddr}\0" \
438 "qspi_bootcmd=echo Trying load from qspi..;" \
439 "sf probe && sf read $load_addr " \
440 "$kernel_start $kernel_size ; env exists secureboot &&" \
441 "sf read $kernelheader_addr_r $kernelheader_start " \
442 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
443 " bootm $load_addr#$board\0" \
444 "nor_bootcmd=echo Trying load from nor..;" \
445 "cp.b $kernel_addr $load_addr " \
446 "$kernel_size ; env exists secureboot && " \
447 "cp.b $kernelheader_addr $kernelheader_addr_r " \
448 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
449 "bootm $load_addr#$board\0"
450#else
e2b65ea9
YS		 451#define CONFIG_EXTRA_ENV_SETTINGS \
452 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
e2b65ea9
YS		 453 "ramdisk_addr=0x800000\0" \
454 "ramdisk_size=0x2000000\0" \
455 "fdt_high=0xa0000000\0" \
456 "initrd_high=0xffffffffffffffff\0" \
0a09d20b 457 "fdt_addr=0x64f00000\0" \
3386c73d 458 "kernel_addr=0x581000000\0" \
ec85721c
VP		 459 "kernel_start=0x1000000\0" \
460 "kernelheader_start=0x800000\0" \
0a09d20b 461 "scriptaddr=0x80000000\0" \
ec85721c 462 "scripthdraddr=0x80080000\0" \
0a09d20b
ZY		 463 "fdtheader_addr_r=0x80100000\0" \
464 "kernelheader_addr_r=0x80200000\0" \
ec85721c 465 "kernelheader_addr=0x580800000\0" \
0a09d20b 466 "kernel_addr_r=0x81000000\0" \
ec85721c 467 "kernelheader_size=0x40000\0" \
0a09d20b
ZY		 468 "fdt_addr_r=0x90000000\0" \
469 "load_addr=0xa0000000\0" \
16ed8560 470 "kernel_size=0x2800000\0" \
bc085549
SL		 471 "kernel_addr_sd=0x8000\0" \
472 "kernel_size_sd=0x14000\0" \
0a09d20b 473 "console=ttyAMA0,38400n8\0" \
8472d876 474 "mcmemsize=0x70000000\0" \
bc085549
SL		 475 "sd_bootcmd=echo Trying load from SD ..;" \
476 "mmcinfo; mmc read $load_addr " \
477 "$kernel_addr_sd $kernel_size_sd && " \
478 "bootm $load_addr#$board\0" \
ec85721c 479 MC_INIT_CMD \
0a09d20b
ZY		 480 BOOTENV \
481 "boot_scripts=ls2088ardb_boot.scr\0" \
ec85721c 482 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
0a09d20b
ZY		 483 "scan_dev_for_boot_part=" \
484 "part list ${devtype} ${devnum} devplist; " \
485 "env exists devplist || setenv devplist 1; " \
486 "for distro_bootpart in ${devplist}; do " \
487 "if fstype ${devtype} " \
488 "${devnum}:${distro_bootpart} " \
489 "bootfstype; then " \
490 "run scan_dev_for_boot; " \
491 "fi; " \
492 "done\0" \
ec85721c
VP		 493 "boot_a_script=" \
494 "load ${devtype} ${devnum}:${distro_bootpart} " \
495 "${scriptaddr} ${prefix}${script}; " \
496 "env exists secureboot && load ${devtype} " \
497 "${devnum}:${distro_bootpart} " \
498 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
499 "&& esbc_validate ${scripthdraddr};" \
500 "source ${scriptaddr}\0" \
0a09d20b
ZY		 501 "qspi_bootcmd=echo Trying load from qspi..;" \
502 "sf probe && sf read $load_addr " \
ec85721c
VP		 503 "$kernel_start $kernel_size ; env exists secureboot &&" \
504 "sf read $kernelheader_addr_r $kernelheader_start " \
505 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
0a09d20b
ZY		 506 " bootm $load_addr#$board\0" \
507 "nor_bootcmd=echo Trying load from nor..;" \
508 "cp.b $kernel_addr $load_addr " \
ec85721c
VP		 509 "$kernel_size ; env exists secureboot && " \
510 "cp.b $kernelheader_addr $kernelheader_addr_r " \
511 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
512 "bootm $load_addr#$board\0"
9570df03
RB		 513#endif
514
515#ifdef CONFIG_TFABOOT
516#define QSPI_NOR_BOOTCOMMAND \
517 "env exists mcinitcmd && env exists secureboot "\
518 "&& esbc_validate 0x20780000; " \
519 "env exists mcinitcmd && " \
520 "fsl_mc lazyapply dpl 0x20d00000; " \
521 "run distro_bootcmd;run qspi_bootcmd; " \
522 "env exists secureboot && esbc_halt;"
523
524/* Try to boot an on-SD kernel first, then do normal distro boot */
525#define SD_BOOTCOMMAND \
526 "env exists mcinitcmd && env exists secureboot "\
527 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
528 "&& esbc_validate $load_addr; " \
529 "env exists mcinitcmd && run mcinitcmd " \
530 "&& mmc read 0x88000000 0x6800 0x800 " \
531 "&& fsl_mc lazyapply dpl 0x88000000; " \
532 "run distro_bootcmd;run sd_bootcmd; " \
533 "env exists secureboot && esbc_halt;"
9ed44787 534
9570df03
RB		 535/* Try to boot an on-NOR kernel first, then do normal distro boot */
536#define IFC_NOR_BOOTCOMMAND \
537 "env exists mcinitcmd && env exists secureboot "\
538 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
539 "&& fsl_mc lazyapply dpl 0x580d00000;" \
540 "run distro_bootcmd;run nor_bootcmd; " \
541 "env exists secureboot && esbc_halt;"
542#else
b99ebaf9 543#undef CONFIG_BOOTCOMMAND
89a168f7 544#ifdef CONFIG_QSPI_BOOT
89a168f7 545/* Try to boot an on-QSPI kernel first, then do normal distro boot */
0a09d20b 546#define CONFIG_BOOTCOMMAND \
ec85721c
VP		 547 "env exists mcinitcmd && env exists secureboot "\
548 "&& esbc_validate 0x20780000; " \
549 "env exists mcinitcmd && " \
550 "fsl_mc lazyapply dpl 0x20d00000; " \
3386c73d
VP		 551 "run distro_bootcmd;run qspi_bootcmd; " \
552 "env exists secureboot && esbc_halt;"
bc085549
SL		 553#elif defined(CONFIG_SD_BOOT)
554/* Try to boot an on-SD kernel first, then do normal distro boot */
555#define CONFIG_BOOTCOMMAND \
556 "env exists mcinitcmd && env exists secureboot "\
557 "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \
558 "&& esbc_validate $load_addr; " \
559 "env exists mcinitcmd && run mcinitcmd " \
560 "&& mmc read 0x88000000 0x6800 0x800 " \
561 "&& fsl_mc lazyapply dpl 0x88000000; " \
3386c73d
VP		 562 "run distro_bootcmd;run sd_bootcmd; " \
563 "env exists secureboot && esbc_halt;"
9ed44787 564#else
b99ebaf9 565/* Try to boot an on-NOR kernel first, then do normal distro boot */
0a09d20b 566#define CONFIG_BOOTCOMMAND \
ec85721c
VP		 567 "env exists mcinitcmd && env exists secureboot "\
568 "&& esbc_validate 0x580780000; env exists mcinitcmd "\
569 "&& fsl_mc lazyapply dpl 0x580d00000;" \
3386c73d
VP		 570 "run distro_bootcmd;run nor_bootcmd; " \
571 "env exists secureboot && esbc_halt;"
89a168f7 572#endif
9570df03 573#endif
9ed44787 574
3484d953
PK		 575/* MAC/PHY configuration */
576#ifdef CONFIG_FSL_MC_ENET
3484d953 577#define CONFIG_PHY_CORTINA
3484d953 578#define CONFIG_SYS_CORTINA_FW_IN_NOR
89a168f7
PJ		 579#ifdef CONFIG_QSPI_BOOT
580#define CONFIG_CORTINA_FW_ADDR 0x20980000
581#else
f5bf23d8 582#define CONFIG_CORTINA_FW_ADDR 0x580980000
89a168f7 583#endif
3484d953
PK		 584#define CONFIG_CORTINA_FW_LENGTH 0x40000
585
586#define CORTINA_PHY_ADDR1 0x10
587#define CORTINA_PHY_ADDR2 0x11
588#define CORTINA_PHY_ADDR3 0x12
589#define CORTINA_PHY_ADDR4 0x13
590#define AQ_PHY_ADDR1 0x00
591#define AQ_PHY_ADDR2 0x01
592#define AQ_PHY_ADDR3 0x02
593#define AQ_PHY_ADDR4 0x03
abc7d0f7 594#define AQR405_IRQ_MASK 0x36
3484d953 595
7ad9cc96 596#define CONFIG_ETHPRIME "DPMAC1@xgmii"
3484d953
PK		 597#endif
598
fcfdb6d5
SJ		 599#include <asm/fsl_secure_boot.h>
600
e2b65ea9 601#endif /* __LS2_RDB_H */
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