[J-u-boot.git] / include / configs / M5235EVB.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Configuation settings for the Freescale MCF5329 FireEngine board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew ([email protected])
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5235EVB_H
#define _M5235EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_i2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTFILE		"u-boot.bin"
#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		"M5235EVB"
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)

#define CONFIG_SYS_CLK			75000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0x40000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#else
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#endif
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#endif

#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

#ifdef NORFLASH_PS32BIT
#	define CONFIG_ENV_OFFSET		(0x8000)
#	define CONFIG_ENV_SIZE		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x4000
#else
#	define CONFIG_ENV_OFFSET		(0x4000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x2000
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 * CS6 - Available
 * CS7 - Available
 */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_CS0_BASE	0xFFC00000
#	define CONFIG_SYS_CS0_MASK	0x003f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D00
#else
#	define CONFIG_SYS_CS0_BASE	0xFFE00000
#	define CONFIG_SYS_CS0_MASK	0x001f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D80
#endif

#endif				/* _M5329EVB_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
4a442d31 TL	2	/*
	3	* Configuation settings for the Freescale MCF5329 FireEngine board.
	4	*
	5	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	6	* TsiChung Liew ([email protected])
4a442d31 TL	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M5235EVB_H
	14	#define _M5235EVB_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
4a442d31	20
4a442d31	21	#define CONFIG_MCFUART
6d0f6bcf	22	#define CONFIG_SYS_UART_PORT (0)
4a442d31 TL	23
	24	#undef CONFIG_WATCHDOG
	25	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
	26
	27	/*
	28	* BOOTP options
	29	*/
	30	#define CONFIG_BOOTP_BOOTFILESIZE
4a442d31	31
4a442d31 TL	32	#define CONFIG_MCFFEC
4a442d31 TL	33	#ifdef CONFIG_MCFFEC
0f3ba7e9	34	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	35	# define CONFIG_SYS_DISCOVER_PHY
	36	# define CONFIG_SYS_RX_ETH_BUFFER 8
	37	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	38
6d0f6bcf JCPV	39	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	40	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	41	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	42	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	43	# ifndef CONFIG_SYS_DISCOVER_PHY
4a442d31 TL	44	# define FECDUPLEX FULL
	45	# define FECSPEED _100BASET
	46	# else
6d0f6bcf JCPV	47	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	48	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	49	# endif
6d0f6bcf	50	# endif /* CONFIG_SYS_DISCOVER_PHY */
4a442d31 TL	51	#endif
	52
	53	/* Timer */
	54	#define CONFIG_MCFTMR
	55	#undef CONFIG_MCFPIT
	56
	57	/* I2C */
00f792e0 HS	58	#define CONFIG_SYS_I2C
	59	#define CONFIG_SYS_i2C_FSL
	60	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	61	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	62	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf JCPV	63	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	64	#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
	65	#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK \| GPIO_PAR_FECI2C_SDA_MASK)
	66	#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL \| GPIO_PAR_FECI2C_SDA_I2CSDA)
4a442d31 TL	67
4a442d31 TL	68	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
4a442d31 TL	69	#define CONFIG_BOOTFILE "u-boot.bin"
4a442d31 TL	70	#ifdef CONFIG_MCFFEC
4a442d31 TL	71	# define CONFIG_IPADDR 192.162.1.2
	72	# define CONFIG_NETMASK 255.255.255.0
	73	# define CONFIG_SERVERIP 192.162.1.1
	74	# define CONFIG_GATEWAYIP 192.162.1.1
4a442d31 TL	75	#endif /* FEC_ENET */
4a442d31 TL	76
5bc0543d	77	#define CONFIG_HOSTNAME "M5235EVB"
4a442d31 TL	78	#define CONFIG_EXTRA_ENV_SETTINGS \
	79	"netdev=eth0\0" \
	80	"loadaddr=10000\0" \
	81	"u-boot=u-boot.bin\0" \
	82	"load=tftp ${loadaddr) ${u-boot}\0" \
	83	"upd=run load; run prog\0" \
	84	"prog=prot off ffe00000 ffe3ffff;" \
	85	"era ffe00000 ffe3ffff;" \
	86	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	87	"save\0" \
	88	""
	89
	90	#define CONFIG_PRAM 512 /* 512 KB */
4a442d31	91
6d0f6bcf	92	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
4a442d31	93
6d0f6bcf JCPV	94	#define CONFIG_SYS_CLK 75000000
6d0f6bcf JCPV	95	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
4a442d31	96
6d0f6bcf	97	#define CONFIG_SYS_MBAR 0x40000000
4a442d31 TL	98
	99	/*
	100	* Low Level Configuration Settings
	101	* (address mappings, register initial values, etc.)
	102	* You should know what you are doing if you make changes here.
	103	*/
	104	/*-----------------------------------------------------------------------
	105	* Definitions for initial stack pointer and data area (in DPRAM)
	106	*/
6d0f6bcf	107	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	108	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
25ddd1fb	110	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
6d0f6bcf	111	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
4a442d31 TL	112
	113	/*-----------------------------------------------------------------------
	114	* Start addresses for the final memory configuration
	115	* (Set up by the startup code)
6d0f6bcf	116	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
4a442d31	117	*/
6d0f6bcf JCPV	118	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	119	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
4a442d31	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	122	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
4a442d31	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	125	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
4a442d31	126
6d0f6bcf JCPV	127	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	128	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
4a442d31 TL	129
	130	/*
	131	* For booting Linux, the board info and command line data
	132	* have to be in the first 8 MB of memory, since this is
	133	* the maximum mapped by the Linux kernel during initialization ??
	134	*/
	135	/* Initial Memory map for Linux */
6d0f6bcf	136	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	137	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
4a442d31 TL	138
	139	/*-----------------------------------------------------------------------
	140	* FLASH organization
	141	*/
6d0f6bcf	142	#ifdef CONFIG_SYS_FLASH_CFI
6d0f6bcf	143	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
4a442d31	144	#ifdef NORFLASH_PS32BIT
6d0f6bcf	145	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
4a442d31	146	#else
6d0f6bcf	147	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
4a442d31	148	#endif
6d0f6bcf JCPV	149	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	150	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
4a442d31 TL	151	#endif
4a442d31 TL	152
012522fe	153	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
4a442d31 TL	154
	155	/* Configuration for environment
	156	* Environment is embedded in u-boot in the second sector of the flash
	157	*/
5296cb1d	158
	159	#define LDS_BOARD_TEXT \
	160	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d	161	env/embedded.o(.text);
5296cb1d	162
4a442d31	163	#ifdef NORFLASH_PS32BIT
0e8d1586 JCPV	164	# define CONFIG_ENV_OFFSET (0x8000)
	165	# define CONFIG_ENV_SIZE 0x4000
	166	# define CONFIG_ENV_SECT_SIZE 0x4000
4a442d31	167	#else
0e8d1586 JCPV	168	# define CONFIG_ENV_OFFSET (0x4000)
	169	# define CONFIG_ENV_SIZE 0x2000
	170	# define CONFIG_ENV_SECT_SIZE 0x2000
4a442d31 TL	171	#endif
	172
	173	/*-----------------------------------------------------------------------
	174	* Cache Configuration
	175	*/
6d0f6bcf	176	#define CONFIG_SYS_CACHELINE_SIZE 16
4a442d31	177
dd9f054e	178	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	179	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	180	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	181	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	182	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
	183	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	184	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	185	CF_ACR_EN \| CF_ACR_SM_ALL)
	186	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	187	CF_CACR_CEIB \| CF_CACR_DCM \| \
	188	CF_CACR_EUSP)
	189
4a442d31 TL	190	/*-----------------------------------------------------------------------
	191	* Chipselect bank definitions
	192	*/
	193	/*
	194	* CS0 - NOR Flash 1, 2, 4, or 8MB
	195	* CS1 - Available
	196	* CS2 - Available
	197	* CS3 - Available
	198	* CS4 - Available
	199	* CS5 - Available
	200	* CS6 - Available
	201	* CS7 - Available
	202	*/
	203	#ifdef NORFLASH_PS32BIT
012522fe	204	# define CONFIG_SYS_CS0_BASE 0xFFC00000
6d0f6bcf	205	# define CONFIG_SYS_CS0_MASK 0x003f0001
012522fe	206	# define CONFIG_SYS_CS0_CTRL 0x00001D00
4a442d31	207	#else
012522fe	208	# define CONFIG_SYS_CS0_BASE 0xFFE00000
6d0f6bcf	209	# define CONFIG_SYS_CS0_MASK 0x001f0001
012522fe	210	# define CONFIG_SYS_CS0_CTRL 0x00001D80
4a442d31 TL	211	#endif
	212
	213	#endif /* _M5329EVB_H */