[J-u-boot.git] / drivers / net / phy / marvell10g.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Marvell 10G 88x3310 PHY driver
 *
 * Based upon the ID registers, this PHY appears to be a mixture of IPs
 * from two different companies.
 *
 * There appears to be several different data paths through the PHY which
 * are automatically managed by the PHY.  The following has been determined
 * via observation and experimentation for a setup using single-lane Serdes:
 *
 *       SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
 *  10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
 *  10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
 *
 * With XAUI, observation shows:
 *
 *        XAUI PHYXS -- <appropriate PCS as above>
 *
 * and no switching of the host interface mode occurs.
 *
 * If both the fiber and copper ports are connected, the first to gain
 * link takes priority and the other port is completely locked out.
 */
#include <console.h>
#include <dm/device_compat.h>
#include <dm/devres.h>
#include <errno.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/compat.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <marvell_phy.h>
#include <phy.h>

#define MV_PHY_ALASKA_NBT_QUIRK_MASK	0xfffffffe
#define MV_PHY_ALASKA_NBT_QUIRK_REV	(MARVELL_PHY_ID_88X3310 | 0xa)

#define MV_VERSION(a, b, c, d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))

enum {
	MV_PMA_FW_VER0		= 0xc011,
	MV_PMA_FW_VER1		= 0xc012,
	MV_PMA_21X0_PORT_CTRL	= 0xc04a,
	MV_PMA_21X0_PORT_CTRL_SWRST				= BIT(15),
	MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK			= 0x7,
	MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII			= 0x0,
	MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII			= 0x1,
	MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII			= 0x2,
	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER			= 0x4,
	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN	= 0x5,
	MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
	MV_PMA_BOOT		= 0xc050,
	MV_PMA_BOOT_FATAL	= BIT(0),

	MV_PCS_BASE_T		= 0x0000,
	MV_PCS_BASE_R		= 0x1000,
	MV_PCS_1000BASEX	= 0x2000,

	MV_PCS_CSCR1		= 0x8000,
	MV_PCS_CSCR1_ED_MASK	= 0x0300,
	MV_PCS_CSCR1_ED_OFF	= 0x0000,
	MV_PCS_CSCR1_ED_RX	= 0x0200,
	MV_PCS_CSCR1_ED_NLP	= 0x0300,
	MV_PCS_CSCR1_MDIX_MASK	= 0x0060,
	MV_PCS_CSCR1_MDIX_MDI	= 0x0000,
	MV_PCS_CSCR1_MDIX_MDIX	= 0x0020,
	MV_PCS_CSCR1_MDIX_AUTO	= 0x0060,

	MV_PCS_DSC1		= 0x8003,
	MV_PCS_DSC1_ENABLE	= BIT(9),
	MV_PCS_DSC1_10GBT	= 0x01c0,
	MV_PCS_DSC1_1GBR	= 0x0038,
	MV_PCS_DSC1_100BTX	= 0x0007,
	MV_PCS_DSC2		= 0x8004,
	MV_PCS_DSC2_2P5G	= 0xf000,
	MV_PCS_DSC2_5G		= 0x0f00,

	MV_PCS_CSSR1		= 0x8008,
	MV_PCS_CSSR1_SPD1_MASK	= 0xc000,
	MV_PCS_CSSR1_SPD1_SPD2	= 0xc000,
	MV_PCS_CSSR1_SPD1_1000	= 0x8000,
	MV_PCS_CSSR1_SPD1_100	= 0x4000,
	MV_PCS_CSSR1_SPD1_10	= 0x0000,
	MV_PCS_CSSR1_DUPLEX_FULL = BIT(13),
	MV_PCS_CSSR1_RESOLVED	= BIT(11),
	MV_PCS_CSSR1_MDIX	= BIT(6),
	MV_PCS_CSSR1_SPD2_MASK	= 0x000c,
	MV_PCS_CSSR1_SPD2_5000	= 0x0008,
	MV_PCS_CSSR1_SPD2_2500	= 0x0004,
	MV_PCS_CSSR1_SPD2_10000	= 0x0000,

	/* Temperature read register (88E2110 only) */
	MV_PCS_TEMP		= 0x8042,

	/* Number of ports on the device */
	MV_PCS_PORT_INFO	= 0xd00d,
	MV_PCS_PORT_INFO_NPORTS_MASK	= 0x0380,
	MV_PCS_PORT_INFO_NPORTS_SHIFT	= 7,

	/* SerDes reinitialization 88E21X0 */
	MV_AN_21X0_SERDES_CTRL2	= 0x800f,
	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS	= BIT(13),
	MV_AN_21X0_SERDES_CTRL2_RUN_INIT	= BIT(15),

	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
	 * registers appear to set themselves to the 0x800X when AN is
	 * restarted, but status registers appear readable from either.
	 */
	MV_AN_CTRL1000		= 0x8000, /* 1000base-T control register */
	MV_AN_STAT1000		= 0x8001, /* 1000base-T status register */

	/* Vendor2 MMD registers */
	MV_V2_PORT_CTRL		= 0xf001,
	MV_V2_PORT_CTRL_PWRDOWN					= BIT(11),
	MV_V2_33X0_PORT_CTRL_SWRST				= BIT(15),
	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK			= 0x7,
	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI			= 0x0,
	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH		= 0x1,
	MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN		= 0x1,
	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH		= 0x2,
	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI			= 0x3,
	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER			= 0x4,
	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN	= 0x5,
	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH	= 0x6,
	MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII			= 0x7,
	MV_V2_PORT_INTR_STS		= 0xf040,
	MV_V2_PORT_INTR_MASK		= 0xf043,
	MV_V2_PORT_INTR_STS_WOL_EN	= BIT(8),
	MV_V2_MAGIC_PKT_WORD0		= 0xf06b,
	MV_V2_MAGIC_PKT_WORD1		= 0xf06c,
	MV_V2_MAGIC_PKT_WORD2		= 0xf06d,
	/* Wake on LAN registers */
	MV_V2_WOL_CTRL			= 0xf06e,
	MV_V2_WOL_CTRL_CLEAR_STS	= BIT(15),
	MV_V2_WOL_CTRL_MAGIC_PKT_EN	= BIT(0),
	/* Temperature control/read registers (88X3310 only) */
	MV_V2_TEMP_CTRL		= 0xf08a,
	MV_V2_TEMP_CTRL_MASK	= 0xc000,
	MV_V2_TEMP_CTRL_SAMPLE	= 0x0000,
	MV_V2_TEMP_CTRL_DISABLE	= 0xc000,
	MV_V2_TEMP		= 0xf08c,
	MV_V2_TEMP_UNKNOWN	= 0x9600, /* unknown function */
};

struct mv3310_chip {
	bool (*has_downshift)(struct phy_device *phydev);
	int (*test_supported_interfaces)(struct phy_device *phydev);
	int (*get_mactype)(struct phy_device *phydev);
	int (*set_mactype)(struct phy_device *phydev, int mactype);
	int (*select_mactype)(struct phy_device *phydev);
	int (*init_interface)(struct phy_device *phydev, int mactype);
};

struct mv3310_priv {
	DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);

	u32 firmware_ver;
	bool has_downshift;
	bool rate_match;
};

static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
{
	return (const struct mv3310_chip *)phydev->drv->data;
}

static int mv3310_power_down(struct phy_device *phydev)
{
	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
				MV_V2_PORT_CTRL_PWRDOWN);
}

static int mv3310_power_up(struct phy_device *phydev)
{
	struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
	int ret;

	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
				 MV_V2_PORT_CTRL_PWRDOWN);

	if (phydev->drv->uid != MARVELL_PHY_ID_88X3310 ||
	    priv->firmware_ver < 0x00030000)
		return ret;

	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
				MV_V2_33X0_PORT_CTRL_SWRST);
}

static int mv3310_reset(struct phy_device *phydev, u32 unit)
{
	int val, err;

	err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
			     MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
	if (err < 0)
		return err;

	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
					 unit + MDIO_CTRL1, val,
					 !(val & MDIO_CTRL1_RESET),
					 5000, 100000, true);
}

static int mv3310_set_downshift(struct phy_device *phydev)
{
	struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;
	const u8 ds = 1;
	u16 val;
	int err;

	if (!priv->has_downshift)
		return -EOPNOTSUPP;

	val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
	val |= FIELD_PREP(MV_PCS_DSC2_5G, ds);
	err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
			     MV_PCS_DSC2_2P5G | MV_PCS_DSC2_5G, val);
	if (err < 0)
		return err;

	val = MV_PCS_DSC1_ENABLE;
	val |= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
	val |= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
	val |= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);

	return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
			      MV_PCS_DSC1_ENABLE | MV_PCS_DSC1_10GBT |
			      MV_PCS_DSC1_1GBR | MV_PCS_DSC1_100BTX, val);
}

static int mv3310_set_edpd(struct phy_device *phydev)
{
	int err;

	err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
				     MV_PCS_CSCR1_ED_MASK,
				     MV_PCS_CSCR1_ED_NLP);
	if (err > 0)
		err = mv3310_reset(phydev, MV_PCS_BASE_T);

	return err;
}

static int mv3310_probe(struct phy_device *phydev)
{
	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
	struct mv3310_priv *priv;
	u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
	int ret;

	if (!phydev->is_c45 ||
	    (phydev->mmds & mmd_mask) != mmd_mask)
		return -ENODEV;

	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
	if (ret < 0)
		return ret;

	if (ret & MV_PMA_BOOT_FATAL) {
		dev_warn(phydev->dev,
			 "PHY failed to boot firmware, status=%04x\n", ret);
		return -ENODEV;
	}

	priv = devm_kzalloc(phydev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	phydev->priv = priv;

	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
	if (ret < 0)
		return ret;

	priv->firmware_ver = ret << 16;

	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
	if (ret < 0)
		return ret;

	priv->firmware_ver |= ret;

	dev_info(phydev->dev, "Firmware version %u.%u.%u.%u\n",
		 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
		 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);

	if (chip->has_downshift)
		priv->has_downshift = chip->has_downshift(phydev);

	/* Powering down the port when not in use saves about 600mW */
	ret = mv3310_power_down(phydev);
	if (ret)
		return ret;

	return 0;
}

static int mv2110_get_mactype(struct phy_device *phydev)
{
	int mactype;

	mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
	if (mactype < 0)
		return mactype;

	return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
}

static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
{
	int err, val;

	mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
	err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
			     MV_PMA_21X0_PORT_CTRL_SWRST |
			     MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
			     MV_PMA_21X0_PORT_CTRL_SWRST | mactype);
	if (err)
		return err;

	err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
			       MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS |
			       MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
	if (err)
		return err;

	err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
					MV_AN_21X0_SERDES_CTRL2, val,
					!(val &
					  MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
					5000, 100000, true);
	if (err)
		return err;

	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
				  MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
}

static int mv2110_select_mactype(struct phy_device *phydev)
{
	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
		return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
		 !(phydev->interface == PHY_INTERFACE_MODE_10GBASER))
		return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
	else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
		return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
	else
		return -1;
}

static int mv3310_get_mactype(struct phy_device *phydev)
{
	int mactype;

	mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
	if (mactype < 0)
		return mactype;

	return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
}

static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
{
	int ret;

	mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
				     MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
				     mactype);
	if (ret <= 0)
		return ret;

	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
				MV_V2_33X0_PORT_CTRL_SWRST);
}

static int mv3310_select_mactype(struct phy_device *phydev)
{
	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
		 phydev->interface == PHY_INTERFACE_MODE_10GBASER)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
		 phydev->interface == PHY_INTERFACE_MODE_RXAUI)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
		 phydev->interface == PHY_INTERFACE_MODE_XAUI)
		return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
	else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
	else if (phydev->interface == PHY_INTERFACE_MODE_RXAUI)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
	else if (phydev->interface == PHY_INTERFACE_MODE_XAUI)
		return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
		return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
	else
		return -1;
}

static int mv2110_init_interface(struct phy_device *phydev, int mactype)
{
	struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;

	priv->rate_match = false;

	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
		priv->rate_match = true;

	return 0;
}

static int mv3310_init_interface(struct phy_device *phydev, int mactype)
{
	struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;

	priv->rate_match = false;

	if (mactype != MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
		return 0;

	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
	    mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
	    mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
		priv->rate_match = true;

	return 0;
}

static int mv3310_config_init(struct phy_device *phydev)
{
	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
	int err, mactype;

	/* Check that the PHY interface type is compatible */
	err = chip->test_supported_interfaces(phydev);
	if (err)
		return err;

	/* Power up so reset works */
	err = mv3310_power_up(phydev);
	if (err)
		return err;

	/* If host provided host supported interface modes, try to select the
	 * best one
	 */
	mactype = chip->select_mactype(phydev);
	if (mactype >= 0) {
		dev_info(phydev->dev, "Changing MACTYPE to %i\n",
			 mactype);
		err = chip->set_mactype(phydev, mactype);
		if (err)
			return err;
	}

	mactype = chip->get_mactype(phydev);
	if (mactype < 0)
		return mactype;

	err = chip->init_interface(phydev, mactype);
	if (err) {
		dev_err(phydev->dev, "MACTYPE configuration invalid\n");
		return err;
	}

	/* Enable EDPD mode - saving 600mW */
	err = mv3310_set_edpd(phydev);
	if (err)
		return err;

	/* Allow downshift */
	err = mv3310_set_downshift(phydev);
	if (err && err != -EOPNOTSUPP)
		return err;

	return 0;
}

static int mv3310_config(struct phy_device *phydev)
{
	int err;

	err = mv3310_probe(phydev);
	if (!err)
		err = mv3310_config_init(phydev);

	return err;
}

static int mv3310_get_number_of_ports(struct phy_device *phydev)
{
	int ret;

	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
	if (ret < 0)
		return ret;

	ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
	ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;

	return ret + 1;
}

static int mv3310_match_phy_device(struct phy_device *phydev)
{
	if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
		return 0;

	return mv3310_get_number_of_ports(phydev) == 1;
}

static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
{
	int val;

	if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
		return 0;

	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
	if (val < 0)
		return val;

	return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
}

static int mv2110_match_phy_device(struct phy_device *phydev)
{
	return mv211x_match_phy_device(phydev, true);
}

static bool mv3310_has_downshift(struct phy_device *phydev)
{
	struct mv3310_priv *priv = (struct mv3310_priv *)phydev->priv;

	/* Fails to downshift with firmware older than v0.3.5.0 */
	return priv->firmware_ver >= MV_VERSION(0, 3, 5, 0);
}

#define mv_test_bit(iface, phydev)	\
	({ if ((phydev)->interface & (iface)) return 0; })

static int mv3310_mv3340_test_supported_interfaces(struct phy_device *phydev)
{
	mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
	if (mv3310_match_phy_device(phydev))
		mv_test_bit(PHY_INTERFACE_MODE_XAUI, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_RXAUI, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
	return -ENODEV;
}

static int mv2110_mv2111_test_supported_interfaces(struct phy_device *phydev)
{
	mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
	if (mv2110_match_phy_device(phydev))
		mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
	mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
	return -ENODEV;
}

static const struct mv3310_chip mv3310_mv3340_type = {
	.has_downshift = mv3310_has_downshift,
	.test_supported_interfaces = mv3310_mv3340_test_supported_interfaces,
	.get_mactype = mv3310_get_mactype,
	.set_mactype = mv3310_set_mactype,
	.select_mactype = mv3310_select_mactype,
	.init_interface = mv3310_init_interface,
};

static const struct mv3310_chip mv2110_mv2111_type = {
	.test_supported_interfaces = mv2110_mv2111_test_supported_interfaces,
	.get_mactype = mv2110_get_mactype,
	.set_mactype = mv2110_set_mactype,
	.select_mactype = mv2110_select_mactype,
	.init_interface = mv2110_init_interface,
};

U_BOOT_PHY_DRIVER(mv88e3310_mv88e3340) = {
	.name		= "mv88x3310",
	.uid		= MARVELL_PHY_ID_88X3310,
	.mask		= MARVELL_PHY_ID_MASK,
	.features	= PHY_10G_FEATURES,
	.data		= (ulong)&mv3310_mv3340_type,
	.config		= mv3310_config,
};

U_BOOT_PHY_DRIVER(mv88e2110_mv88e2111) = {
	.name		= "mv88e2110",
	.uid		= MARVELL_PHY_ID_88E2110,
	.mask		= MARVELL_PHY_ID_MASK,
	.features	= PHY_10G_FEATURES,
	.data		= (ulong)&mv2110_mv2111_type,
	.config		= mv3310_config,
};
Commit	Line	Data
b6fcab07 MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Marvell 10G 88x3310 PHY driver
	4	*
	5	* Based upon the ID registers, this PHY appears to be a mixture of IPs
	6	* from two different companies.
	7	*
	8	* There appears to be several different data paths through the PHY which
	9	* are automatically managed by the PHY. The following has been determined
	10	* via observation and experimentation for a setup using single-lane Serdes:
	11	*
	12	* SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
	13	* 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
	14	* 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
	15	*
	16	* With XAUI, observation shows:
	17	*
	18	* XAUI PHYXS -- <appropriate PCS as above>
	19	*
	20	* and no switching of the host interface mode occurs.
	21	*
	22	* If both the fiber and copper ports are connected, the first to gain
	23	* link takes priority and the other port is completely locked out.
	24	*/
b6fcab07 MV	25	#include <console.h>
	26	#include <dm/device_compat.h>
	27	#include <dm/devres.h>
	28	#include <errno.h>
	29	#include <linux/bitfield.h>
	30	#include <linux/bitops.h>
	31	#include <linux/compat.h>
	32	#include <linux/delay.h>
	33	#include <linux/iopoll.h>
	34	#include <marvell_phy.h>
	35	#include <phy.h>
	36
	37	#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
	38	#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 \| 0xa)
	39
	40	#define MV_VERSION(a, b, c, d) ((a) << 24 \| (b) << 16 \| (c) << 8 \| (d))
	41
	42	enum {
	43	MV_PMA_FW_VER0 = 0xc011,
	44	MV_PMA_FW_VER1 = 0xc012,
	45	MV_PMA_21X0_PORT_CTRL = 0xc04a,
	46	MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
	47	MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
	48	MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
	49	MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
	50	MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
	51	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
	52	MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
	53	MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
	54	MV_PMA_BOOT = 0xc050,
	55	MV_PMA_BOOT_FATAL = BIT(0),
	56
	57	MV_PCS_BASE_T = 0x0000,
	58	MV_PCS_BASE_R = 0x1000,
	59	MV_PCS_1000BASEX = 0x2000,
	60
	61	MV_PCS_CSCR1 = 0x8000,
	62	MV_PCS_CSCR1_ED_MASK = 0x0300,
	63	MV_PCS_CSCR1_ED_OFF = 0x0000,
	64	MV_PCS_CSCR1_ED_RX = 0x0200,
	65	MV_PCS_CSCR1_ED_NLP = 0x0300,
	66	MV_PCS_CSCR1_MDIX_MASK = 0x0060,
	67	MV_PCS_CSCR1_MDIX_MDI = 0x0000,
	68	MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
	69	MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
	70
	71	MV_PCS_DSC1 = 0x8003,
	72	MV_PCS_DSC1_ENABLE = BIT(9),
	73	MV_PCS_DSC1_10GBT = 0x01c0,
	74	MV_PCS_DSC1_1GBR = 0x0038,
	75	MV_PCS_DSC1_100BTX = 0x0007,
	76	MV_PCS_DSC2 = 0x8004,
	77	MV_PCS_DSC2_2P5G = 0xf000,
	78	MV_PCS_DSC2_5G = 0x0f00,
	79
	80	MV_PCS_CSSR1 = 0x8008,
	81	MV_PCS_CSSR1_SPD1_MASK = 0xc000,
	82	MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
	83	MV_PCS_CSSR1_SPD1_1000 = 0x8000,
	84	MV_PCS_CSSR1_SPD1_100 = 0x4000,
	85	MV_PCS_CSSR1_SPD1_10 = 0x0000,
	86	MV_PCS_CSSR1_DUPLEX_FULL = BIT(13),
	87	MV_PCS_CSSR1_RESOLVED = BIT(11),
	88	MV_PCS_CSSR1_MDIX = BIT(6),
89	MV_PCS_CSSR1_SPD2_MASK = 0x000c,
90	MV_PCS_CSSR1_SPD2_5000 = 0x0008,
91	MV_PCS_CSSR1_SPD2_2500 = 0x0004,
92	MV_PCS_CSSR1_SPD2_10000 = 0x0000,
93
94	/* Temperature read register (88E2110 only) */
95	MV_PCS_TEMP = 0x8042,
96
97	/* Number of ports on the device */
98	MV_PCS_PORT_INFO = 0xd00d,
99	MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
100	MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
101
102	/* SerDes reinitialization 88E21X0 */
103	MV_AN_21X0_SERDES_CTRL2 = 0x800f,
104	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS = BIT(13),
105	MV_AN_21X0_SERDES_CTRL2_RUN_INIT = BIT(15),
106
107	/* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108	* registers appear to set themselves to the 0x800X when AN is
109	* restarted, but status registers appear readable from either.
110	*/
111	MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
112	MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
113
114	/* Vendor2 MMD registers */
115	MV_V2_PORT_CTRL = 0xf001,
116	MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
117	MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
118	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
119	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
120	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
121	MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
122	MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
123	MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
124	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
125	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
126	MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
127	MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
128	MV_V2_PORT_INTR_STS = 0xf040,
129	MV_V2_PORT_INTR_MASK = 0xf043,
130	MV_V2_PORT_INTR_STS_WOL_EN = BIT(8),
131	MV_V2_MAGIC_PKT_WORD0 = 0xf06b,
132	MV_V2_MAGIC_PKT_WORD1 = 0xf06c,
133	MV_V2_MAGIC_PKT_WORD2 = 0xf06d,
134	/* Wake on LAN registers */
135	MV_V2_WOL_CTRL = 0xf06e,
136	MV_V2_WOL_CTRL_CLEAR_STS = BIT(15),
137	MV_V2_WOL_CTRL_MAGIC_PKT_EN = BIT(0),
138	/* Temperature control/read registers (88X3310 only) */
139	MV_V2_TEMP_CTRL = 0xf08a,
140	MV_V2_TEMP_CTRL_MASK = 0xc000,
141	MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
142	MV_V2_TEMP_CTRL_DISABLE = 0xc000,
143	MV_V2_TEMP = 0xf08c,
144	MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
145	};
146
147	struct mv3310_chip {
148	bool (has_downshift)(struct phy_device phydev);
149	int (test_supported_interfaces)(struct phy_device phydev);
150	int (get_mactype)(struct phy_device phydev);
151	int (set_mactype)(struct phy_device phydev, int mactype);
152	int (select_mactype)(struct phy_device phydev);
153	int (init_interface)(struct phy_device phydev, int mactype);
154	};
155
156	struct mv3310_priv {
157	DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
158
159	u32 firmware_ver;
160	bool has_downshift;
161	bool rate_match;
162	};
163
164	static const struct mv3310_chip to_mv3310_chip(struct phy_device phydev)
165	{
166	return (const struct mv3310_chip *)phydev->drv->data;
167	}
168
169	static int mv3310_power_down(struct phy_device *phydev)
170	{
171	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
172	MV_V2_PORT_CTRL_PWRDOWN);
173	}
174
175	static int mv3310_power_up(struct phy_device *phydev)
176	{
177	struct mv3310_priv priv = (struct mv3310_priv )phydev->priv;
178	int ret;
179
180	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
181	MV_V2_PORT_CTRL_PWRDOWN);
182
183	if (phydev->drv->uid != MARVELL_PHY_ID_88X3310 \|\|
184	priv->firmware_ver < 0x00030000)
185	return ret;
186
187	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
188	MV_V2_33X0_PORT_CTRL_SWRST);
189	}
190
191	static int mv3310_reset(struct phy_device *phydev, u32 unit)
192	{
193	int val, err;
194
195	err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
196	MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
197	if (err < 0)
198	return err;
199
200	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
201	unit + MDIO_CTRL1, val,
202	!(val & MDIO_CTRL1_RESET),
203	5000, 100000, true);
204	}
205
206	static int mv3310_set_downshift(struct phy_device *phydev)
207	{
208	struct mv3310_priv priv = (struct mv3310_priv )phydev->priv;
209	const u8 ds = 1;
210	u16 val;
211	int err;
212
213	if (!priv->has_downshift)
214	return -EOPNOTSUPP;
215
216	val = FIELD_PREP(MV_PCS_DSC2_2P5G, ds);
217	val \|= FIELD_PREP(MV_PCS_DSC2_5G, ds);
218	err = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC2,
219	MV_PCS_DSC2_2P5G \| MV_PCS_DSC2_5G, val);
220	if (err < 0)
221	return err;
222
223	val = MV_PCS_DSC1_ENABLE;
224	val \|= FIELD_PREP(MV_PCS_DSC1_10GBT, ds);
225	val \|= FIELD_PREP(MV_PCS_DSC1_1GBR, ds);
226	val \|= FIELD_PREP(MV_PCS_DSC1_100BTX, ds);
227
228	return phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1,
229	MV_PCS_DSC1_ENABLE \| MV_PCS_DSC1_10GBT \|
230	MV_PCS_DSC1_1GBR \| MV_PCS_DSC1_100BTX, val);
231	}
232
233	static int mv3310_set_edpd(struct phy_device *phydev)
234	{
235	int err;
236
237	err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
238	MV_PCS_CSCR1_ED_MASK,
239	MV_PCS_CSCR1_ED_NLP);
240	if (err > 0)
241	err = mv3310_reset(phydev, MV_PCS_BASE_T);
242
243	return err;
244	}
245
246	static int mv3310_probe(struct phy_device *phydev)
247	{
248	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
249	struct mv3310_priv *priv;
250	u32 mmd_mask = MDIO_DEVS_PMAPMD \| MDIO_DEVS_AN;
251	int ret;
252
253	if (!phydev->is_c45 \|\|
254	(phydev->mmds & mmd_mask) != mmd_mask)
255	return -ENODEV;
256
257	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
258	if (ret < 0)
259	return ret;
260
261	if (ret & MV_PMA_BOOT_FATAL) {
262	dev_warn(phydev->dev,
263	"PHY failed to boot firmware, status=%04x\n", ret);
264	return -ENODEV;
265	}
266
267	priv = devm_kzalloc(phydev->dev, sizeof(*priv), GFP_KERNEL);
268	if (!priv)
269	return -ENOMEM;
270
271	phydev->priv = priv;
272
273	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
274	if (ret < 0)
275	return ret;
276
277	priv->firmware_ver = ret << 16;
278
279	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
280	if (ret < 0)
281	return ret;
282
283	priv->firmware_ver \|= ret;
284
285	dev_info(phydev->dev, "Firmware version %u.%u.%u.%u\n",
286	priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
287	(priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
288
289	if (chip->has_downshift)
290	priv->has_downshift = chip->has_downshift(phydev);
291
292	/* Powering down the port when not in use saves about 600mW */
293	ret = mv3310_power_down(phydev);
294	if (ret)
295	return ret;
296
297	return 0;
298	}
299
300	static int mv2110_get_mactype(struct phy_device *phydev)
301	{
302	int mactype;
303
304	mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
305	if (mactype < 0)
306	return mactype;
307
308	return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
309	}
310
311	static int mv2110_set_mactype(struct phy_device *phydev, int mactype)
312	{
313	int err, val;
314
315	mactype &= MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
316	err = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL,
317	MV_PMA_21X0_PORT_CTRL_SWRST \|
318	MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK,
319	MV_PMA_21X0_PORT_CTRL_SWRST \| mactype);
320	if (err)
321	return err;
322
323	err = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
324	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS \|
325	MV_AN_21X0_SERDES_CTRL2_RUN_INIT);
326	if (err)
327	return err;
328
329	err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_AN,
330	MV_AN_21X0_SERDES_CTRL2, val,
331	!(val &
332	MV_AN_21X0_SERDES_CTRL2_RUN_INIT),
333	5000, 100000, true);
334	if (err)
335	return err;
336
337	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2,
338	MV_AN_21X0_SERDES_CTRL2_AUTO_INIT_DIS);
339	}
340
341	static int mv2110_select_mactype(struct phy_device *phydev)
342	{
343	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
344	return MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII;
345	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
346	!(phydev->interface == PHY_INTERFACE_MODE_10GBASER))
347	return MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER;
348	else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
349	return MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
350	else
351	return -1;
352	}
353
354	static int mv3310_get_mactype(struct phy_device *phydev)
355	{
356	int mactype;
357
358	mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
359	if (mactype < 0)
360	return mactype;
361
362	return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
363	}
364
365	static int mv3310_set_mactype(struct phy_device *phydev, int mactype)
366	{
367	int ret;
368
369	mactype &= MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
370	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
371	MV_V2_33X0_PORT_CTRL_MACTYPE_MASK,
372	mactype);
373	if (ret <= 0)
374	return ret;
375
376	return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
377	MV_V2_33X0_PORT_CTRL_SWRST);
378	}
379
380	static int mv3310_select_mactype(struct phy_device *phydev)
381	{
382	if (phydev->interface == PHY_INTERFACE_MODE_USXGMII)
383	return MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII;
384	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
385	phydev->interface == PHY_INTERFACE_MODE_10GBASER)
386	return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
387	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
388	phydev->interface == PHY_INTERFACE_MODE_RXAUI)
389	return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI;
390	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII &&
391	phydev->interface == PHY_INTERFACE_MODE_XAUI)
392	return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI;
393	else if (phydev->interface == PHY_INTERFACE_MODE_10GBASER)
394	return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH;
395	else if (phydev->interface == PHY_INTERFACE_MODE_RXAUI)
396	return MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH;
397	else if (phydev->interface == PHY_INTERFACE_MODE_XAUI)
398	return MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH;
399	else if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
400	return MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER;
401	else
402	return -1;
403	}
404
405	static int mv2110_init_interface(struct phy_device *phydev, int mactype)
406	{
407	struct mv3310_priv priv = (struct mv3310_priv )phydev->priv;
408
409	priv->rate_match = false;
410
411	if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
412	priv->rate_match = true;
413
414	return 0;
415	}
416
417	static int mv3310_init_interface(struct phy_device *phydev, int mactype)
418	{
419	struct mv3310_priv priv = (struct mv3310_priv )phydev->priv;
420
421	priv->rate_match = false;
422
423	if (mactype != MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
424	return 0;
425
426	if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH \|\|
427	mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH \|\|
428	mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
429	priv->rate_match = true;
430
431	return 0;
432	}
433
434	static int mv3310_config_init(struct phy_device *phydev)
435	{
436	const struct mv3310_chip *chip = to_mv3310_chip(phydev);
437	int err, mactype;
438
439	/* Check that the PHY interface type is compatible */
440	err = chip->test_supported_interfaces(phydev);
441	if (err)
442	return err;
443
444	/* Power up so reset works */
445	err = mv3310_power_up(phydev);
446	if (err)
447	return err;
448
449	/* If host provided host supported interface modes, try to select the
450	* best one
451	*/
452	mactype = chip->select_mactype(phydev);
453	if (mactype >= 0) {
454	dev_info(phydev->dev, "Changing MACTYPE to %i\n",
455	mactype);
456	err = chip->set_mactype(phydev, mactype);
457	if (err)
458	return err;
459	}
460
461	mactype = chip->get_mactype(phydev);
462	if (mactype < 0)
463	return mactype;
464
465	err = chip->init_interface(phydev, mactype);
466	if (err) {
467	dev_err(phydev->dev, "MACTYPE configuration invalid\n");
468	return err;
469	}
470
471	/* Enable EDPD mode - saving 600mW */
472	err = mv3310_set_edpd(phydev);
473	if (err)
474	return err;
475
476	/* Allow downshift */
477	err = mv3310_set_downshift(phydev);
478	if (err && err != -EOPNOTSUPP)
479	return err;
480
481	return 0;
482	}
483
484	static int mv3310_config(struct phy_device *phydev)
485	{
486	int err;
487
488	err = mv3310_probe(phydev);
489	if (!err)
490	err = mv3310_config_init(phydev);
491
492	return err;
493	}
494
495	static int mv3310_get_number_of_ports(struct phy_device *phydev)
496	{
497	int ret;
498
499	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
500	if (ret < 0)
501	return ret;
502
503	ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
504	ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
505
506	return ret + 1;
507	}
508
509	static int mv3310_match_phy_device(struct phy_device *phydev)
510	{
511	if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
512	return 0;
513
514	return mv3310_get_number_of_ports(phydev) == 1;
515	}
516
517	static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
518	{
519	int val;
520
521	if ((phydev->phy_id & MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
522	return 0;
523
524	val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
525	if (val < 0)
526	return val;
527
528	return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
529	}
530
531	static int mv2110_match_phy_device(struct phy_device *phydev)
532	{
533	return mv211x_match_phy_device(phydev, true);
534	}
535
536	static bool mv3310_has_downshift(struct phy_device *phydev)
537	{
538	struct mv3310_priv priv = (struct mv3310_priv )phydev->priv;
539
540	/* Fails to downshift with firmware older than v0.3.5.0 */
541	return priv->firmware_ver >= MV_VERSION(0, 3, 5, 0);
542	}
543
544	#define mv_test_bit(iface, phydev) \
545	({ if ((phydev)->interface & (iface)) return 0; })
546
547	static int mv3310_mv3340_test_supported_interfaces(struct phy_device *phydev)
548	{
549	mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
550	mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
551	mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
552	if (mv3310_match_phy_device(phydev))
553	mv_test_bit(PHY_INTERFACE_MODE_XAUI, phydev);
554	mv_test_bit(PHY_INTERFACE_MODE_RXAUI, phydev);
555	mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
556	mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
557	return -ENODEV;
558	}
559
560	static int mv2110_mv2111_test_supported_interfaces(struct phy_device *phydev)
561	{
562	mv_test_bit(PHY_INTERFACE_MODE_SGMII, phydev);
563	mv_test_bit(PHY_INTERFACE_MODE_2500BASEX, phydev);
564	if (mv2110_match_phy_device(phydev))
565	mv_test_bit(PHY_INTERFACE_MODE_5GBASER, phydev);
566	mv_test_bit(PHY_INTERFACE_MODE_10GBASER, phydev);
567	mv_test_bit(PHY_INTERFACE_MODE_USXGMII, phydev);
568	return -ENODEV;
569	}
570
571	static const struct mv3310_chip mv3310_mv3340_type = {
572	.has_downshift = mv3310_has_downshift,
573	.test_supported_interfaces = mv3310_mv3340_test_supported_interfaces,
574	.get_mactype = mv3310_get_mactype,
575	.set_mactype = mv3310_set_mactype,
576	.select_mactype = mv3310_select_mactype,
577	.init_interface = mv3310_init_interface,
578	};
579
580	static const struct mv3310_chip mv2110_mv2111_type = {
581	.test_supported_interfaces = mv2110_mv2111_test_supported_interfaces,
582	.get_mactype = mv2110_get_mactype,
583	.set_mactype = mv2110_set_mactype,
584	.select_mactype = mv2110_select_mactype,
585	.init_interface = mv2110_init_interface,
586	};
587
588	U_BOOT_PHY_DRIVER(mv88e3310_mv88e3340) = {
589	.name = "mv88x3310",
590	.uid = MARVELL_PHY_ID_88X3310,
591	.mask = MARVELL_PHY_ID_MASK,
592	.features = PHY_10G_FEATURES,
593	.data = (ulong)&mv3310_mv3340_type,
594	.config = mv3310_config,
595	};
596
597	U_BOOT_PHY_DRIVER(mv88e2110_mv88e2111) = {
598	.name = "mv88e2110",
599	.uid = MARVELL_PHY_ID_88E2110,
600	.mask = MARVELL_PHY_ID_MASK,
601	.features = PHY_10G_FEATURES,
602	.data = (ulong)&mv2110_mv2111_type,
603	.config = mv3310_config,
604	};