[J-u-boot.git] / drivers / net / fm / tgec_phy.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 * Some part is taken from tsec.c
 */
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <fsl_tgec.h>
#include <fm_eth.h>

/*
 * Write value to the PHY for this device to the register at regnum, waiting
 * until the write is done before it returns.  All PHY configuration has to be
 * done through the TSEC1 MIIM regs
 */
static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
			   int regnum, u16 value)
{
	u32 mdio_ctl;
	u32 stat_val;
	struct tgec_mdio_controller *regs = bus->priv;

	if (dev_addr == MDIO_DEVAD_NONE)
		return 0;

	/* Wait till the bus is free */
	stat_val = MDIO_STAT_CLKDIV(100);
	out_be32(&regs->mdio_stat, stat_val);
	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
		;

	/* Set the port and dev addr */
	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
	out_be32(&regs->mdio_ctl, mdio_ctl);

	/* Set the register address */
	out_be32(&regs->mdio_addr, regnum & 0xffff);

	/* Wait till the bus is free */
	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
		;

	/* Write the value to the register */
	out_be32(&regs->mdio_data, MDIO_DATA(value));

	/* Wait till the MDIO write is complete */
	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
		;

	return 0;
}

/*
 * Reads from register regnum in the PHY for device dev, returning the value.
 * Clears miimcom first.  All PHY configuration has to be done through the
 * TSEC1 MIIM regs
 */
static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
			  int regnum)
{
	u32 mdio_ctl;
	u32 stat_val;
	struct tgec_mdio_controller *regs = bus->priv;

	if (dev_addr == MDIO_DEVAD_NONE)
		return 0xffff;

	stat_val = MDIO_STAT_CLKDIV(100);
	out_be32(&regs->mdio_stat, stat_val);
	/* Wait till the bus is free */
	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
		;

	/* Set the Port and Device Addrs */
	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
	out_be32(&regs->mdio_ctl, mdio_ctl);

	/* Set the register address */
	out_be32(&regs->mdio_addr, regnum & 0xffff);

	/* Wait till the bus is free */
	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
		;

	/* Initiate the read */
	mdio_ctl |= MDIO_CTL_READ;
	out_be32(&regs->mdio_ctl, mdio_ctl);

	/* Wait till the MDIO write is complete */
	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
		;

	/* Return all Fs if nothing was there */
	if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
		return 0xffff;

	return in_be32(&regs->mdio_data) & 0xffff;
}

static int tgec_mdio_reset(struct mii_dev *bus)
{
	return 0;
}

int fm_tgec_mdio_init(struct bd_info *bis, struct tgec_mdio_info *info)
{
	struct mii_dev *bus = mdio_alloc();

	if (!bus) {
		printf("Failed to allocate FM TGEC MDIO bus\n");
		return -1;
	}

	bus->read = tgec_mdio_read;
	bus->write = tgec_mdio_write;
	bus->reset = tgec_mdio_reset;
	strcpy(bus->name, info->name);

	bus->priv = info->regs;

	return mdio_register(bus);
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c916d7c9 KG	2	/*
c916d7c9 KG	3	* Copyright 2009-2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
c916d7c9 KG	5	* Some part is taken from tsec.c
c916d7c9 KG	6	*/
c916d7c9 KG	7	#include <miiphy.h>
	8	#include <phy.h>
	9	#include <asm/io.h>
8225b2fd	10	#include <fsl_tgec.h>
c916d7c9 KG	11	#include <fm_eth.h>
	12
	13	/*
	14	* Write value to the PHY for this device to the register at regnum, waiting
	15	* until the write is done before it returns. All PHY configuration has to be
	16	* done through the TSEC1 MIIM regs
	17	*/
960d70c6 KP	18	static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
960d70c6 KP	19	int regnum, u16 value)
c916d7c9 KG	20	{
	21	u32 mdio_ctl;
	22	u32 stat_val;
	23	struct tgec_mdio_controller *regs = bus->priv;
	24
	25	if (dev_addr == MDIO_DEVAD_NONE)
	26	return 0;
	27
	28	/* Wait till the bus is free */
	29	stat_val = MDIO_STAT_CLKDIV(100);
	30	out_be32(&regs->mdio_stat, stat_val);
	31	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
	32	;
	33
	34	/* Set the port and dev addr */
	35	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) \| MDIO_CTL_DEV_ADDR(dev_addr);
	36	out_be32(&regs->mdio_ctl, mdio_ctl);
	37
	38	/* Set the register address */
	39	out_be32(&regs->mdio_addr, regnum & 0xffff);
	40
	41	/* Wait till the bus is free */
	42	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
	43	;
	44
	45	/* Write the value to the register */
	46	out_be32(&regs->mdio_data, MDIO_DATA(value));
	47
	48	/* Wait till the MDIO write is complete */
	49	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
	50	;
	51
	52	return 0;
	53	}
	54
	55	/*
	56	* Reads from register regnum in the PHY for device dev, returning the value.
	57	* Clears miimcom first. All PHY configuration has to be done through the
	58	* TSEC1 MIIM regs
	59	*/
960d70c6 KP	60	static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
960d70c6 KP	61	int regnum)
c916d7c9 KG	62	{
	63	u32 mdio_ctl;
	64	u32 stat_val;
	65	struct tgec_mdio_controller *regs = bus->priv;
	66
	67	if (dev_addr == MDIO_DEVAD_NONE)
	68	return 0xffff;
	69
	70	stat_val = MDIO_STAT_CLKDIV(100);
	71	out_be32(&regs->mdio_stat, stat_val);
	72	/* Wait till the bus is free */
	73	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
	74	;
	75
	76	/* Set the Port and Device Addrs */
	77	mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) \| MDIO_CTL_DEV_ADDR(dev_addr);
	78	out_be32(&regs->mdio_ctl, mdio_ctl);
	79
	80	/* Set the register address */
	81	out_be32(&regs->mdio_addr, regnum & 0xffff);
	82
	83	/* Wait till the bus is free */
	84	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
	85	;
	86
	87	/* Initiate the read */
	88	mdio_ctl \|= MDIO_CTL_READ;
	89	out_be32(&regs->mdio_ctl, mdio_ctl);
	90
	91	/* Wait till the MDIO write is complete */
	92	while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY)
	93	;
	94
	95	/* Return all Fs if nothing was there */
	96	if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
	97	return 0xffff;
	98
	99	return in_be32(&regs->mdio_data) & 0xffff;
	100	}
	101
960d70c6	102	static int tgec_mdio_reset(struct mii_dev *bus)
c916d7c9 KG	103	{
	104	return 0;
	105	}
	106
b75d8dc5	107	int fm_tgec_mdio_init(struct bd_info bis, struct tgec_mdio_info info)
c916d7c9 KG	108	{
	109	struct mii_dev *bus = mdio_alloc();
	110
	111	if (!bus) {
	112	printf("Failed to allocate FM TGEC MDIO bus\n");
	113	return -1;
	114	}
	115
	116	bus->read = tgec_mdio_read;
	117	bus->write = tgec_mdio_write;
	118	bus->reset = tgec_mdio_reset;
192bc694	119	strcpy(bus->name, info->name);
c916d7c9 KG	120
	121	bus->priv = info->regs;
	122
	123	return mdio_register(bus);
	124	}