[J-u-boot.git] / include / configs / MPC8548CDS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
 * Copyright 2020 NXP
 */

/*
 * mpc8548cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1			/* SRIO port 1 */

#define CONFIG_PCI1		/* PCI controller 1 */
#define CONFIG_PCIE1		/* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2

#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

#ifndef __ASSEMBLY__
#include <linux/stringify.h>
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/

#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

/*
 * Physical Address Map
 *
 * 32bit:
 * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
 * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
 * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
 * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
 * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
 * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 * 36bit:
 * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
 * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
 * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
 * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
 * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
 * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
 * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
 * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
 * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
 * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
 * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
 */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_SYS_FLASH_BANKS_LIST \
	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_HWCONFIG			/* enable hwconfig */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
#else
#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows	OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *		    or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL	  = BR[24:26] = 000
 *    Valid		  = BR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT		  OR[20]    = 1
 *    ACS		  OR[21:22] = 11
 *    XACS		  OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA		  OR[28]    = 0
 *    TRLX		  OR[29]    = 1
 *    EHTR		  OR[30]    = 1
 *    EAD extra time	  OR[31]    = 1
 *
 * 0	4    8	  12   16   20	 24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#ifdef CONFIG_PHYS_64BIT
#define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
#else
#define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#if !CONFIG_IS_ENABLED(DM_I2C)
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
#else
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif

/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_CCID

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
#else
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#endif
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
#endif
#endif

/*
 * RapidIO MMU
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME	"eTSEC3"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC3_PHY_ADDR		2
#define TSEC4_PHY_ADDR		3

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC4_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */

#define CONFIG_IPADDR	 192.168.1.253

#define CONFIG_HOSTNAME	 "unknown"
#define CONFIG_ROOTPATH	 "/nfsroot"
#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	 255.255.255.0

#define	CONFIG_EXTRA_ENV_SETTINGS		\
	"hwconfig=fsl_ddr:ecc=off\0"		\
	"netdev=eth0\0"				\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot; "	\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"consoledev=ttyS1\0"			\
	"ramdiskaddr=2000000\0"			\
	"ramdiskfile=ramdisk.uboot\0"		\
	"fdtaddr=1e00000\0"			\
	"fdtfile=mpc8548cds.dtb\0"

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
d9b94f28	2	/*
8b47d7ec	3	* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
01d97d5f	4	* Copyright 2020 NXP
d9b94f28 JL	5	*/
	6
	7	/*
	8	* mpc8548cds board configuration file
	9	*
	10	* Please refer to doc/README.mpc85xxcds for more info.
	11	*
	12	*/
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
8b47d7ec KG	16	#define CONFIG_SYS_SRIO
	17	#define CONFIG_SRIO1 /* SRIO port 1 */
	18
f2cff6b1	19	#define CONFIG_PCI1 /* PCI controller 1 */
b38eaec5	20	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
f2cff6b1	21	#undef CONFIG_PCI2
f2cff6b1	22
f2cff6b1	23	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
d9b94f28	24
d9b94f28	25	#ifndef __ASSEMBLY__
1af3c7f4	26	#include <linux/stringify.h>
d9b94f28	27	#endif
d9b94f28 JL	28
	29	/*
	30	* These can be toggled for performance analysis, otherwise use default.
	31	*/
f2cff6b1	32	#define CONFIG_L2_CACHE /* toggle L2 cache */
d9b94f28 JL	33
	34	/*
	35	* Only possible on E500 Version 2 or newer cores.
	36	*/
	37	#define CONFIG_ENABLE_36BIT_PHYS 1
	38
e46fedfe TT	39	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	40	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
d9b94f28	41
e31d2c1e	42	/* DDR Setup */
e31d2c1e	43	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
e31d2c1e	44
e31d2c1e JL	45	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
e31d2c1e JL	46
6d0f6bcf JCPV	47	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	48	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
d9b94f28	49
e31d2c1e	50	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
d9b94f28	51
e31d2c1e JL	52	/* I2C addresses of SPD EEPROMs */
	53	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	54
	55	/* Make sure required options are set */
d9b94f28 JL	56	#ifndef CONFIG_SPD_EEPROM
	57	#error ("CONFIG_SPD_EEPROM is required")
	58	#endif
	59
fff80975	60	/*
	61	* Physical Address Map
	62	*
	63	* 32bit:
	64	* 0x0000_0000 0x7fff_ffff DDR 2G cacheable
	65	* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
	66	* 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
	67	* 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
	68	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	69	* 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
	70	* 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
	71	* 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
	72	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
	73	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	74	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	75	*
b76aef60	76	* 36bit:
	77	* 0x00000_0000 0x07fff_ffff DDR 2G cacheable
	78	* 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
	79	* 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
	80	* 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
	81	* 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
	82	* 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
	83	* 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
	84	* 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
	85	* 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
	86	* 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
	87	* 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
	88	*
fff80975	89	*/
fff80975	90
d9b94f28 JL	91	/*
	92	* Local Bus Definitions
	93	*/
	94
	95	/*
	96	* FLASH on the Local Bus
	97	* Two banks, 8M each, using the CFI driver.
	98	* Boot from BR0/OR0 bank at 0xff00_0000
	99	* Alternate BR1/OR1 bank at 0xff80_0000
	100	*
	101	* BR0, BR1:
	102	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	103	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	104	* Port Size = 16 bits = BRx[19:20] = 10
	105	* Use GPCM = BRx[24:26] = 000
	106	* Valid = BRx[31] = 1
	107	*
f2cff6b1 ES	108	* 0 4 8 12 16 20 24 28
	109	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	110	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
d9b94f28 JL	111	*
	112	* OR0, OR1:
	113	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	114	* Reserved ORx[17:18] = 11, confusion here?
	115	* CSNT = ORx[20] = 1
	116	* ACS = half cycle delay = ORx[21:22] = 11
	117	* SCY = 6 = ORx[24:27] = 0110
	118	* TRLX = use relaxed timing = ORx[29] = 1
	119	* EAD = use external address latch delay = OR[31] = 1
	120	*
f2cff6b1 ES	121	* 0 4 8 12 16 20 24 28
f2cff6b1 ES	122	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
d9b94f28 JL	123	*/
d9b94f28 JL	124
fff80975	125	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
b76aef60	126	#ifdef CONFIG_PHYS_64BIT
	127	#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
	128	#else
fff80975	129	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
b76aef60	130	#endif
d9b94f28	131
fff80975	132	#define CONFIG_SYS_FLASH_BANKS_LIST \
fff80975	133	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
6d0f6bcf JCPV	134	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	135	#undef CONFIG_SYS_FLASH_CHECKSUM
	136	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	137	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
d9b94f28	138
14d0a02a	139	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
d9b94f28	140
6d0f6bcf	141	#define CONFIG_SYS_FLASH_EMPTY_INFO
d9b94f28	142
867b06f4	143	#define CONFIG_HWCONFIG /* enable hwconfig */
d9b94f28 JL	144
	145	/*
	146	* SDRAM on the Local Bus
	147	*/
fff80975	148	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
b76aef60	149	#ifdef CONFIG_PHYS_64BIT
	150	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
	151	#else
fff80975	152	#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
b76aef60	153	#endif
6d0f6bcf	154	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
d9b94f28 JL	155
	156	/*
	157	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	158	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
d9b94f28 JL	159	*
	160	* For BR2, need:
	161	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	162	* port-size = 32-bits = BR2[19:20] = 11
	163	* no parity checking = BR2[21:22] = 00
	164	* SDRAM for MSEL = BR2[24:26] = 011
	165	* Valid = BR[31] = 1
	166	*
f2cff6b1	167	* 0 4 8 12 16 20 24 28
d9b94f28 JL	168	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
d9b94f28 JL	169	*
6d0f6bcf	170	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
d9b94f28 JL	171	* FIXME: the top 17 bits of BR2.
	172	*/
	173
d9b94f28	174	/*
6d0f6bcf	175	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
d9b94f28 JL	176	*
	177	* For OR2, need:
	178	* 64MB mask for AM, OR2[0:7] = 1111 1100
	179	* XAM, OR2[17:18] = 11
	180	* 9 columns OR2[19-21] = 010
f2cff6b1	181	* 13 rows OR2[23-25] = 100
d9b94f28 JL	182	* EAD set for extra time OR[31] = 1
d9b94f28 JL	183	*
f2cff6b1	184	* 0 4 8 12 16 20 24 28
d9b94f28 JL	185	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	186	*/
	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	189	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	190	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	191	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
d9b94f28	192
d9b94f28 JL	193	/*
	194	* Common settings for all Local Bus SDRAM commands.
	195	* At run time, either BSMA1516 (for CPU 1.1)
f2cff6b1	196	* or BSMA1617 (for CPU 1.0) (old)
d9b94f28 JL	197	* is OR'ed in too.
d9b94f28 JL	198	*/
b0fe93ed KG	199	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	200	\| LSDMR_PRETOACT7 \
	201	\| LSDMR_ACTTORW7 \
	202	\| LSDMR_BL8 \
	203	\| LSDMR_WRC4 \
	204	\| LSDMR_CL3 \
	205	\| LSDMR_RFEN \
d9b94f28 JL	206	)
	207
	208	/*
	209	* The CADMUS registers are connected to CS3 on CDS.
	210	* The new memory map places CADMUS at 0xf8000000.
	211	*
	212	* For BR3, need:
	213	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	214	* port-size = 8-bits = BR[19:20] = 01
	215	* no parity checking = BR[21:22] = 00
f2cff6b1 ES	216	* GPMC for MSEL = BR[24:26] = 000
f2cff6b1 ES	217	* Valid = BR[31] = 1
d9b94f28	218	*
f2cff6b1	219	* 0 4 8 12 16 20 24 28
d9b94f28 JL	220	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	221	*
	222	* For OR3, need:
f2cff6b1	223	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
d9b94f28	224	* disable buffer ctrl OR[19] = 0
f2cff6b1 ES	225	* CSNT OR[20] = 1
	226	* ACS OR[21:22] = 11
	227	* XACS OR[23] = 1
d9b94f28	228	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
f2cff6b1 ES	229	* SETA OR[28] = 0
	230	* TRLX OR[29] = 1
	231	* EHTR OR[30] = 1
	232	* EAD extra time OR[31] = 1
d9b94f28	233	*
f2cff6b1	234	* 0 4 8 12 16 20 24 28
d9b94f28 JL	235	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	236	*/
	237
25eedb2c JL	238	#define CONFIG_FSL_CADMUS
25eedb2c JL	239
d9b94f28	240	#define CADMUS_BASE_ADDR 0xf8000000
b76aef60	241	#ifdef CONFIG_PHYS_64BIT
	242	#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
	243	#else
fff80975	244	#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
b76aef60	245	#endif
d9b94f28	246
6d0f6bcf JCPV	247	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	248	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	249	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
f2cff6b1	250
25ddd1fb	251	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	252	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d9b94f28	253
7bb72855	254	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
d9b94f28 JL	255
d9b94f28 JL	256	/* Serial Port */
6d0f6bcf JCPV	257	#define CONFIG_SYS_NS16550_SERIAL
	258	#define CONFIG_SYS_NS16550_REG_SIZE 1
	259	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
d9b94f28	260
6d0f6bcf	261	#define CONFIG_SYS_BAUDRATE_TABLE \
d9b94f28 JL	262	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
d9b94f28 JL	263
6d0f6bcf JCPV	264	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	265	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
d9b94f28	266
20476726 JL	267	/*
	268	* I2C
	269	*/
2147a169	270	#if !CONFIG_IS_ENABLED(DM_I2C)
00f792e0	271	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
01d97d5f BL	272	#else
01d97d5f BL	273	#define CONFIG_SYS_SPD_BUS_NUM 0
01d97d5f	274	#endif
d9b94f28	275
e8d18541	276	/* EEPROM */
6d0f6bcf	277	#define CONFIG_SYS_I2C_EEPROM_CCID
e8d18541	278
d9b94f28 JL	279	/*
d9b94f28 JL	280	* General PCI
362dd830	281	* Memory space is mapped 1-1, but I/O space must start from 0.
d9b94f28	282	*/
5af0fdd8	283	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
b76aef60	284	#ifdef CONFIG_PHYS_64BIT
	285	#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
	286	#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
	287	#else
10795f42	288	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	289	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
b76aef60	290	#endif
6d0f6bcf	291	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	292	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	293	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
b76aef60	294	#ifdef CONFIG_PHYS_64BIT
	295	#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
	296	#else
6d0f6bcf	297	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
b76aef60	298	#endif
6d0f6bcf	299	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
d9b94f28	300
f2cff6b1	301	#ifdef CONFIG_PCIE1
5af0fdd8	302	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
b76aef60	303	#ifdef CONFIG_PHYS_64BIT
b76aef60	304	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
b76aef60	305	#else
5af0fdd8	306	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
b76aef60	307	#endif
aca5f018	308	#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
b76aef60	309	#ifdef CONFIG_PHYS_64BIT
	310	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
	311	#else
6d0f6bcf	312	#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
b76aef60	313	#endif
f2cff6b1	314	#endif
d9b94f28	315
41fb7e0f ZR	316	/*
	317	* RapidIO MMU
	318	*/
fff80975	319	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
b76aef60	320	#ifdef CONFIG_PHYS_64BIT
	321	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
	322	#else
fff80975	323	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
b76aef60	324	#endif
8b47d7ec	325	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
d9b94f28	326
7f3f2bd2 RV	327	#ifdef CONFIG_LEGACY
	328	#define BRIDGE_ID 17
	329	#define VIA_ID 2
	330	#else
	331	#define BRIDGE_ID 28
	332	#define VIA_ID 4
	333	#endif
	334
d9b94f28	335	#if defined(CONFIG_PCI)
867b06f4	336	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
d9b94f28 JL	337	#endif /* CONFIG_PCI */
d9b94f28 JL	338
d9b94f28 JL	339	#if defined(CONFIG_TSEC_ENET)
d9b94f28 JL	340
255a3577 KP	341	#define CONFIG_TSEC1 1
	342	#define CONFIG_TSEC1_NAME "eTSEC0"
	343	#define CONFIG_TSEC2 1
	344	#define CONFIG_TSEC2_NAME "eTSEC1"
	345	#define CONFIG_TSEC3 1
	346	#define CONFIG_TSEC3_NAME "eTSEC2"
f2cff6b1	347	#define CONFIG_TSEC4
255a3577	348	#define CONFIG_TSEC4_NAME "eTSEC3"
d9b94f28 JL	349	#undef CONFIG_MPC85XX_FEC
	350
	351	#define TSEC1_PHY_ADDR 0
	352	#define TSEC2_PHY_ADDR 1
	353	#define TSEC3_PHY_ADDR 2
	354	#define TSEC4_PHY_ADDR 3
d9b94f28 JL	355
	356	#define TSEC1_PHYIDX 0
	357	#define TSEC2_PHYIDX 0
	358	#define TSEC3_PHYIDX 0
	359	#define TSEC4_PHYIDX 0
3a79013e AF	360	#define TSEC1_FLAGS TSEC_GIGABIT
	361	#define TSEC2_FLAGS TSEC_GIGABIT
	362	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	363	#define TSEC4_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
d9b94f28 JL	364	#endif /* CONFIG_TSEC_ENET */
	365
	366	/*
	367	* Environment
	368	*/
d9b94f28 JL	369
d9b94f28 JL	370	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	371	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d9b94f28	372
d9b94f28 JL	373	/*
	374	* Miscellaneous configurable options
	375	*/
d9b94f28 JL	376
	377	/*
	378	* For booting Linux, the board info and command line data
a832ac41	379	* have to be in the first 64 MB of memory, since this is
d9b94f28 JL	380	* the maximum mapped by the Linux kernel during initialization.
d9b94f28 JL	381	*/
a832ac41 KG	382	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	383	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
d9b94f28	384
d9b94f28 JL	385	/*
	386	* Environment Configuration
	387	*/
d9b94f28	388
f2cff6b1	389	#define CONFIG_IPADDR 192.168.1.253
d9b94f28	390
5bc0543d	391	#define CONFIG_HOSTNAME "unknown"
8b3637c6	392	#define CONFIG_ROOTPATH "/nfsroot"
f2cff6b1	393	#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
d9b94f28	394
f2cff6b1	395	#define CONFIG_SERVERIP 192.168.1.1
d9b94f28	396	#define CONFIG_GATEWAYIP 192.168.1.1
f2cff6b1	397	#define CONFIG_NETMASK 255.255.255.0
d9b94f28	398
867b06f4	399	#define CONFIG_EXTRA_ENV_SETTINGS \
	400	"hwconfig=fsl_ddr:ecc=off\0" \
	401	"netdev=eth0\0" \
5368c55d	402	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
867b06f4	403	"tftpflash=tftpboot $loadaddr $uboot; " \
5368c55d MV	404	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	405	" +$filesize; " \
	406	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	407	" +$filesize; " \
	408	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	409	" $filesize; " \
	410	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	411	" +$filesize; " \
	412	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	413	" $filesize\0" \
867b06f4	414	"consoledev=ttyS1\0" \
	415	"ramdiskaddr=2000000\0" \
	416	"ramdiskfile=ramdisk.uboot\0" \
b24a4f62	417	"fdtaddr=1e00000\0" \
867b06f4	418	"fdtfile=mpc8548cds.dtb\0"
f2cff6b1	419
d9b94f28	420	#endif /* __CONFIG_H */