[J-u-boot.git] / include / i2c.h

/*
 * Copyright (C) 2009 Sergey Kubushyn <[email protected]>
 * Copyright (C) 2009 - 2013 Heiko Schocher <[email protected]>
 * Changes for multibus/multiadapter I2C support.
 *
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * The original I2C interface was
 *   (C) 2000 by Paolo Scaffardi ([email protected])
 *   AIRVENT SAM s.p.a - RIMINI(ITALY)
 * but has been changed substantially.
 */

#ifndef _I2C_H_
#define _I2C_H_

/*
 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
 *
 * The implementation MUST NOT use static or global variables if the
 * I2C routines are used to read SDRAM configuration information
 * because this is done before the memories are initialized. Limited
 * use of stack-based variables are OK (the initial stack size is
 * limited).
 *
 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
 */

/*
 * Configuration items.
 */
#define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */

#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
/* no muxes used bus = i2c adapters */
#define CONFIG_SYS_I2C_DIRECT_BUS	1
#define CONFIG_SYS_I2C_MAX_HOPS		0
#define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
#else
/* we use i2c muxes */
#undef CONFIG_SYS_I2C_DIRECT_BUS
#endif

/* define the I2C bus number for RTC and DTT if not already done */
#if !defined(CONFIG_SYS_RTC_BUS_NUM)
#define CONFIG_SYS_RTC_BUS_NUM		0
#endif
#if !defined(CONFIG_SYS_DTT_BUS_NUM)
#define CONFIG_SYS_DTT_BUS_NUM		0
#endif
#if !defined(CONFIG_SYS_SPD_BUS_NUM)
#define CONFIG_SYS_SPD_BUS_NUM		0
#endif

struct i2c_adapter {
	void		(*init)(struct i2c_adapter *adap, int speed,
				int slaveaddr);
	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len);
	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
				uint addr, int alen, uint8_t *buffer,
				int len);
	uint		(*set_bus_speed)(struct i2c_adapter *adap,
				uint speed);
	int		speed;
	int		waitdelay;
	int		slaveaddr;
	int		init_done;
	int		hwadapnr;
	char		*name;
};

#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
	{ \
		.init		=	_init, \
		.probe		=	_probe, \
		.read		=	_read, \
		.write		=	_write, \
		.set_bus_speed	=	_set_speed, \
		.speed		=	_speed, \
		.slaveaddr	=	_slaveaddr, \
		.init_done	=	0, \
		.hwadapnr	=	_hwadapnr, \
		.name		=	#_name \
};

#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
			_set_speed, _speed, _slaveaddr, _hwadapnr) \
	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);

struct i2c_adapter *i2c_get_adapter(int index);

#ifndef CONFIG_SYS_I2C_DIRECT_BUS
struct i2c_mux {
	int	id;
	char	name[16];
};

struct i2c_next_hop {
	struct i2c_mux		mux;
	uint8_t		chip;
	uint8_t		channel;
};

struct i2c_bus_hose {
	int	adapter;
	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
};
#define I2C_NULL_HOP	{{-1, ""}, 0, 0}
extern struct i2c_bus_hose	i2c_bus[];

#define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
#else
#define I2C_ADAPTER(bus)	bus
#endif
#define	I2C_BUS			gd->cur_i2c_bus

#define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
#define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
#define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)

#ifndef CONFIG_SYS_I2C_DIRECT_BUS
#define I2C_MUX_PCA9540_ID	1
#define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
#define I2C_MUX_PCA9542_ID	2
#define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
#define I2C_MUX_PCA9544_ID	3
#define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
#define I2C_MUX_PCA9547_ID	4
#define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
#define I2C_MUX_PCA9548_ID	5
#define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
#endif

#ifndef I2C_SOFT_DECLARATIONS
# if defined(CONFIG_MPC8260)
#  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
# elif defined(CONFIG_8xx)
#  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;

# elif (defined(CONFIG_AT91RM9200) || \
	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
	defined(CONFIG_AT91SAM9263))
#  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
# else
#  define I2C_SOFT_DECLARATIONS
# endif
#endif

#ifdef CONFIG_8xx
/* Set default value for the I2C bus speed on 8xx. In the
 * future, we'll define these in all 8xx board config files.
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif
#endif

/*
 * Many boards/controllers/drivers don't support an I2C slave interface so
 * provide a default slave address for them for use in common code.  A real
 * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
 * support a slave interface.
 */
#ifndef	CONFIG_SYS_I2C_SLAVE
#define	CONFIG_SYS_I2C_SLAVE	0xfe
#endif

/*
 * Initialization, must be called once on start up, may be called
 * repeatedly to change the speed and slave addresses.
 */
void i2c_init(int speed, int slaveaddr);
void i2c_init_board(void);
#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
void i2c_board_late_init(void);
#endif

#ifdef CONFIG_SYS_I2C
/*
 * i2c_get_bus_num:
 *
 *  Returns index of currently active I2C bus.  Zero-based.
 */
unsigned int i2c_get_bus_num(void);

/*
 * i2c_set_bus_num:
 *
 *  Change the active I2C bus.  Subsequent read/write calls will
 *  go to this one.
 *
 *	bus - bus index, zero based
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_num(unsigned int bus);

/*
 * i2c_init_all():
 *
 * Initializes all I2C adapters in the system. All i2c_adap structures must
 * be initialized beforehead with function pointers and data, including
 * speed and slaveaddr. Returns 0 on success, non-0 on failure.
 */
void i2c_init_all(void);

/*
 * Probe the given I2C chip address.  Returns 0 if a chip responded,
 * not 0 on failure.
 */
int i2c_probe(uint8_t chip);

/*
 * Read/Write interface:
 *   chip:    I2C chip address, range 0..127
 *   addr:    Memory (register) address within the chip
 *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 *              memories, 0 for register type devices with only one
 *              register)
 *   buffer:  Where to read/write the data
 *   len:     How many bytes to read/write
 *
 *   Returns: 0 on success, not 0 on failure
 */
int i2c_read(uint8_t chip, unsigned int addr, int alen,
				uint8_t *buffer, int len);

int i2c_write(uint8_t chip, unsigned int addr, int alen,
				uint8_t *buffer, int len);

/*
 * Utility routines to read/write registers.
 */
uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);

void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);

/*
 * i2c_set_bus_speed:
 *
 *  Change the speed of the active I2C bus
 *
 *	speed - bus speed in Hz
 *
 *	Returns: new bus speed
 *
 */
unsigned int i2c_set_bus_speed(unsigned int speed);

/*
 * i2c_get_bus_speed:
 *
 *  Returns speed of currently active I2C bus in Hz
 */

unsigned int i2c_get_bus_speed(void);

/*
 * i2c_reloc_fixup:
 *
 * Adjusts I2C pointers after U-Boot is relocated to DRAM
 */
void i2c_reloc_fixup(void);
#if defined(CONFIG_SYS_I2C_SOFT)
void i2c_soft_init(void);
void i2c_soft_active(void);
void i2c_soft_tristate(void);
int i2c_soft_read(void);
void i2c_soft_sda(int bit);
void i2c_soft_scl(int bit);
void i2c_soft_delay(void);
#endif
#else

/*
 * Probe the given I2C chip address.  Returns 0 if a chip responded,
 * not 0 on failure.
 */
int i2c_probe(uchar chip);

/*
 * Read/Write interface:
 *   chip:    I2C chip address, range 0..127
 *   addr:    Memory (register) address within the chip
 *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
 *              memories, 0 for register type devices with only one
 *              register)
 *   buffer:  Where to read/write the data
 *   len:     How many bytes to read/write
 *
 *   Returns: 0 on success, not 0 on failure
 */
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);

/*
 * Utility routines to read/write registers.
 */
static inline u8 i2c_reg_read(u8 addr, u8 reg)
{
	u8 buf;

#ifdef CONFIG_8xx
	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

#ifdef DEBUG
	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
#endif

	i2c_read(addr, reg, 1, &buf, 1);

	return buf;
}

static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
{
#ifdef CONFIG_8xx
	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif

#ifdef DEBUG
	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
	       __func__, addr, reg, val);
#endif

	i2c_write(addr, reg, 1, &val, 1);
}

/*
 * Functions for setting the current I2C bus and its speed
 */

/*
 * i2c_set_bus_num:
 *
 *  Change the active I2C bus.  Subsequent read/write calls will
 *  go to this one.
 *
 *	bus - bus index, zero based
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_num(unsigned int bus);

/*
 * i2c_get_bus_num:
 *
 *  Returns index of currently active I2C bus.  Zero-based.
 */

unsigned int i2c_get_bus_num(void);

/*
 * i2c_set_bus_speed:
 *
 *  Change the speed of the active I2C bus
 *
 *	speed - bus speed in Hz
 *
 *	Returns: 0 on success, not 0 on failure
 *
 */
int i2c_set_bus_speed(unsigned int);

/*
 * i2c_get_bus_speed:
 *
 *  Returns speed of currently active I2C bus in Hz
 */

unsigned int i2c_get_bus_speed(void);
#endif /* CONFIG_SYS_I2C */

/*
 * only for backwardcompatibility, should go away if we switched
 * completely to new multibus support.
 */
#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
# if !defined(CONFIG_SYS_MAX_I2C_BUS)
#  define CONFIG_SYS_MAX_I2C_BUS		2
# endif
# define I2C_MULTI_BUS				1
#else
# define CONFIG_SYS_MAX_I2C_BUS		1
# define I2C_MULTI_BUS				0
#endif

/* NOTE: These two functions MUST be always_inline to avoid code growth! */
static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
static inline unsigned int I2C_GET_BUS(void)
{
	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
}

static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
static inline void I2C_SET_BUS(unsigned int bus)
{
	if (I2C_MULTI_BUS)
		i2c_set_bus_num(bus);
}

/* Multi I2C definitions */
enum {
	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
	I2C_8, I2C_9, I2C_10,
};

/* Multi I2C busses handling */
#ifdef CONFIG_SOFT_I2C_MULTI_BUS
extern int get_multi_scl_pin(void);
extern int get_multi_sda_pin(void);
extern int multi_i2c_init(void);
#endif

/**
 * Get FDT values for i2c bus.
 *
 * @param blob  Device tree blbo
 * @return the number of I2C bus
 */
void board_i2c_init(const void *blob);

/**
 * Find the I2C bus number by given a FDT I2C node.
 *
 * @param blob  Device tree blbo
 * @param node  FDT I2C node to find
 * @return the number of I2C bus (zero based), or -1 on error
 */
int i2c_get_bus_num_fdt(int node);

/**
 * Reset the I2C bus represented by the given a FDT I2C node.
 *
 * @param blob  Device tree blbo
 * @param node  FDT I2C node to find
 * @return 0 if port was reset, -1 if not found
 */
int i2c_reset_port_fdt(const void *blob, int node);
#endif	/* _I2C_H_ */
Commit	Line	Data
1f045217	1	/*
385c9ef5 HS	2	* Copyright (C) 2009 Sergey Kubushyn <[email protected]>
	3	* Copyright (C) 2009 - 2013 Heiko Schocher <[email protected]>
	4	* Changes for multibus/multiadapter I2C support.
	5	*
1f045217 WD	6	* (C) Copyright 2001
	7	* Gerald Van Baren, Custom IDEAS, [email protected].
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
1f045217 WD	10	*
	11	* The original I2C interface was
	12	* (C) 2000 by Paolo Scaffardi ([email protected])
	13	* AIRVENT SAM s.p.a - RIMINI(ITALY)
	14	* but has been changed substantially.
	15	*/
	16
	17	#ifndef _I2C_H_
	18	#define _I2C_H_
	19
	20	/*
	21	* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
	22	*
	23	* The implementation MUST NOT use static or global variables if the
	24	* I2C routines are used to read SDRAM configuration information
	25	* because this is done before the memories are initialized. Limited
	26	* use of stack-based variables are OK (the initial stack size is
	27	* limited).
	28	*
	29	* WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
	30	*/
	31
	32	/*
	33	* Configuration items.
	34	*/
	35	#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
	36
385c9ef5 HS	37	#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
	38	/* no muxes used bus = i2c adapters */
	39	#define CONFIG_SYS_I2C_DIRECT_BUS 1
	40	#define CONFIG_SYS_I2C_MAX_HOPS 0
	41	#define CONFIG_SYS_NUM_I2C_BUSES ll_entry_count(struct i2c_adapter, i2c)
79b2d0bb	42	#else
385c9ef5 HS	43	/* we use i2c muxes */
385c9ef5 HS	44	#undef CONFIG_SYS_I2C_DIRECT_BUS
79b2d0bb SR	45	#endif
79b2d0bb SR	46
8c12045a	47	/* define the I2C bus number for RTC and DTT if not already done */
6d0f6bcf JCPV	48	#if !defined(CONFIG_SYS_RTC_BUS_NUM)
6d0f6bcf JCPV	49	#define CONFIG_SYS_RTC_BUS_NUM 0
8c12045a	50	#endif
6d0f6bcf JCPV	51	#if !defined(CONFIG_SYS_DTT_BUS_NUM)
6d0f6bcf JCPV	52	#define CONFIG_SYS_DTT_BUS_NUM 0
8c12045a	53	#endif
6d0f6bcf JCPV	54	#if !defined(CONFIG_SYS_SPD_BUS_NUM)
6d0f6bcf JCPV	55	#define CONFIG_SYS_SPD_BUS_NUM 0
d8a8ea5c	56	#endif
8c12045a	57
385c9ef5 HS	58	struct i2c_adapter {
	59	void (init)(struct i2c_adapter adap, int speed,
	60	int slaveaddr);
	61	int (probe)(struct i2c_adapter adap, uint8_t chip);
	62	int (read)(struct i2c_adapter adap, uint8_t chip,
	63	uint addr, int alen, uint8_t *buffer,
	64	int len);
	65	int (write)(struct i2c_adapter adap, uint8_t chip,
	66	uint addr, int alen, uint8_t *buffer,
	67	int len);
	68	uint (set_bus_speed)(struct i2c_adapter adap,
	69	uint speed);
	70	int speed;
d5243359	71	int waitdelay;
385c9ef5 HS	72	int slaveaddr;
	73	int init_done;
	74	int hwadapnr;
	75	char *name;
	76	};
	77
	78	#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
	79	_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
	80	{ \
	81	.init = _init, \
	82	.probe = _probe, \
	83	.read = _read, \
	84	.write = _write, \
	85	.set_bus_speed = _set_speed, \
	86	.speed = _speed, \
	87	.slaveaddr = _slaveaddr, \
	88	.init_done = 0, \
	89	.hwadapnr = _hwadapnr, \
	90	.name = #_name \
	91	};
	92
	93	#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
	94	_set_speed, _speed, _slaveaddr, _hwadapnr) \
	95	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
	96	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
	97	_set_speed, _speed, _slaveaddr, _hwadapnr, _name);
	98
	99	struct i2c_adapter *i2c_get_adapter(int index);
	100
	101	#ifndef CONFIG_SYS_I2C_DIRECT_BUS
	102	struct i2c_mux {
	103	int id;
	104	char name[16];
	105	};
	106
	107	struct i2c_next_hop {
	108	struct i2c_mux mux;
	109	uint8_t chip;
	110	uint8_t channel;
	111	};
	112
	113	struct i2c_bus_hose {
	114	int adapter;
	115	struct i2c_next_hop next_hop[CONFIG_SYS_I2C_MAX_HOPS];
	116	};
	117	#define I2C_NULL_HOP {{-1, ""}, 0, 0}
	118	extern struct i2c_bus_hose i2c_bus[];
	119
	120	#define I2C_ADAPTER(bus) i2c_bus[bus].adapter
	121	#else
	122	#define I2C_ADAPTER(bus) bus
	123	#endif
	124	#define I2C_BUS gd->cur_i2c_bus
	125
	126	#define I2C_ADAP_NR(bus) i2c_get_adapter(I2C_ADAPTER(bus))
	127	#define I2C_ADAP I2C_ADAP_NR(gd->cur_i2c_bus)
	128	#define I2C_ADAP_HWNR (I2C_ADAP->hwadapnr)
	129
	130	#ifndef CONFIG_SYS_I2C_DIRECT_BUS
	131	#define I2C_MUX_PCA9540_ID 1
	132	#define I2C_MUX_PCA9540 {I2C_MUX_PCA9540_ID, "PCA9540B"}
	133	#define I2C_MUX_PCA9542_ID 2
	134	#define I2C_MUX_PCA9542 {I2C_MUX_PCA9542_ID, "PCA9542A"}
	135	#define I2C_MUX_PCA9544_ID 3
136	#define I2C_MUX_PCA9544 {I2C_MUX_PCA9544_ID, "PCA9544A"}
137	#define I2C_MUX_PCA9547_ID 4
138	#define I2C_MUX_PCA9547 {I2C_MUX_PCA9547_ID, "PCA9547A"}
e6658749 MB	139	#define I2C_MUX_PCA9548_ID 5
e6658749 MB	140	#define I2C_MUX_PCA9548 {I2C_MUX_PCA9548_ID, "PCA9548"}
385c9ef5 HS	141	#endif
385c9ef5 HS	142
98aed379 HS	143	#ifndef I2C_SOFT_DECLARATIONS
98aed379 HS	144	# if defined(CONFIG_MPC8260)
6d0f6bcf	145	# define I2C_SOFT_DECLARATIONS volatile ioport_t iop = ioport_addr((immap_t )CONFIG_SYS_IMMR, I2C_PORT);
98aed379	146	# elif defined(CONFIG_8xx)
6d0f6bcf	147	# define I2C_SOFT_DECLARATIONS volatile immap_t immr = (immap_t )CONFIG_SYS_IMMR;
0cf0b931 JS	148
	149	# elif (defined(CONFIG_AT91RM9200) \|\| \
	150	defined(CONFIG_AT91SAM9260) \|\| defined(CONFIG_AT91SAM9261) \|\| \
cb96a0a4	151	defined(CONFIG_AT91SAM9263))
78132275	152	# define I2C_SOFT_DECLARATIONS at91_pio_t pio = (at91_pio_t ) ATMEL_BASE_PIOA;
98aed379 HS	153	# else
	154	# define I2C_SOFT_DECLARATIONS
	155	# endif
	156	#endif
ecf5f077 TT	157
ecf5f077 TT	158	#ifdef CONFIG_8xx
9c90a2c8	159	/* Set default value for the I2C bus speed on 8xx. In the
ecf5f077 TT	160	* future, we'll define these in all 8xx board config files.
	161	*/
	162	#ifndef CONFIG_SYS_I2C_SPEED
	163	#define CONFIG_SYS_I2C_SPEED 50000
	164	#endif
9c90a2c8	165	#endif
ecf5f077	166
9c90a2c8 PT	167	/*
	168	* Many boards/controllers/drivers don't support an I2C slave interface so
	169	* provide a default slave address for them for use in common code. A real
	170	* value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
	171	* support a slave interface.
	172	*/
ecf5f077	173	#ifndef CONFIG_SYS_I2C_SLAVE
9c90a2c8	174	#define CONFIG_SYS_I2C_SLAVE 0xfe
ecf5f077 TT	175	#endif
ecf5f077 TT	176
1f045217 WD	177	/*
	178	* Initialization, must be called once on start up, may be called
	179	* repeatedly to change the speed and slave addresses.
	180	*/
	181	void i2c_init(int speed, int slaveaddr);
06d01dbe	182	void i2c_init_board(void);
26a33504 RR	183	#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	184	void i2c_board_late_init(void);
	185	#endif
1f045217	186
385c9ef5	187	#ifdef CONFIG_SYS_I2C
385c9ef5 HS	188	/*
	189	* i2c_get_bus_num:
	190	*
	191	* Returns index of currently active I2C bus. Zero-based.
	192	*/
	193	unsigned int i2c_get_bus_num(void);
	194
	195	/*
	196	* i2c_set_bus_num:
	197	*
	198	* Change the active I2C bus. Subsequent read/write calls will
	199	* go to this one.
	200	*
	201	* bus - bus index, zero based
	202	*
	203	* Returns: 0 on success, not 0 on failure
	204	*
	205	*/
	206	int i2c_set_bus_num(unsigned int bus);
	207
	208	/*
	209	* i2c_init_all():
	210	*
	211	* Initializes all I2C adapters in the system. All i2c_adap structures must
	212	* be initialized beforehead with function pointers and data, including
	213	* speed and slaveaddr. Returns 0 on success, non-0 on failure.
	214	*/
	215	void i2c_init_all(void);
	216
	217	/*
	218	* Probe the given I2C chip address. Returns 0 if a chip responded,
	219	* not 0 on failure.
	220	*/
	221	int i2c_probe(uint8_t chip);
	222
	223	/*
	224	* Read/Write interface:
	225	* chip: I2C chip address, range 0..127
	226	* addr: Memory (register) address within the chip
	227	* alen: Number of bytes to use for addr (typically 1, 2 for larger
	228	* memories, 0 for register type devices with only one
	229	* register)
	230	* buffer: Where to read/write the data
	231	* len: How many bytes to read/write
	232	*
	233	* Returns: 0 on success, not 0 on failure
	234	*/
	235	int i2c_read(uint8_t chip, unsigned int addr, int alen,
	236	uint8_t *buffer, int len);
	237
	238	int i2c_write(uint8_t chip, unsigned int addr, int alen,
	239	uint8_t *buffer, int len);
	240
	241	/*
	242	* Utility routines to read/write registers.
	243	*/
	244	uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
	245
	246	void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
	247
	248	/*
	249	* i2c_set_bus_speed:
	250	*
	251	* Change the speed of the active I2C bus
252	*
253	* speed - bus speed in Hz
254	*
255	* Returns: new bus speed
256	*
257	*/
258	unsigned int i2c_set_bus_speed(unsigned int speed);
67b23a32	259
385c9ef5 HS	260	/*
	261	* i2c_get_bus_speed:
	262	*
	263	* Returns speed of currently active I2C bus in Hz
	264	*/
67b23a32	265
385c9ef5	266	unsigned int i2c_get_bus_speed(void);
67b23a32	267
385c9ef5 HS	268	/*
	269	* i2c_reloc_fixup:
	270	*
	271	* Adjusts I2C pointers after U-Boot is relocated to DRAM
	272	*/
	273	void i2c_reloc_fixup(void);
ea818dbb HS	274	#if defined(CONFIG_SYS_I2C_SOFT)
	275	void i2c_soft_init(void);
	276	void i2c_soft_active(void);
	277	void i2c_soft_tristate(void);
	278	int i2c_soft_read(void);
	279	void i2c_soft_sda(int bit);
	280	void i2c_soft_scl(int bit);
	281	void i2c_soft_delay(void);
67b23a32	282	#endif
385c9ef5	283	#else
67b23a32	284
1f045217 WD	285	/*
	286	* Probe the given I2C chip address. Returns 0 if a chip responded,
	287	* not 0 on failure.
	288	*/
	289	int i2c_probe(uchar chip);
	290
	291	/*
	292	* Read/Write interface:
	293	* chip: I2C chip address, range 0..127
	294	* addr: Memory (register) address within the chip
	295	* alen: Number of bytes to use for addr (typically 1, 2 for larger
	296	* memories, 0 for register type devices with only one
	297	* register)
	298	* buffer: Where to read/write the data
	299	* len: How many bytes to read/write
	300	*
	301	* Returns: 0 on success, not 0 on failure
	302	*/
	303	int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
	304	int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
	305
	306	/*
	307	* Utility routines to read/write registers.
	308	*/
ecf5f077 TT	309	static inline u8 i2c_reg_read(u8 addr, u8 reg)
	310	{
	311	u8 buf;
	312
	313	#ifdef CONFIG_8xx
	314	/* MPC8xx needs this. Maybe one day we can get rid of it. */
	315	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	316	#endif
	317
	318	#ifdef DEBUG
	319	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
	320	#endif
	321
ecf5f077	322	i2c_read(addr, reg, 1, &buf, 1);
ecf5f077 TT	323
	324	return buf;
	325	}
	326
	327	static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
	328	{
	329	#ifdef CONFIG_8xx
	330	/* MPC8xx needs this. Maybe one day we can get rid of it. */
	331	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	332	#endif
	333
	334	#ifdef DEBUG
	335	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
	336	__func__, addr, reg, val);
	337	#endif
	338
ecf5f077	339	i2c_write(addr, reg, 1, &val, 1);
ecf5f077	340	}
1f045217	341
bb99ad6d BW	342	/*
	343	* Functions for setting the current I2C bus and its speed
	344	*/
	345
	346	/*
	347	* i2c_set_bus_num:
	348	*
	349	* Change the active I2C bus. Subsequent read/write calls will
	350	* go to this one.
	351	*
53677ef1	352	* bus - bus index, zero based
bb99ad6d	353	*
53677ef1	354	* Returns: 0 on success, not 0 on failure
bb99ad6d BW	355	*
bb99ad6d BW	356	*/
9ca880a2	357	int i2c_set_bus_num(unsigned int bus);
bb99ad6d BW	358
	359	/*
	360	* i2c_get_bus_num:
	361	*
	362	* Returns index of currently active I2C bus. Zero-based.
	363	*/
	364
9ca880a2	365	unsigned int i2c_get_bus_num(void);
bb99ad6d BW	366
	367	/*
	368	* i2c_set_bus_speed:
	369	*
	370	* Change the speed of the active I2C bus
	371	*
53677ef1	372	* speed - bus speed in Hz
bb99ad6d	373	*
53677ef1	374	* Returns: 0 on success, not 0 on failure
bb99ad6d BW	375	*
bb99ad6d BW	376	*/
9ca880a2	377	int i2c_set_bus_speed(unsigned int);
bb99ad6d BW	378
	379	/*
	380	* i2c_get_bus_speed:
	381	*
	382	* Returns speed of currently active I2C bus in Hz
	383	*/
	384
9ca880a2	385	unsigned int i2c_get_bus_speed(void);
385c9ef5 HS	386	#endif /* CONFIG_SYS_I2C */
	387
	388	/*
	389	* only for backwardcompatibility, should go away if we switched
	390	* completely to new multibus support.
	391	*/
	392	#if defined(CONFIG_SYS_I2C) \|\| defined(CONFIG_I2C_MULTI_BUS)
	393	# if !defined(CONFIG_SYS_MAX_I2C_BUS)
	394	# define CONFIG_SYS_MAX_I2C_BUS 2
	395	# endif
ea0f73ab	396	# define I2C_MULTI_BUS 1
385c9ef5 HS	397	#else
	398	# define CONFIG_SYS_MAX_I2C_BUS 1
	399	# define I2C_MULTI_BUS 0
	400	#endif
bb99ad6d	401
cd7b4e82 MV	402	/* NOTE: These two functions MUST be always_inline to avoid code growth! */
	403	static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
	404	static inline unsigned int I2C_GET_BUS(void)
	405	{
	406	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
	407	}
	408
	409	static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
	410	static inline void I2C_SET_BUS(unsigned int bus)
	411	{
	412	if (I2C_MULTI_BUS)
	413	i2c_set_bus_num(bus);
	414	}
	415
7ca8f73a ŁM	416	/* Multi I2C definitions */
	417	enum {
	418	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
	419	I2C_8, I2C_9, I2C_10,
	420	};
	421
	422	/* Multi I2C busses handling */
	423	#ifdef CONFIG_SOFT_I2C_MULTI_BUS
	424	extern int get_multi_scl_pin(void);
	425	extern int get_multi_sda_pin(void);
	426	extern int multi_i2c_init(void);
	427	#endif
a9d2ae70 RS	428
	429	/**
	430	* Get FDT values for i2c bus.
	431	*
	432	* @param blob Device tree blbo
	433	* @return the number of I2C bus
	434	*/
	435	void board_i2c_init(const void *blob);
	436
	437	/**
	438	* Find the I2C bus number by given a FDT I2C node.
	439	*
	440	* @param blob Device tree blbo
	441	* @param node FDT I2C node to find
	442	* @return the number of I2C bus (zero based), or -1 on error
	443	*/
	444	int i2c_get_bus_num_fdt(int node);
	445
	446	/**
	447	* Reset the I2C bus represented by the given a FDT I2C node.
	448	*
	449	* @param blob Device tree blbo
	450	* @param node FDT I2C node to find
	451	* @return 0 if port was reset, -1 if not found
	452	*/
	453	int i2c_reset_port_fdt(const void *blob, int node);
1f045217	454	#endif /* _I2C_H_ */