[J-u-boot.git] / include / fsl_mdio.h

/*
 * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
 *	Jun-jie Zhang <[email protected]>
 *	Mingkai Hu <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __FSL_PHY_H__
#define __FSL_PHY_H__

#include <net.h>
#include <miiphy.h>
#include <asm/fsl_enet.h>

/* PHY register offsets */
#define PHY_EXT_PAGE_ACCESS	0x1f

/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT          0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT   0x00000007
#define MIIMCFG_INIT_VALUE	    0x00000003

/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE	0x00000001
#define MIIMCOM_SCAN_CYCLE	0x00000002

/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT	8

/* MII Management Indicator Register */
#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004

void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
		int dev_addr, int reg, int value);
int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
		int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
		u16 value);
int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum, u16 value);
int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
		int regnum);

struct fsl_pq_mdio_info {
	struct tsec_mii_mng __iomem *regs;
	char *name;
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);

#endif /* __FSL_PHY_H__ */
Commit	Line	Data
063c1263	1	/*
5be00a01	2	* Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
063c1263 AF	3	* Jun-jie Zhang <[email protected]>
	4	* Mingkai Hu <[email protected]>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
063c1263 AF	7	*/
	8	#ifndef __FSL_PHY_H__
	9	#define __FSL_PHY_H__
	10
	11	#include <net.h>
	12	#include <miiphy.h>
	13	#include <asm/fsl_enet.h>
	14
	15	/* PHY register offsets */
	16	#define PHY_EXT_PAGE_ACCESS 0x1f
	17
	18	/* MII Management Configuration Register */
	19	#define MIIMCFG_RESET_MGMT 0x80000000
	20	#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
	21	#define MIIMCFG_INIT_VALUE 0x00000003
	22
	23	/* MII Management Command Register */
	24	#define MIIMCOM_READ_CYCLE 0x00000001
	25	#define MIIMCOM_SCAN_CYCLE 0x00000002
	26
	27	/* MII Management Address Register */
	28	#define MIIMADD_PHY_ADDR_SHIFT 8
	29
	30	/* MII Management Indicator Register */
	31	#define MIIMIND_BUSY 0x00000001
	32	#define MIIMIND_NOTVALID 0x00000004
	33
5be00a01	34	void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
063c1263	35	int dev_addr, int reg, int value);
5be00a01	36	int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
063c1263 AF	37	int dev_addr, int regnum);
	38	int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
	39	int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
	40	u16 value);
111fd19e RZ	41	int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
	42	int regnum, u16 value);
	43	int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
	44	int regnum);
063c1263 AF	45
063c1263 AF	46	struct fsl_pq_mdio_info {
5be00a01	47	struct tsec_mii_mng __iomem *regs;
063c1263 AF	48	char *name;
	49	};
	50	int fsl_pq_mdio_init(bd_t bis, struct fsl_pq_mdio_info info);
	51
	52	#endif /* __FSL_PHY_H__ */