projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 6cb144bc ML |
1 | /* |
| 2 | * Copyright (C) 2011 Andes Technology Corporation | |
| 3 | * Shawn Lin, Andes Technology Corporation <[email protected]> | |
| 4 | * Macpaul Lin, Andes Technology Corporation <[email protected]> | |
| 5 | * | |
| 1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 6cb144bc ML |
7 | */ |
| 8 | ||
| 9 | #ifndef __CONFIG_H | |
| 10 | #define __CONFIG_H | |
| 11 | ||
| 12 | #include <asm/arch/ag101.h> | |
| 13 | ||
| 14 | /* | |
| 15 | * CPU and Board Configuration Options | |
| 16 | */ | |
| 17 | #define CONFIG_ADP_AG101P | |
| 18 | ||
| 19 | #define CONFIG_USE_INTERRUPT | |
| 20 | ||
| 21 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
| 22 | ||
| e3c58b02 | 23 | /* |
| 24 | * Definitions related to passing arguments to kernel. | |
| 25 | */ | |
| 26 | #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ | |
| 27 | #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ | |
| 28 | #define CONFIG_INITRD_TAG /* send initrd params */ | |
| 29 | ||
| 6cb144bc ML |
30 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
| 31 | #define CONFIG_MEM_REMAP | |
| 32 | #endif | |
| 33 | ||
| 34 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
| 35 | #define CONFIG_SYS_TEXT_BASE 0x03200000 | |
| 36 | #else | |
| 37 | #define CONFIG_SYS_TEXT_BASE 0x00000000 | |
| 38 | #endif | |
| 39 | ||
| 40 | /* | |
| 41 | * Timer | |
| 42 | */ | |
| 6cb144bc ML |
43 | #define CONFIG_SYS_CLK_FREQ 39062500 |
| 44 | #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ | |
| 45 | ||
| 46 | /* | |
| 47 | * Use Externel CLOCK or PCLK | |
| 48 | */ | |
| 49 | #undef CONFIG_FTRTC010_EXTCLK | |
| 50 | ||
| 51 | #ifndef CONFIG_FTRTC010_EXTCLK | |
| 52 | #define CONFIG_FTRTC010_PCLK | |
| 53 | #endif | |
| 54 | ||
| 55 | #ifdef CONFIG_FTRTC010_EXTCLK | |
| 56 | #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ | |
| 57 | #else | |
| 58 | #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ | |
| 59 | #endif | |
| 60 | ||
| 61 | #define TIMER_LOAD_VAL 0xffffffff | |
| 62 | ||
| 63 | /* | |
| 64 | * Real Time Clock | |
| 65 | */ | |
| 66 | #define CONFIG_RTC_FTRTC010 | |
| 67 | ||
| 68 | /* | |
| 69 | * Real Time Clock Divider | |
| 70 | * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) | |
| 71 | */ | |
| 72 | #define OSC_5MHZ (5*1000000) | |
| 73 | #define OSC_CLK (4*OSC_5MHZ) | |
| 74 | #define RTC_DIV_COUNT (0.5) /* Why?? */ | |
| 75 | ||
| 76 | /* | |
| 77 | * Serial console configuration | |
| 78 | */ | |
| 79 | ||
| 80 | /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ | |
| 81 | #define CONFIG_BAUDRATE 38400 | |
| 82 | #define CONFIG_CONS_INDEX 1 | |
| 83 | #define CONFIG_SYS_NS16550 | |
| 84 | #define CONFIG_SYS_NS16550_SERIAL | |
| 85 | #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE | |
| 86 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
| 87 | #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ | |
| 88 | ||
| 6cb144bc ML |
89 | /* |
| 90 | * Ethernet | |
| 91 | */ | |
| 92 | #define CONFIG_FTMAC100 | |
| 93 | ||
| 94 | #define CONFIG_BOOTDELAY 3 | |
| 95 | ||
| 96 | /* | |
| 97 | * SD (MMC) controller | |
| 98 | */ | |
| 99 | #define CONFIG_MMC | |
| 100 | #define CONFIG_CMD_MMC | |
| 101 | #define CONFIG_GENERIC_MMC | |
| 102 | #define CONFIG_DOS_PARTITION | |
| 103 | #define CONFIG_FTSDC010 | |
| 104 | #define CONFIG_FTSDC010_NUMBER 1 | |
| 61ccf082 | 105 | #define CONFIG_FTSDC010_SDIO |
| 6cb144bc | 106 | #define CONFIG_CMD_FAT |
| 61ccf082 | 107 | #define CONFIG_CMD_EXT2 |
| 6cb144bc ML |
108 | |
| 109 | /* | |
| 110 | * Command line configuration. | |
| 111 | */ | |
| 112 | #include <config_cmd_default.h> | |
| 113 | ||
| 114 | #define CONFIG_CMD_CACHE | |
| 115 | #define CONFIG_CMD_DATE | |
| 116 | #define CONFIG_CMD_PING | |
| 117 | ||
| 118 | /* | |
| 119 | * Miscellaneous configurable options | |
| 120 | */ | |
| 121 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 122 | #define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */ | |
| 123 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 124 | ||
| 125 | /* Print Buffer Size */ | |
| 126 | #define CONFIG_SYS_PBSIZE \ | |
| 127 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 128 | ||
| 129 | /* max number of command args */ | |
| 130 | #define CONFIG_SYS_MAXARGS 16 | |
| 131 | ||
| 132 | /* Boot Argument Buffer Size */ | |
| 133 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 134 | ||
| 6cb144bc ML |
135 | /* |
| 136 | * Size of malloc() pool | |
| 137 | */ | |
| 138 | /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ | |
| 139 | #define CONFIG_SYS_MALLOC_LEN (512 << 10) | |
| 140 | ||
| 6cb144bc ML |
141 | /* |
| 142 | * AHB Controller configuration | |
| 143 | */ | |
| 144 | #define CONFIG_FTAHBC020S | |
| 145 | ||
| 146 | #ifdef CONFIG_FTAHBC020S | |
| 147 | #include <faraday/ftahbc020s.h> | |
| 148 | ||
| 149 | /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ | |
| 150 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 | |
| 151 | ||
| 152 | /* | |
| 153 | * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, | |
| 154 | * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote | |
| 155 | * in C language. | |
| 156 | */ | |
| 157 | #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ | |
| 158 | (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ | |
| 159 | FTAHBC020S_SLAVE_BSR_SIZE(0xb)) | |
| 160 | #endif | |
| 161 | ||
| 162 | /* | |
| 163 | * Watchdog | |
| 164 | */ | |
| 165 | #define CONFIG_FTWDT010_WATCHDOG | |
| 166 | ||
| 167 | /* | |
| 168 | * PMU Power controller configuration | |
| 169 | */ | |
| 170 | #define CONFIG_PMU | |
| 171 | #define CONFIG_FTPMU010_POWER | |
| 172 | ||
| 173 | #ifdef CONFIG_FTPMU010_POWER | |
| 174 | #include <faraday/ftpmu010.h> | |
| 175 | #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E | |
| 176 | #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ | |
| 177 | FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ | |
| 178 | FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ | |
| 179 | FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ | |
| 180 | FTPMU010_SDRAMHTC_CKE_DCSR | \ | |
| 181 | FTPMU010_SDRAMHTC_DQM_DCSR | \ | |
| 182 | FTPMU010_SDRAMHTC_SDCLK_DCSR) | |
| 183 | #endif | |
| 184 | ||
| 185 | /* | |
| 186 | * SDRAM controller configuration | |
| 187 | */ | |
| 188 | #define CONFIG_FTSDMC021 | |
| 189 | ||
| 190 | #ifdef CONFIG_FTSDMC021 | |
| 191 | #include <faraday/ftsdmc021.h> | |
| 192 | ||
| 193 | #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ | |
| 194 | FTSDMC021_TP1_TRP(1) | \ | |
| 195 | FTSDMC021_TP1_TRCD(1) | \ | |
| 196 | FTSDMC021_TP1_TRF(3) | \ | |
| 197 | FTSDMC021_TP1_TWR(1) | \ | |
| 198 | FTSDMC021_TP1_TCL(2)) | |
| 199 | ||
| 200 | #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ | |
| 201 | FTSDMC021_TP2_INI_REFT(8) | \ | |
| 202 | FTSDMC021_TP2_REF_INTV(0x180)) | |
| 203 | ||
| 204 | /* | |
| 205 | * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, | |
| 206 | * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in | |
| 207 | * C language. | |
| 208 | */ | |
| 209 | #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ | |
| 210 | FTSDMC021_CR1_DSZ(3) | \ | |
| 211 | FTSDMC021_CR1_MBW(2) | \ | |
| 212 | FTSDMC021_CR1_BNKSIZE(6)) | |
| 213 | ||
| 214 | #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ | |
| 215 | FTSDMC021_CR2_IREF | \ | |
| 216 | FTSDMC021_CR2_ISMR) | |
| 217 | ||
| 218 | #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE | |
| 219 | #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ | |
| 220 | CONFIG_SYS_FTSDMC021_BANK0_BASE) | |
| 221 | ||
| 3c016704 | 222 | #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ |
| 223 | (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) | |
| 224 | #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ | |
| 225 | CONFIG_SYS_FTSDMC021_BANK1_BASE) | |
| 6cb144bc ML |
226 | #endif |
| 227 | ||
| 228 | /* | |
| 229 | * Physical Memory Map | |
| 230 | */ | |
| 231 | #if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT) | |
| 232 | #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ | |
| 233 | #if defined(CONFIG_MEM_REMAP) | |
| 234 | #define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/ | |
| 235 | #endif | |
| 236 | #else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */ | |
| 237 | #define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */ | |
| 238 | #endif | |
| 3c016704 | 239 | #define PHYS_SDRAM_1 \ |
| 240 | (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ | |
| 6cb144bc | 241 | |
| 3c016704 | 242 | #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ |
| 6cb144bc | 243 | #define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */ |
| 3c016704 | 244 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
| 6cb144bc ML |
245 | |
| 246 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 | |
| 247 | ||
| 248 | #ifdef CONFIG_MEM_REMAP | |
| 249 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ | |
| 250 | GENERATED_GBL_DATA_SIZE) | |
| 251 | #else | |
| 252 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
| 253 | GENERATED_GBL_DATA_SIZE) | |
| 254 | #endif /* CONFIG_MEM_REMAP */ | |
| 255 | ||
| 256 | /* | |
| 257 | * Load address and memory test area should agree with | |
| 258 | * arch/nds32/config.mk. Be careful not to overwrite U-boot itself. | |
| 259 | */ | |
| 260 | #define CONFIG_SYS_LOAD_ADDR 0x300000 | |
| 261 | ||
| 262 | /* memtest works on 63 MB in DRAM */ | |
| 263 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 | |
| 264 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) | |
| 265 | ||
| 266 | /* | |
| 267 | * Static memory controller configuration | |
| 268 | */ | |
| 269 | #define CONFIG_FTSMC020 | |
| 270 | ||
| 271 | #ifdef CONFIG_FTSMC020 | |
| 272 | #include <faraday/ftsmc020.h> | |
| 273 | ||
| 274 | #define CONFIG_SYS_FTSMC020_CONFIGS { \ | |
| 275 | { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ | |
| 276 | { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ | |
| 277 | } | |
| 278 | ||
| 279 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ | |
| 280 | #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ | |
| 281 | FTSMC020_BANK_SIZE_32M | \ | |
| 282 | FTSMC020_BANK_MBW_32) | |
| 283 | ||
| 284 | #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ | |
| 285 | FTSMC020_TPR_AST(1) | \ | |
| 286 | FTSMC020_TPR_CTW(1) | \ | |
| 287 | FTSMC020_TPR_ATI(1) | \ | |
| 288 | FTSMC020_TPR_AT2(1) | \ | |
| 289 | FTSMC020_TPR_WTC(1) | \ | |
| 290 | FTSMC020_TPR_AHT(1) | \ | |
| 291 | FTSMC020_TPR_TRNA(1)) | |
| 292 | #endif | |
| 293 | ||
| 294 | /* | |
| 295 | * FLASH on ADP_AG101P is connected to BANK0 | |
| 296 | * Just disalbe the other BANK to avoid detection error. | |
| 297 | */ | |
| 298 | #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ | |
| 299 | FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ | |
| 300 | FTSMC020_BANK_SIZE_32M | \ | |
| 301 | FTSMC020_BANK_MBW_32) | |
| 302 | ||
| 303 | #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ | |
| 304 | FTSMC020_TPR_CTW(3) | \ | |
| 305 | FTSMC020_TPR_ATI(0xf) | \ | |
| 306 | FTSMC020_TPR_AT2(3) | \ | |
| 307 | FTSMC020_TPR_WTC(3) | \ | |
| 308 | FTSMC020_TPR_AHT(3) | \ | |
| 309 | FTSMC020_TPR_TRNA(0xf)) | |
| 310 | ||
| 311 | #define FTSMC020_BANK1_CONFIG (0x00) | |
| 312 | #define FTSMC020_BANK1_TIMING (0x00) | |
| 313 | #endif /* CONFIG_FTSMC020 */ | |
| 314 | ||
| 315 | /* | |
| 316 | * FLASH and environment organization | |
| 317 | */ | |
| 318 | /* use CFI framework */ | |
| 319 | #define CONFIG_SYS_FLASH_CFI | |
| 320 | #define CONFIG_FLASH_CFI_DRIVER | |
| 321 | ||
| 322 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 323 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 324 | ||
| 325 | /* support JEDEC */ | |
| 326 | ||
| 327 | /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ | |
| 328 | #ifdef CONFIG_SKIP_LOWLEVEL_INIT | |
| 329 | #define PHYS_FLASH_1 0x80400000 /* BANK 1 */ | |
| 330 | #else /* !CONFIG_SKIP_LOWLEVEL_INIT */ | |
| 331 | #ifdef CONFIG_MEM_REMAP | |
| 332 | #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ | |
| 333 | #else | |
| 334 | #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ | |
| 335 | #endif /* CONFIG_MEM_REMAP */ | |
| 336 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ | |
| 337 | ||
| 338 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 | |
| 339 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } | |
| 340 | #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 | |
| 341 | ||
| 342 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ | |
| 343 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ | |
| 344 | ||
| 345 | /* max number of memory banks */ | |
| 346 | /* | |
| 347 | * There are 4 banks supported for this Controller, | |
| 348 | * but we have only 1 bank connected to flash on board | |
| 349 | */ | |
| 350 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 351 | ||
| 352 | /* max number of sectors on one chip */ | |
| 353 | #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2) | |
| 354 | #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE | |
| 355 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
| 356 | ||
| 357 | /* environments */ | |
| 358 | #define CONFIG_ENV_IS_IN_FLASH | |
| 359 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) | |
| 360 | #define CONFIG_ENV_SIZE 8192 | |
| 361 | #define CONFIG_ENV_OVERWRITE | |
| 362 | ||
| 363 | #endif /* __CONFIG_H */ |