[J-u-boot.git] / include / configs / km / km-mpc83xx.h

/*
 * Internal Definitions
 */
#include <linux/stringify.h>
#define BOOTFLASH_START	0xF0000000

/*
 * DDR Setup
 */
#define CFG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */

#define CFG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)

#define CFG_83XX_DDR_USES_CS0

/*
 * Manually set up DDR parameters
 */
#define CFG_SYS_SDRAM_SIZE		0x80000000 /* 2048 MiB */

/*
 * The reserved memory
 */
#define CFG_SYS_FLASH_BASE		0xF0000000

/* Reserve 768 kB for Mon */

/*
 * Initial RAM Base Address Setup
 */
#define CFG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CFG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
/*
 * Init Local Bus Memory Controller:
 *
 * Bank Bus     Machine PortSz  Size  Device
 * ---- ---     ------- ------  -----  ------
 *  0   Local   GPCM    16 bit  256MB FLASH
 *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 *
 */

/*
 * FLASH on the Local Bus
 */
#define CFG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */

#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }

/* I2C */
#define CFG_SYS_NUM_I2C_BUSES	4
#define CFG_SYS_I2C_MAX_HOPS		1
#define CFG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
		{1, {I2C_NULL_HOP} } }

#if defined(CONFIG_CMD_NAND)
#define CFG_SYS_NAND_BASE		CFG_SYS_KMBEC_FPGA_BASE
#endif

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_SYS_BOOTMAPSZ		(8 << 20)

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
Commit	Line	Data
aed7d0e3 MS	1	/*
	2	* Internal Definitions
	3	*/
1af3c7f4	4	#include <linux/stringify.h>
aed7d0e3 MS	5	#define BOOTFLASH_START 0xF0000000
aed7d0e3 MS	6
aed7d0e3 MS	7	/*
	8	* DDR Setup
	9	*/
aa6e94de	10	#define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
aed7d0e3	11
65cc0e2a	12	#define CFG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \| \
aed7d0e3 MS	13	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
	14
	15	#define CFG_83XX_DDR_USES_CS0
	16
	17	/*
	18	* Manually set up DDR parameters
	19	*/
aa6e94de	20	#define CFG_SYS_SDRAM_SIZE 0x80000000 /* 2048 MiB */
aed7d0e3 MS	21
	22	/*
	23	* The reserved memory
	24	*/
65cc0e2a	25	#define CFG_SYS_FLASH_BASE 0xF0000000
aed7d0e3	26
aed7d0e3	27	/* Reserve 768 kB for Mon */
aed7d0e3 MS	28
	29	/*
	30	* Initial RAM Base Address Setup
	31	*/
65cc0e2a TR	32	#define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
65cc0e2a TR	33	#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
aed7d0e3 MS	34	/*
	35	* Init Local Bus Memory Controller:
	36	*
	37	* Bank Bus Machine PortSz Size Device
	38	* ---- --- ------- ------ ----- ------
	39	* 0 Local GPCM 16 bit 256MB FLASH
	40	* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
	41	*
	42	*/
	43
	44	/*
	45	* FLASH on the Local Bus
	46	*/
65cc0e2a	47	#define CFG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
aed7d0e3	48
65cc0e2a	49	#define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE }
aed7d0e3	50
aed7d0e3	51	/* I2C */
cdc5ed8f	52	#define CFG_SYS_NUM_I2C_BUSES 4
65cc0e2a TR	53	#define CFG_SYS_I2C_MAX_HOPS 1
65cc0e2a TR	54	#define CFG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
aed7d0e3 MS	55	{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
	56	{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
	57	{1, {I2C_NULL_HOP} } }
	58
aed7d0e3	59	#if defined(CONFIG_CMD_NAND)
65cc0e2a	60	#define CFG_SYS_NAND_BASE CFG_SYS_KMBEC_FPGA_BASE
aed7d0e3 MS	61	#endif
	62
	63	/*
	64	* For booting Linux, the board info and command line data
	65	* have to be in the first 8 MB of memory, since this is
	66	* the maximum mapped by the Linux kernel during initialization.
	67	*/
65cc0e2a	68	#define CFG_SYS_BOOTMAPSZ (8 << 20)
aed7d0e3	69
aed7d0e3 MS	70	/*
	71	* QE UEC ethernet configuration
	72	*/
	73	#define CONFIG_UEC_ETH