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Merge branch 'master' of git://git.denx.de/u-boot-arm
[J-u-boot.git] / common / cmd_bdinfo.c
CommitLineData
8bde7f77
WD
1/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Boot support
26 */
27#include <common.h>
28#include <command.h>
29
d87080b7 30DECLARE_GLOBAL_DATA_PTR;
8bde7f77 31
8bde7f77
WD
32static void print_num(const char *, ulong);
33
6fcc3be4
SG
34#if !(defined(CONFIG_ARM) || defined(CONFIG_M68K) || defined(CONFIG_SANDBOX)) \
35 || defined(CONFIG_CMD_NET)
36#define HAVE_PRINT_ETH
de2dff6f 37static void print_eth(int idx);
26e42cbd 38#endif
de2dff6f 39
6fcc3be4
SG
40#if (!defined(CONFIG_ARM) && !defined(CONFIG_X86) && !defined(CONFIG_SANDBOX))
41#define HAVE_PRINT_LNUM
b57ca3e1 42static void print_lnum(const char *, u64);
c99ea790 43#endif
8bde7f77 44
c99ea790 45#if defined(CONFIG_PPC)
0c277ef9 46static void print_mhz(const char *, unsigned long);
8bde7f77 47
5902e8f7 48int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 49{
8bde7f77 50 bd_t *bd = gd->bd;
8bde7f77
WD
51
52#ifdef DEBUG
5902e8f7
ML
53 print_num("bd address", (ulong)bd);
54#endif
55 print_num("memstart", bd->bi_memstart);
56 print_lnum("memsize", bd->bi_memsize);
57 print_num("flashstart", bd->bi_flashstart);
58 print_num("flashsize", bd->bi_flashsize);
59 print_num("flashoffset", bd->bi_flashoffset);
60 print_num("sramstart", bd->bi_sramstart);
61 print_num("sramsize", bd->bi_sramsize);
62#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || \
63 defined(CONFIG_8260) || defined(CONFIG_E500)
64 print_num("immr_base", bd->bi_immr_base);
65#endif
66 print_num("bootflags", bd->bi_bootflags);
67#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
68 defined(CONFIG_405GP) || \
69 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
70 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
71 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
72 defined(CONFIG_XILINX_405)
0c277ef9
TT
73 print_mhz("procfreq", bd->bi_procfreq);
74 print_mhz("plb_busfreq", bd->bi_plb_busfreq);
5902e8f7
ML
75#if defined(CONFIG_405EP) || defined(CONFIG_405GP) || \
76 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
77 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
78 defined(CONFIG_440SPE) || defined(CONFIG_XILINX_405)
0c277ef9 79 print_mhz("pci_busfreq", bd->bi_pci_busfreq);
8bde7f77 80#endif
9fea65a6 81#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
9c4c5ae3 82#if defined(CONFIG_CPM2)
0c277ef9
TT
83 print_mhz("vco", bd->bi_vco);
84 print_mhz("sccfreq", bd->bi_sccfreq);
85 print_mhz("brgfreq", bd->bi_brgfreq);
8bde7f77 86#endif
0c277ef9 87 print_mhz("intfreq", bd->bi_intfreq);
9c4c5ae3 88#if defined(CONFIG_CPM2)
0c277ef9 89 print_mhz("cpmfreq", bd->bi_cpmfreq);
8bde7f77 90#endif
0c277ef9 91 print_mhz("busfreq", bd->bi_busfreq);
9fea65a6 92#endif /* CONFIG_405GP, CONFIG_405CR, CONFIG_405EP, CONFIG_XILINX_405, CONFIG_440EP CONFIG_440GR */
983fda83 93#if defined(CONFIG_MPC8220)
0c277ef9
TT
94 print_mhz("inpfreq", bd->bi_inpfreq);
95 print_mhz("flbfreq", bd->bi_flbfreq);
96 print_mhz("pcifreq", bd->bi_pcifreq);
97 print_mhz("vcofreq", bd->bi_vcofreq);
98 print_mhz("pevfreq", bd->bi_pevfreq);
983fda83 99#endif
03f5c550 100
de2dff6f 101 print_eth(0);
e2ffd59b 102#if defined(CONFIG_HAS_ETH1)
de2dff6f 103 print_eth(1);
03f5c550 104#endif
e2ffd59b 105#if defined(CONFIG_HAS_ETH2)
de2dff6f 106 print_eth(2);
42d1f039 107#endif
e2ffd59b 108#if defined(CONFIG_HAS_ETH3)
de2dff6f 109 print_eth(3);
03f5c550 110#endif
c68a05fe 111#if defined(CONFIG_HAS_ETH4)
de2dff6f 112 print_eth(4);
c68a05fe 113#endif
c68a05fe 114#if defined(CONFIG_HAS_ETH5)
de2dff6f 115 print_eth(5);
c68a05fe 116#endif
117
8bde7f77 118#ifdef CONFIG_HERMES
0c277ef9 119 print_mhz("ethspeed", bd->bi_ethspeed);
8bde7f77 120#endif
5902e8f7
ML
121 printf("IP addr = %pI4\n", &bd->bi_ip_addr);
122 printf("baudrate = %6ld bps\n", bd->bi_baudrate);
123 print_num("relocaddr", gd->relocaddr);
8bde7f77
WD
124 return 0;
125}
126
c99ea790 127#elif defined(CONFIG_NIOS2)
5c952cf0 128
5902e8f7 129int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5c952cf0 130{
5c952cf0
WD
131 bd_t *bd = gd->bd;
132
5902e8f7
ML
133 print_num("mem start", (ulong)bd->bi_memstart);
134 print_lnum("mem size", (u64)bd->bi_memsize);
135 print_num("flash start", (ulong)bd->bi_flashstart);
136 print_num("flash size", (ulong)bd->bi_flashsize);
137 print_num("flash offset", (ulong)bd->bi_flashoffset);
5c952cf0 138
6d0f6bcf 139#if defined(CONFIG_SYS_SRAM_BASE)
5c952cf0
WD
140 print_num ("sram start", (ulong)bd->bi_sramstart);
141 print_num ("sram size", (ulong)bd->bi_sramsize);
142#endif
143
90253178 144#if defined(CONFIG_CMD_NET)
de2dff6f 145 print_eth(0);
5902e8f7 146 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
5c952cf0
WD
147#endif
148
5902e8f7 149 printf("baudrate = %ld bps\n", bd->bi_baudrate);
5c952cf0
WD
150
151 return 0;
152}
c99ea790
RM
153
154#elif defined(CONFIG_MICROBLAZE)
cfc67116 155
5902e8f7 156int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cfc67116 157{
cfc67116 158 bd_t *bd = gd->bd;
5902e8f7
ML
159 print_num("mem start ", (ulong)bd->bi_memstart);
160 print_lnum("mem size ", (u64)bd->bi_memsize);
161 print_num("flash start ", (ulong)bd->bi_flashstart);
162 print_num("flash size ", (ulong)bd->bi_flashsize);
163 print_num("flash offset ", (ulong)bd->bi_flashoffset);
6d0f6bcf 164#if defined(CONFIG_SYS_SRAM_BASE)
5902e8f7
ML
165 print_num("sram start ", (ulong)bd->bi_sramstart);
166 print_num("sram size ", (ulong)bd->bi_sramsize);
cfc67116 167#endif
90253178 168#if defined(CONFIG_CMD_NET)
de2dff6f 169 print_eth(0);
5902e8f7 170 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
cfc67116 171#endif
5902e8f7 172 printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
cfc67116
MS
173 return 0;
174}
4a551709 175
c99ea790
RM
176#elif defined(CONFIG_SPARC)
177
54841ab5 178int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
00ab32c8
DH
179{
180 bd_t *bd = gd->bd;
00ab32c8
DH
181
182#ifdef DEBUG
183 print_num("bd address ", (ulong) bd);
184#endif
185 print_num("memstart ", bd->bi_memstart);
b57ca3e1 186 print_lnum("memsize ", bd->bi_memsize);
00ab32c8 187 print_num("flashstart ", bd->bi_flashstart);
6d0f6bcf 188 print_num("CONFIG_SYS_MONITOR_BASE ", CONFIG_SYS_MONITOR_BASE);
0e8d1586 189 print_num("CONFIG_ENV_ADDR ", CONFIG_ENV_ADDR);
6d0f6bcf
JCPV
190 printf("CONFIG_SYS_RELOC_MONITOR_BASE = 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
191 CONFIG_SYS_MONITOR_LEN);
192 printf("CONFIG_SYS_MALLOC_BASE = 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE,
193 CONFIG_SYS_MALLOC_LEN);
194 printf("CONFIG_SYS_INIT_SP_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
195 CONFIG_SYS_STACK_SIZE);
196 printf("CONFIG_SYS_PROM_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
197 CONFIG_SYS_PROM_SIZE);
198 printf("CONFIG_SYS_GBL_DATA_OFFSET = 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
25ddd1fb 199 GENERATED_GBL_DATA_SIZE);
00ab32c8
DH
200
201#if defined(CONFIG_CMD_NET)
de2dff6f 202 print_eth(0);
b6446b67 203 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
00ab32c8 204#endif
b6446b67 205 printf("baudrate = %6ld bps\n", bd->bi_baudrate);
00ab32c8
DH
206 return 0;
207}
208
c99ea790
RM
209#elif defined(CONFIG_M68K)
210
0c277ef9 211static void print_mhz(const char *, unsigned long);
8e585f02 212
5902e8f7 213int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8e585f02 214{
8e585f02 215 bd_t *bd = gd->bd;
8ae158cd 216
5902e8f7
ML
217 print_num("memstart", (ulong)bd->bi_memstart);
218 print_lnum("memsize", (u64)bd->bi_memsize);
219 print_num("flashstart", (ulong)bd->bi_flashstart);
220 print_num("flashsize", (ulong)bd->bi_flashsize);
221 print_num("flashoffset", (ulong)bd->bi_flashoffset);
6d0f6bcf 222#if defined(CONFIG_SYS_INIT_RAM_ADDR)
5902e8f7
ML
223 print_num("sramstart", (ulong)bd->bi_sramstart);
224 print_num("sramsize", (ulong)bd->bi_sramsize);
8e585f02 225#endif
6d0f6bcf 226#if defined(CONFIG_SYS_MBAR)
5902e8f7 227 print_num("mbar", bd->bi_mbar_base);
8e585f02 228#endif
0c277ef9
TT
229 print_mhz("cpufreq", bd->bi_intfreq);
230 print_mhz("busfreq", bd->bi_busfreq);
8ae158cd 231#ifdef CONFIG_PCI
0c277ef9 232 print_mhz("pcifreq", bd->bi_pcifreq);
8ae158cd
TL
233#endif
234#ifdef CONFIG_EXTRA_CLOCK
0c277ef9
TT
235 print_mhz("flbfreq", bd->bi_flbfreq);
236 print_mhz("inpfreq", bd->bi_inpfreq);
237 print_mhz("vcofreq", bd->bi_vcofreq);
8ae158cd 238#endif
26667b7f 239#if defined(CONFIG_CMD_NET)
de2dff6f 240 print_eth(0);
8e585f02 241#if defined(CONFIG_HAS_ETH1)
de2dff6f 242 print_eth(1);
8e585f02 243#endif
8e585f02 244#if defined(CONFIG_HAS_ETH2)
de2dff6f 245 print_eth(2);
8e585f02 246#endif
8e585f02 247#if defined(CONFIG_HAS_ETH3)
de2dff6f 248 print_eth(3);
8e585f02
TL
249#endif
250
5902e8f7 251 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
26667b7f 252#endif
5902e8f7 253 printf("baudrate = %ld bps\n", bd->bi_baudrate);
8e585f02
TL
254
255 return 0;
256}
257
8dc48d71 258#elif defined(CONFIG_BLACKFIN)
c99ea790 259
0c277ef9 260static void print_mhz(const char *, unsigned long);
8dc48d71 261
54841ab5 262int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8dc48d71 263{
8dc48d71
MF
264 bd_t *bd = gd->bd;
265
266 printf("U-Boot = %s\n", bd->bi_r_version);
267 printf("CPU = %s\n", bd->bi_cpu);
268 printf("Board = %s\n", bd->bi_board_name);
0c277ef9
TT
269 print_mhz("VCO", bd->bi_vco);
270 print_mhz("CCLK", bd->bi_cclk);
271 print_mhz("SCLK", bd->bi_sclk);
8dc48d71 272
5902e8f7
ML
273 print_num("boot_params", (ulong)bd->bi_boot_params);
274 print_num("memstart", (ulong)bd->bi_memstart);
275 print_lnum("memsize", (u64)bd->bi_memsize);
276 print_num("flashstart", (ulong)bd->bi_flashstart);
277 print_num("flashsize", (ulong)bd->bi_flashsize);
278 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8dc48d71 279
de2dff6f 280 print_eth(0);
b6446b67
MF
281 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
282 printf("baudrate = %d bps\n", bd->bi_baudrate);
8dc48d71
MF
283
284 return 0;
285}
286
c99ea790 287#elif defined(CONFIG_MIPS)
8bde7f77 288
5902e8f7 289int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 290{
8bde7f77
WD
291 bd_t *bd = gd->bd;
292
5902e8f7
ML
293 print_num("boot_params", (ulong)bd->bi_boot_params);
294 print_num("memstart", (ulong)bd->bi_memstart);
295 print_lnum("memsize", (u64)bd->bi_memsize);
296 print_num("flashstart", (ulong)bd->bi_flashstart);
297 print_num("flashsize", (ulong)bd->bi_flashsize);
298 print_num("flashoffset", (ulong)bd->bi_flashoffset);
8bde7f77 299
de2dff6f 300 print_eth(0);
5902e8f7
ML
301 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
302 printf("baudrate = %d bps\n", bd->bi_baudrate);
8bde7f77
WD
303
304 return 0;
305}
8bde7f77 306
c99ea790
RM
307#elif defined(CONFIG_AVR32)
308
5902e8f7 309int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
c99ea790
RM
310{
311 bd_t *bd = gd->bd;
312
5902e8f7
ML
313 print_num("boot_params", (ulong)bd->bi_boot_params);
314 print_num("memstart", (ulong)bd->bi_memstart);
315 print_lnum("memsize", (u64)bd->bi_memsize);
316 print_num("flashstart", (ulong)bd->bi_flashstart);
317 print_num("flashsize", (ulong)bd->bi_flashsize);
318 print_num("flashoffset", (ulong)bd->bi_flashoffset);
c99ea790
RM
319
320 print_eth(0);
5902e8f7
ML
321 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
322 printf("baudrate = %lu bps\n", bd->bi_baudrate);
c99ea790
RM
323
324 return 0;
325}
326
327#elif defined(CONFIG_ARM)
8bde7f77 328
5902e8f7 329int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
8bde7f77 330{
8bde7f77
WD
331 int i;
332 bd_t *bd = gd->bd;
333
5902e8f7
ML
334 print_num("arch_number", bd->bi_arch_number);
335 print_num("boot_params", (ulong)bd->bi_boot_params);
8bde7f77 336
5902e8f7 337 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
8bde7f77
WD
338 print_num("DRAM bank", i);
339 print_num("-> start", bd->bi_dram[i].start);
340 print_num("-> size", bd->bi_dram[i].size);
341 }
342
a41dbbd9 343#if defined(CONFIG_CMD_NET)
de2dff6f 344 print_eth(0);
5902e8f7 345 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
a41dbbd9 346#endif
5902e8f7 347 printf("baudrate = %d bps\n", bd->bi_baudrate);
e47f2db5 348#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
5902e8f7 349 print_num("TLB addr", gd->tlb_addr);
f1d2b313 350#endif
5902e8f7
ML
351 print_num("relocaddr", gd->relocaddr);
352 print_num("reloc off", gd->reloc_off);
353 print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
354 print_num("sp start ", gd->start_addr_sp);
355 print_num("FB base ", gd->fb_base);
8bde7f77
WD
356 return 0;
357}
358
ebd0d062
NI
359#elif defined(CONFIG_SH)
360
5902e8f7 361int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
ebd0d062
NI
362{
363 bd_t *bd = gd->bd;
5902e8f7
ML
364 print_num("mem start ", (ulong)bd->bi_memstart);
365 print_lnum("mem size ", (u64)bd->bi_memsize);
366 print_num("flash start ", (ulong)bd->bi_flashstart);
367 print_num("flash size ", (ulong)bd->bi_flashsize);
368 print_num("flash offset ", (ulong)bd->bi_flashoffset);
ebd0d062
NI
369
370#if defined(CONFIG_CMD_NET)
371 print_eth(0);
5902e8f7 372 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
ebd0d062 373#endif
5902e8f7 374 printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
ebd0d062
NI
375 return 0;
376}
377
a806ee6f
GR
378#elif defined(CONFIG_X86)
379
0c277ef9 380static void print_mhz(const char *, unsigned long);
a806ee6f 381
5902e8f7 382int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
a806ee6f
GR
383{
384 int i;
385 bd_t *bd = gd->bd;
a806ee6f 386
5902e8f7
ML
387 print_num("boot_params", (ulong)bd->bi_boot_params);
388 print_num("bi_memstart", bd->bi_memstart);
389 print_num("bi_memsize", bd->bi_memsize);
390 print_num("bi_flashstart", bd->bi_flashstart);
391 print_num("bi_flashsize", bd->bi_flashsize);
392 print_num("bi_flashoffset", bd->bi_flashoffset);
393 print_num("bi_sramstart", bd->bi_sramstart);
394 print_num("bi_sramsize", bd->bi_sramsize);
395 print_num("bi_bootflags", bd->bi_bootflags);
0c277ef9
TT
396 print_mhz("cpufreq", bd->bi_intfreq);
397 print_mhz("busfreq", bd->bi_busfreq);
5902e8f7
ML
398
399 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
a806ee6f
GR
400 print_num("DRAM bank", i);
401 print_num("-> start", bd->bi_dram[i].start);
402 print_num("-> size", bd->bi_dram[i].size);
403 }
404
405#if defined(CONFIG_CMD_NET)
406 print_eth(0);
5902e8f7 407 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
0c277ef9 408 print_mhz("ethspeed", bd->bi_ethspeed);
a806ee6f 409#endif
5902e8f7 410 printf("baudrate = %d bps\n", bd->bi_baudrate);
a806ee6f
GR
411
412 return 0;
413}
414
6fcc3be4
SG
415#elif defined(CONFIG_SANDBOX)
416
417int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
418{
419 int i;
420 bd_t *bd = gd->bd;
421
422 print_num("boot_params", (ulong)bd->bi_boot_params);
423
424 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
425 print_num("DRAM bank", i);
426 print_num("-> start", bd->bi_dram[i].start);
427 print_num("-> size", bd->bi_dram[i].size);
428 }
429
430#if defined(CONFIG_CMD_NET)
431 print_eth(0);
432 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
433#endif
434 print_num("FB base ", gd->fb_base);
435 return 0;
436}
437
64d61461
ML
438#elif defined(CONFIG_NDS32)
439
440int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
441{
442 int i;
443 bd_t *bd = gd->bd;
444
445 print_num("arch_number", bd->bi_arch_number);
446 print_num("boot_params", (ulong)bd->bi_boot_params);
447
448 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
449 print_num("DRAM bank", i);
450 print_num("-> start", bd->bi_dram[i].start);
451 print_num("-> size", bd->bi_dram[i].size);
452 }
453
454#if defined(CONFIG_CMD_NET)
455 print_eth(0);
456 printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
457#endif
458 printf("baudrate = %d bps\n", bd->bi_baudrate);
459
460 return 0;
461}
462
c99ea790
RM
463#else
464 #error "a case for this architecture does not exist!"
465#endif
8bde7f77
WD
466
467static void print_num(const char *name, ulong value)
468{
5902e8f7 469 printf("%-12s= 0x%08lX\n", name, value);
8bde7f77
WD
470}
471
6fcc3be4 472#ifdef HAVE_PRINT_ETH
de2dff6f
MF
473static void print_eth(int idx)
474{
475 char name[10], *val;
476 if (idx)
477 sprintf(name, "eth%iaddr", idx);
478 else
479 strcpy(name, "ethaddr");
480 val = getenv(name);
481 if (!val)
482 val = "(not set)";
483 printf("%-12s= %s\n", name, val);
484}
26e42cbd 485#endif
de2dff6f 486
6fcc3be4 487#ifdef HAVE_PRINT_LNUM
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488static void print_lnum(const char *name, u64 value)
489{
5902e8f7 490 printf("%-12s= 0x%.8llX\n", name, value);
b57ca3e1
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491}
492#endif
493
5902e8f7
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494#if defined(CONFIG_PPC) || \
495 defined(CONFIG_M68K) || \
496 defined(CONFIG_BLACKFIN) || \
497 defined(CONFIG_X86)
0c277ef9 498static void print_mhz(const char *name, unsigned long hz)
8bde7f77 499{
0c277ef9
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500 char buf[32];
501
502 printf("%-12s= %6s MHz\n", name, strmhz(buf, hz));
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503}
504#endif /* CONFIG_PPC */
505
506
507/* -------------------------------------------------------------------- */
508
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509U_BOOT_CMD(
510 bdinfo, 1, 1, do_bdinfo,
2fb2604d 511 "print Board Info structure",
a89c33db 512 ""
8bde7f77 513);
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