[J-u-boot.git] / arch / arm / lib / gic_64.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * GIC Initialization Routines.
 *
 * (C) Copyright 2013
 * David Feng <[email protected]>
 */

#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>


/*************************************************************************
 *
 * void gic_init_secure(DistributorBase);
 *
 * Initialize secure copy of GIC at EL3.
 *
 *************************************************************************/
ENTRY(gic_init_secure)
	/*
	 * Initialize Distributor
	 * x0: Distributor Base
	 */
#if defined(CONFIG_GICV3)
	mov	w9, #0x37		/* EnableGrp0 | EnableGrp1NS */
					/* EnableGrp1S | ARE_S | ARE_NS */
	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
	ldr	w9, [x0, GICD_TYPER]
	and	w10, w9, #0x1f		/* ITLinesNumber */
	cbz	w10, 1f			/* No SPIs */
	add	x11, x0, (GICD_IGROUPRn + 4)
	add	x12, x0, (GICD_IGROUPMODRn + 4)
	mov	w9, #~0
0:	str	w9, [x11], #0x4
	str	wzr, [x12], #0x4	/* Config SPIs as Group1NS */
	sub	w10, w10, #0x1
	cbnz	w10, 0b
#elif defined(CONFIG_GICV2)
	mov	w9, #0x3		/* EnableGrp0 | EnableGrp1 */
	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
	ldr	w9, [x0, GICD_TYPER]
	and	w10, w9, #0x1f		/* ITLinesNumber */
	cbz	w10, 1f			/* No SPIs */
	add	x11, x0, GICD_IGROUPRn
	mov	w9, #~0			/* Config SPIs as Grp1 */
	str	w9, [x11], #0x4
0:	str	w9, [x11], #0x4
	sub	w10, w10, #0x1
	cbnz	w10, 0b

	ldr	x1, =GICC_BASE		/* GICC_CTLR */
	mov	w0, #3			/* EnableGrp0 | EnableGrp1 */
	str	w0, [x1]

	mov	w0, #1 << 7		/* allow NS access to GICC_PMR */
	str	w0, [x1, #4]		/* GICC_PMR */
#endif
1:
	ret
ENDPROC(gic_init_secure)


/*************************************************************************
 * For Gicv2:
 * void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
 * For Gicv3:
 * void gic_init_secure_percpu(ReDistributorBase);
 *
 * Initialize secure copy of GIC at EL3.
 *
 *************************************************************************/
ENTRY(gic_init_secure_percpu)
#if defined(CONFIG_GICV3)
	/*
	 * Initialize ReDistributor
	 * x0: ReDistributor Base
	 */
	mrs	x10, mpidr_el1
	lsr	x9, x10, #32
	bfi	x10, x9, #24, #8	/* w10 is aff3:aff2:aff1:aff0 */
	mov	x9, x0
1:	ldr	x11, [x9, GICR_TYPER]
	lsr	x11, x11, #32		/* w11 is aff3:aff2:aff1:aff0 */
	cmp	w10, w11
	b.eq	2f
	add	x9, x9, #(2 << 16)
	b	1b

	/* x9: ReDistributor Base Address of Current CPU */
2:	mov	w10, #~0x2
	ldr	w11, [x9, GICR_WAKER]
	and	w11, w11, w10		/* Clear ProcessorSleep */
	str	w11, [x9, GICR_WAKER]
	dsb	st
	isb
3:	ldr	w10, [x9, GICR_WAKER]
	tbnz	w10, #2, 3b		/* Wait Children be Alive */

	add	x10, x9, #(1 << 16)	/* SGI_Base */
	mov	w11, #~0
	str	w11, [x10, GICR_IGROUPRn]
	str	wzr, [x10, GICR_IGROUPMODRn]	/* SGIs|PPIs Group1NS */
	mov	w11, #0x1		/* Enable SGI 0 */
	str	w11, [x10, GICR_ISENABLERn]

	switch_el x10, 3f, 2f, 1f
3:
	/* Initialize Cpu Interface */
	mrs	x10, ICC_SRE_EL3
	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
					/* Allow EL2 access to ICC_SRE_EL2 */
	msr	ICC_SRE_EL3, x10
	isb

	mov	x10, #0x3		/* EnableGrp1NS | EnableGrp1S */
	msr	ICC_IGRPEN1_EL3, x10
	isb

	msr	ICC_CTLR_EL3, xzr
	isb
2:
	mrs	x10, ICC_SRE_EL2
	orr	x10, x10, #0xf		/* SRE & Disable IRQ/FIQ Bypass & */
					/* Allow EL1 access to ICC_SRE_EL1 */
	msr	ICC_SRE_EL2, x10
	isb
1:
	msr	ICC_CTLR_EL1, xzr	/* NonSecure ICC_CTLR_EL1 */
	isb

	mov	x10, #0x1 << 7		/* Non-Secure access to ICC_PMR_EL1 */
	msr	ICC_PMR_EL1, x10
	isb
#elif defined(CONFIG_GICV2)
	/*
	 * Initialize SGIs and PPIs
	 * x0: Distributor Base
	 * x1: Cpu Interface Base
	 */
	mov	w9, #~0			/* Config SGIs and PPIs as Grp1 */
	str	w9, [x0, GICD_IGROUPRn]	/* GICD_IGROUPR0 */
	mov	w9, #0x1		/* Enable SGI 0 */
	str	w9, [x0, GICD_ISENABLERn]

	/* Initialize Cpu Interface */
	mov	w9, #0x1e7		/* Disable IRQ/FIQ Bypass & */
					/* Enable Ack Group1 Interrupt & */
					/* EnableGrp0 & EnableGrp1 */
	str	w9, [x1, GICC_CTLR]	/* Secure GICC_CTLR */

	mov	w9, #0x1 << 7		/* Non-Secure access to GICC_PMR */
	str	w9, [x1, GICC_PMR]
#endif
	ret
ENDPROC(gic_init_secure_percpu)


/*************************************************************************
 * For Gicv2:
 * void gic_kick_secondary_cpus(DistributorBase);
 * For Gicv3:
 * void gic_kick_secondary_cpus(void);
 *
 *************************************************************************/
ENTRY(gic_kick_secondary_cpus)
#if defined(CONFIG_GICV3)
	mov	x9, #(1 << 40)
	msr	ICC_ASGI1R_EL1, x9
	isb
#elif defined(CONFIG_GICV2)
	mov	w9, #0x8000
	movk	w9, #0x100, lsl #16
	str	w9, [x0, GICD_SGIR]
#endif
	ret
ENDPROC(gic_kick_secondary_cpus)


/*************************************************************************
 * For Gicv2:
 * void gic_wait_for_interrupt(CpuInterfaceBase);
 * For Gicv3:
 * void gic_wait_for_interrupt(void);
 *
 * Wait for SGI 0 from master.
 *
 *************************************************************************/
ENTRY(gic_wait_for_interrupt)
#if defined(CONFIG_GICV3)
	gic_wait_for_interrupt_m x9
#elif defined(CONFIG_GICV2)
	gic_wait_for_interrupt_m x0, w9
#endif
	ret
ENDPROC(gic_wait_for_interrupt)
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c71645ad DF	2	/*
	3	* GIC Initialization Routines.
	4	*
	5	* (C) Copyright 2013
	6	* David Feng <[email protected]>
c71645ad DF	7	*/
	8
	9	#include <asm-offsets.h>
	10	#include <config.h>
	11	#include <linux/linkage.h>
c71645ad	12	#include <asm/gic.h>
40f8dec5	13	#include <asm/macro.h>
c71645ad DF	14
	15
	16	/*************************************************************************
	17	*
	18	* void gic_init_secure(DistributorBase);
	19	*
	20	* Initialize secure copy of GIC at EL3.
	21	*
	22	*************************************************************************/
	23	ENTRY(gic_init_secure)
	24	/*
	25	* Initialize Distributor
	26	* x0: Distributor Base
	27	*/
	28	#if defined(CONFIG_GICV3)
	29	mov w9, #0x37 /* EnableGrp0 \| EnableGrp1NS */
	30	/* EnableGrp1S \| ARE_S \| ARE_NS */
	31	str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
	32	ldr w9, [x0, GICD_TYPER]
	33	and w10, w9, #0x1f /* ITLinesNumber */
	34	cbz w10, 1f /* No SPIs */
	35	add x11, x0, (GICD_IGROUPRn + 4)
	36	add x12, x0, (GICD_IGROUPMODRn + 4)
	37	mov w9, #~0
	38	0: str w9, [x11], #0x4
	39	str wzr, [x12], #0x4 /* Config SPIs as Group1NS */
	40	sub w10, w10, #0x1
	41	cbnz w10, 0b
	42	#elif defined(CONFIG_GICV2)
	43	mov w9, #0x3 /* EnableGrp0 \| EnableGrp1 */
	44	str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
	45	ldr w9, [x0, GICD_TYPER]
	46	and w10, w9, #0x1f /* ITLinesNumber */
	47	cbz w10, 1f /* No SPIs */
b1964c72	48	add x11, x0, GICD_IGROUPRn
c71645ad	49	mov w9, #~0 /* Config SPIs as Grp1 */
b1964c72	50	str w9, [x11], #0x4
c71645ad DF	51	0: str w9, [x11], #0x4
	52	sub w10, w10, #0x1
	53	cbnz w10, 0b
b1964c72 TR	54
	55	ldr x1, =GICC_BASE /* GICC_CTLR */
	56	mov w0, #3 /* EnableGrp0 \| EnableGrp1 */
	57	str w0, [x1]
	58
	59	mov w0, #1 << 7 /* allow NS access to GICC_PMR */
	60	str w0, [x1, #4] /* GICC_PMR */
c71645ad DF	61	#endif
	62	1:
	63	ret
	64	ENDPROC(gic_init_secure)
	65
	66
	67	/*************************************************************************
	68	* For Gicv2:
	69	* void gic_init_secure_percpu(DistributorBase, CpuInterfaceBase);
	70	* For Gicv3:
	71	* void gic_init_secure_percpu(ReDistributorBase);
	72	*
	73	* Initialize secure copy of GIC at EL3.
	74	*
	75	*************************************************************************/
	76	ENTRY(gic_init_secure_percpu)
	77	#if defined(CONFIG_GICV3)
	78	/*
	79	* Initialize ReDistributor
	80	* x0: ReDistributor Base
	81	*/
	82	mrs x10, mpidr_el1
	83	lsr x9, x10, #32
	84	bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
	85	mov x9, x0
	86	1: ldr x11, [x9, GICR_TYPER]
	87	lsr x11, x11, #32 /* w11 is aff3:aff2:aff1:aff0 */
	88	cmp w10, w11
	89	b.eq 2f
	90	add x9, x9, #(2 << 16)
	91	b 1b
	92
	93	/* x9: ReDistributor Base Address of Current CPU */
	94	2: mov w10, #~0x2
	95	ldr w11, [x9, GICR_WAKER]
	96	and w11, w11, w10 /* Clear ProcessorSleep */
	97	str w11, [x9, GICR_WAKER]
	98	dsb st
	99	isb
	100	3: ldr w10, [x9, GICR_WAKER]
	101	tbnz w10, #2, 3b /* Wait Children be Alive */
	102
	103	add x10, x9, #(1 << 16) /* SGI_Base */
	104	mov w11, #~0
	105	str w11, [x10, GICR_IGROUPRn]
	106	str wzr, [x10, GICR_IGROUPMODRn] /* SGIs\|PPIs Group1NS */
	107	mov w11, #0x1 /* Enable SGI 0 */
	108	str w11, [x10, GICR_ISENABLERn]
	109
e6149576 MS	110	switch_el x10, 3f, 2f, 1f
e6149576 MS	111	3:
c71645ad DF	112	/* Initialize Cpu Interface */
	113	mrs x10, ICC_SRE_EL3
	114	orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
	115	/* Allow EL2 access to ICC_SRE_EL2 */
	116	msr ICC_SRE_EL3, x10
	117	isb
	118
c71645ad DF	119	mov x10, #0x3 /* EnableGrp1NS \| EnableGrp1S */
	120	msr ICC_IGRPEN1_EL3, x10
	121	isb
	122
	123	msr ICC_CTLR_EL3, xzr
	124	isb
e6149576 MS	125	2:
	126	mrs x10, ICC_SRE_EL2
	127	orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
	128	/* Allow EL1 access to ICC_SRE_EL1 */
	129	msr ICC_SRE_EL2, x10
	130	isb
	131	1:
c71645ad DF	132	msr ICC_CTLR_EL1, xzr /* NonSecure ICC_CTLR_EL1 */
	133	isb
	134
	135	mov x10, #0x1 << 7 /* Non-Secure access to ICC_PMR_EL1 */
	136	msr ICC_PMR_EL1, x10
	137	isb
	138	#elif defined(CONFIG_GICV2)
	139	/*
	140	* Initialize SGIs and PPIs
	141	* x0: Distributor Base
	142	* x1: Cpu Interface Base
	143	*/
	144	mov w9, #~0 /* Config SGIs and PPIs as Grp1 */
	145	str w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
	146	mov w9, #0x1 /* Enable SGI 0 */
	147	str w9, [x0, GICD_ISENABLERn]
	148
	149	/* Initialize Cpu Interface */
	150	mov w9, #0x1e7 /* Disable IRQ/FIQ Bypass & */
	151	/* Enable Ack Group1 Interrupt & */
	152	/* EnableGrp0 & EnableGrp1 */
	153	str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
	154
	155	mov w9, #0x1 << 7 /* Non-Secure access to GICC_PMR */
	156	str w9, [x1, GICC_PMR]
	157	#endif
	158	ret
	159	ENDPROC(gic_init_secure_percpu)
	160
	161
	162	/*************************************************************************
	163	* For Gicv2:
	164	* void gic_kick_secondary_cpus(DistributorBase);
	165	* For Gicv3:
	166	* void gic_kick_secondary_cpus(void);
	167	*
	168	*************************************************************************/
	169	ENTRY(gic_kick_secondary_cpus)
	170	#if defined(CONFIG_GICV3)
	171	mov x9, #(1 << 40)
	172	msr ICC_ASGI1R_EL1, x9
	173	isb
	174	#elif defined(CONFIG_GICV2)
	175	mov w9, #0x8000
	176	movk w9, #0x100, lsl #16
	177	str w9, [x0, GICD_SGIR]
	178	#endif
	179	ret
	180	ENDPROC(gic_kick_secondary_cpus)
	181
	182
	183	/*************************************************************************
	184	* For Gicv2:
	185	* void gic_wait_for_interrupt(CpuInterfaceBase);
	186	* For Gicv3:
	187	* void gic_wait_for_interrupt(void);
	188	*
	189	* Wait for SGI 0 from master.
	190	*
	191	*************************************************************************/
	192	ENTRY(gic_wait_for_interrupt)
c71645ad	193	#if defined(CONFIG_GICV3)
40f8dec5	194	gic_wait_for_interrupt_m x9
c71645ad	195	#elif defined(CONFIG_GICV2)
40f8dec5	196	gic_wait_for_interrupt_m x0, w9
c71645ad	197	#endif
c71645ad DF	198	ret
c71645ad DF	199	ENDPROC(gic_wait_for_interrupt)