[J-u-boot.git] / drivers / mmc / pxa_mmc_gen.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2010 Marek Vasut <[email protected]>
 *
 * Loosely based on the old code and Linux's PXA MMC driver
 */

#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-mmc.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <mmc.h>

/* PXAMMC Generic default config for various CPUs */
#if defined(CONFIG_CPU_PXA25X)
#define PXAMMC_FIFO_SIZE	1
#define PXAMMC_MIN_SPEED	312500
#define PXAMMC_MAX_SPEED	20000000
#define PXAMMC_HOST_CAPS	(0)
#elif defined(CONFIG_CPU_PXA27X)
#define PXAMMC_CRC_SKIP
#define PXAMMC_FIFO_SIZE	32
#define PXAMMC_MIN_SPEED	304000
#define PXAMMC_MAX_SPEED	19500000
#define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT)
#elif defined(CONFIG_CPU_MONAHANS)
#define PXAMMC_FIFO_SIZE	32
#define PXAMMC_MIN_SPEED	304000
#define PXAMMC_MAX_SPEED	26000000
#define PXAMMC_HOST_CAPS	(MMC_MODE_4BIT | MMC_MODE_HS)
#else
#error "This CPU isn't supported by PXA MMC!"
#endif

#define MMC_STAT_ERRORS							\
	(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN |	\
	MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE |		\
	MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)

/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
#define PXA_MMC_TIMEOUT	100

struct pxa_mmc_priv {
	struct pxa_mmc_regs *regs;
};

/* Wait for bit to be set */
static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	unsigned int timeout = PXA_MMC_TIMEOUT;

	/* Wait for bit to be set */
	while (--timeout) {
		if (readl(&regs->stat) & mask)
			break;
		udelay(10);
	}

	if (!timeout)
		return -ETIMEDOUT;

	return 0;
}

static int pxa_mmc_stop_clock(struct mmc *mmc)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	unsigned int timeout = PXA_MMC_TIMEOUT;

	/* If the clock aren't running, exit */
	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
		return 0;

	/* Tell the controller to turn off the clock */
	writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);

	/* Wait until the clock are off */
	while (--timeout) {
		if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
			break;
		udelay(10);
	}

	/* The clock refused to stop, scream and die a painful death */
	if (!timeout)
		return -ETIMEDOUT;

	/* The clock stopped correctly */
	return 0;
}

static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
				uint32_t cmdat)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	int ret;

	/* The card can send a "busy" response */
	if (cmd->resp_type & MMC_RSP_BUSY)
		cmdat |= MMC_CMDAT_BUSY;

	/* Inform the controller about response type */
	switch (cmd->resp_type) {
	case MMC_RSP_R1:
	case MMC_RSP_R1b:
		cmdat |= MMC_CMDAT_R1;
		break;
	case MMC_RSP_R2:
		cmdat |= MMC_CMDAT_R2;
		break;
	case MMC_RSP_R3:
		cmdat |= MMC_CMDAT_R3;
		break;
	default:
		break;
	}

	/* Load command and it's arguments into the controller */
	writel(cmd->cmdidx, &regs->cmd);
	writel(cmd->cmdarg >> 16, &regs->argh);
	writel(cmd->cmdarg & 0xffff, &regs->argl);
	writel(cmdat, &regs->cmdat);

	/* Start the controller clock and wait until they are started */
	writel(MMC_STRPCL_START_CLK, &regs->strpcl);

	ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
	if (ret)
		return ret;

	/* Correct and happy end */
	return 0;
}

static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	uint32_t a, b, c;
	int i;
	int stat;

	/* Read the controller status */
	stat = readl(&regs->stat);

	/*
	 * Linux says:
	 * Did I mention this is Sick.  We always need to
	 * discard the upper 8 bits of the first 16-bit word.
	 */
	a = readl(&regs->res) & 0xffff;
	for (i = 0; i < 4; i++) {
		b = readl(&regs->res) & 0xffff;
		c = readl(&regs->res) & 0xffff;
		cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
		a = c;
	}

	/* The command response didn't arrive */
	if (stat & MMC_STAT_TIME_OUT_RESPONSE)
		return -ETIMEDOUT;
	else if (stat & MMC_STAT_RES_CRC_ERROR
			&& cmd->resp_type & MMC_RSP_CRC) {
#ifdef	PXAMMC_CRC_SKIP
		if (cmd->resp_type & MMC_RSP_136
				&& cmd->response[0] & (1 << 31))
			printf("Ignoring CRC, this may be dangerous!\n");
		else
#endif
		return -EILSEQ;
	}

	/* The command response was successfully read */
	return 0;
}

static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	uint32_t len;
	uint32_t *buf = (uint32_t *)data->dest;
	int size;
	int ret;

	len = data->blocks * data->blocksize;

	while (len) {
		/* The controller has data ready */
		if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
			len -= size;
			size /= 4;

			/* Read data into the buffer */
			while (size--)
				*buf++ = readl(&regs->rxfifo);

		}

		if (readl(&regs->stat) & MMC_STAT_ERRORS)
			return -EIO;
	}

	/* Wait for the transmission-done interrupt */
	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
	if (ret)
		return ret;

	return 0;
}

static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	uint32_t len;
	uint32_t *buf = (uint32_t *)data->src;
	int size;
	int ret;

	len = data->blocks * data->blocksize;

	while (len) {
		/* The controller is ready to receive data */
		if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
			size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
			len -= size;
			size /= 4;

			while (size--)
				writel(*buf++, &regs->txfifo);

			if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
				writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
		}

		if (readl(&regs->stat) & MMC_STAT_ERRORS)
			return -EIO;
	}

	/* Wait for the transmission-done interrupt */
	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
	if (ret)
		return ret;

	/* Wait until the data are really written to the card */
	ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
	if (ret)
		return ret;

	return 0;
}

static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
				struct mmc_data *data)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	uint32_t cmdat = 0;
	int ret;

	/* Stop the controller */
	ret = pxa_mmc_stop_clock(mmc);
	if (ret)
		return ret;

	/* If we're doing data transfer, configure the controller accordingly */
	if (data) {
		writel(data->blocks, &regs->nob);
		writel(data->blocksize, &regs->blklen);
		/* This delay can be optimized, but stick with max value */
		writel(0xffff, &regs->rdto);
		cmdat |= MMC_CMDAT_DATA_EN;
		if (data->flags & MMC_DATA_WRITE)
			cmdat |= MMC_CMDAT_WRITE;
	}

	/* Run in 4bit mode if the card can do it */
	if (mmc->bus_width == 4)
		cmdat |= MMC_CMDAT_SD_4DAT;

	/* Execute the command */
	ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
	if (ret)
		return ret;

	/* Wait until the command completes */
	ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
	if (ret)
		return ret;

	/* Read back the result */
	ret = pxa_mmc_cmd_done(mmc, cmd);
	if (ret)
		return ret;

	/* In case there was a data transfer scheduled, do it */
	if (data) {
		if (data->flags & MMC_DATA_WRITE)
			pxa_mmc_do_write_xfer(mmc, data);
		else
			pxa_mmc_do_read_xfer(mmc, data);
	}

	return 0;
}

static int pxa_mmc_set_ios(struct mmc *mmc)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;
	uint32_t tmp;
	uint32_t pxa_mmc_clock;

	if (!mmc->clock) {
		pxa_mmc_stop_clock(mmc);
		return 0;
	}

	/* PXA3xx can do 26MHz with special settings. */
	if (mmc->clock == 26000000) {
		writel(0x7, &regs->clkrt);
		return 0;
	}

	/* Set clock to the card the usual way. */
	pxa_mmc_clock = 0;
	tmp = mmc->cfg->f_max / mmc->clock;
	tmp += tmp % 2;

	while (tmp > 1) {
		pxa_mmc_clock++;
		tmp >>= 1;
	}

	writel(pxa_mmc_clock, &regs->clkrt);

	return 0;
}

static int pxa_mmc_init(struct mmc *mmc)
{
	struct pxa_mmc_priv *priv = mmc->priv;
	struct pxa_mmc_regs *regs = priv->regs;

	/* Make sure the clock are stopped */
	pxa_mmc_stop_clock(mmc);

	/* Turn off SPI mode */
	writel(0, &regs->spi);

	/* Set up maximum timeout to wait for command response */
	writel(MMC_RES_TO_MAX_MASK, &regs->resto);

	/* Mask all interrupts */
	writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
		&regs->i_mask);
	return 0;
}

static const struct mmc_ops pxa_mmc_ops = {
	.send_cmd	= pxa_mmc_request,
	.set_ios	= pxa_mmc_set_ios,
	.init		= pxa_mmc_init,
};

static struct mmc_config pxa_mmc_cfg = {
	.name		= "PXA MMC",
	.ops		= &pxa_mmc_ops,
	.voltages	= MMC_VDD_32_33 | MMC_VDD_33_34,
	.f_max		= PXAMMC_MAX_SPEED,
	.f_min		= PXAMMC_MIN_SPEED,
	.host_caps	= PXAMMC_HOST_CAPS,
	.b_max		= CONFIG_SYS_MMC_MAX_BLK_COUNT,
};

int pxa_mmc_register(int card_index)
{
	struct mmc *mmc;
	struct pxa_mmc_priv *priv;
	uint32_t reg;
	int ret = -ENOMEM;

	priv = malloc(sizeof(struct pxa_mmc_priv));
	if (!priv)
		goto err0;

	memset(priv, 0, sizeof(*priv));

	switch (card_index) {
	case 0:
		priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
		break;
	case 1:
		priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
		break;
	default:
		ret = -EINVAL;
		printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
			card_index);
		goto err1;
	}

#ifndef	CONFIG_CPU_MONAHANS	/* PXA2xx */
	reg = readl(CKEN);
	reg |= CKEN12_MMC;
	writel(reg, CKEN);
#else				/* PXA3xx */
	reg = readl(CKENA);
	reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
	writel(reg, CKENA);
#endif

	mmc = mmc_create(&pxa_mmc_cfg, priv);
	if (mmc == NULL)
		goto err1;

	return 0;

err1:
	free(priv);
err0:
	return ret;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
07133f2e MV	2	/*
	3	* Copyright (C) 2010 Marek Vasut <[email protected]>
	4	*
	5	* Loosely based on the old code and Linux's PXA MMC driver
07133f2e MV	6	*/
07133f2e MV	7
07133f2e	8	#include <common.h>
07133f2e MV	9	#include <asm/arch/hardware.h>
07133f2e MV	10	#include <asm/arch/regs-mmc.h>
1221ce45	11	#include <linux/errno.h>
07133f2e	12	#include <asm/io.h>
54a5cf81 MZ	13	#include <malloc.h>
54a5cf81 MZ	14	#include <mmc.h>
07133f2e MV	15
07133f2e MV	16	/* PXAMMC Generic default config for various CPUs */
abc20aba	17	#if defined(CONFIG_CPU_PXA25X)
07133f2e MV	18	#define PXAMMC_FIFO_SIZE 1
	19	#define PXAMMC_MIN_SPEED 312500
	20	#define PXAMMC_MAX_SPEED 20000000
	21	#define PXAMMC_HOST_CAPS (0)
abc20aba	22	#elif defined(CONFIG_CPU_PXA27X)
07133f2e MV	23	#define PXAMMC_CRC_SKIP
	24	#define PXAMMC_FIFO_SIZE 32
	25	#define PXAMMC_MIN_SPEED 304000
	26	#define PXAMMC_MAX_SPEED 19500000
	27	#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
	28	#elif defined(CONFIG_CPU_MONAHANS)
	29	#define PXAMMC_FIFO_SIZE 32
	30	#define PXAMMC_MIN_SPEED 304000
	31	#define PXAMMC_MAX_SPEED 26000000
	32	#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT \| MMC_MODE_HS)
	33	#else
	34	#error "This CPU isn't supported by PXA MMC!"
	35	#endif
	36
	37	#define MMC_STAT_ERRORS \
	38	(MMC_STAT_RES_CRC_ERROR \| MMC_STAT_SPI_READ_ERROR_TOKEN \| \
	39	MMC_STAT_CRC_READ_ERROR \| MMC_STAT_TIME_OUT_RESPONSE \| \
	40	MMC_STAT_READ_TIME_OUT \| MMC_STAT_CRC_WRITE_ERROR)
	41
	42	/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
	43	#define PXA_MMC_TIMEOUT 100
	44
	45	struct pxa_mmc_priv {
	46	struct pxa_mmc_regs *regs;
	47	};
	48
	49	/* Wait for bit to be set */
	50	static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
	51	{
93bfd616	52	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	53	struct pxa_mmc_regs *regs = priv->regs;
	54	unsigned int timeout = PXA_MMC_TIMEOUT;
	55
	56	/* Wait for bit to be set */
	57	while (--timeout) {
	58	if (readl(&regs->stat) & mask)
	59	break;
	60	udelay(10);
	61	}
	62
	63	if (!timeout)
	64	return -ETIMEDOUT;
	65
	66	return 0;
	67	}
	68
	69	static int pxa_mmc_stop_clock(struct mmc *mmc)
	70	{
93bfd616	71	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	72	struct pxa_mmc_regs *regs = priv->regs;
	73	unsigned int timeout = PXA_MMC_TIMEOUT;
	74
	75	/* If the clock aren't running, exit */
	76	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
	77	return 0;
	78
	79	/* Tell the controller to turn off the clock */
	80	writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
	81
	82	/* Wait until the clock are off */
	83	while (--timeout) {
	84	if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
	85	break;
	86	udelay(10);
	87	}
	88
	89	/* The clock refused to stop, scream and die a painful death */
	90	if (!timeout)
	91	return -ETIMEDOUT;
	92
	93	/* The clock stopped correctly */
	94	return 0;
	95	}
	96
	97	static int pxa_mmc_start_cmd(struct mmc mmc, struct mmc_cmd cmd,
	98	uint32_t cmdat)
	99	{
93bfd616	100	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	101	struct pxa_mmc_regs *regs = priv->regs;
	102	int ret;
	103
	104	/* The card can send a "busy" response */
95b01c47	105	if (cmd->resp_type & MMC_RSP_BUSY)
07133f2e MV	106	cmdat \|= MMC_CMDAT_BUSY;
	107
	108	/* Inform the controller about response type */
	109	switch (cmd->resp_type) {
	110	case MMC_RSP_R1:
	111	case MMC_RSP_R1b:
	112	cmdat \|= MMC_CMDAT_R1;
	113	break;
	114	case MMC_RSP_R2:
	115	cmdat \|= MMC_CMDAT_R2;
	116	break;
	117	case MMC_RSP_R3:
	118	cmdat \|= MMC_CMDAT_R3;
	119	break;
	120	default:
	121	break;
	122	}
	123
	124	/* Load command and it's arguments into the controller */
	125	writel(cmd->cmdidx, &regs->cmd);
	126	writel(cmd->cmdarg >> 16, &regs->argh);
	127	writel(cmd->cmdarg & 0xffff, &regs->argl);
	128	writel(cmdat, &regs->cmdat);
	129
	130	/* Start the controller clock and wait until they are started */
	131	writel(MMC_STRPCL_START_CLK, &regs->strpcl);
	132
	133	ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
	134	if (ret)
	135	return ret;
	136
	137	/* Correct and happy end */
	138	return 0;
	139	}
	140
	141	static int pxa_mmc_cmd_done(struct mmc mmc, struct mmc_cmd cmd)
	142	{
93bfd616	143	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	144	struct pxa_mmc_regs *regs = priv->regs;
	145	uint32_t a, b, c;
	146	int i;
	147	int stat;
	148
	149	/* Read the controller status */
	150	stat = readl(&regs->stat);
	151
	152	/*
	153	* Linux says:
	154	* Did I mention this is Sick. We always need to
	155	* discard the upper 8 bits of the first 16-bit word.
	156	*/
	157	a = readl(&regs->res) & 0xffff;
	158	for (i = 0; i < 4; i++) {
	159	b = readl(&regs->res) & 0xffff;
	160	c = readl(&regs->res) & 0xffff;
	161	cmd->response[i] = (a << 24) \| (b << 8) \| (c >> 8);
	162	a = c;
	163	}
	164
	165	/* The command response didn't arrive */
	166	if (stat & MMC_STAT_TIME_OUT_RESPONSE)
	167	return -ETIMEDOUT;
95b01c47 AF	168	else if (stat & MMC_STAT_RES_CRC_ERROR
95b01c47 AF	169	&& cmd->resp_type & MMC_RSP_CRC) {
07133f2e	170	#ifdef PXAMMC_CRC_SKIP
95b01c47 AF	171	if (cmd->resp_type & MMC_RSP_136
95b01c47 AF	172	&& cmd->response[0] & (1 << 31))
07133f2e MV	173	printf("Ignoring CRC, this may be dangerous!\n");
	174	else
	175	#endif
	176	return -EILSEQ;
	177	}
	178
	179	/* The command response was successfully read */
	180	return 0;
	181	}
	182
	183	static int pxa_mmc_do_read_xfer(struct mmc mmc, struct mmc_data data)
	184	{
93bfd616	185	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	186	struct pxa_mmc_regs *regs = priv->regs;
	187	uint32_t len;
	188	uint32_t buf = (uint32_t )data->dest;
	189	int size;
	190	int ret;
	191
	192	len = data->blocks * data->blocksize;
	193
	194	while (len) {
	195	/* The controller has data ready */
	196	if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
b4141195	197	size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
07133f2e MV	198	len -= size;
	199	size /= 4;
	200
	201	/* Read data into the buffer */
	202	while (size--)
	203	*buf++ = readl(&regs->rxfifo);
	204
	205	}
	206
	207	if (readl(&regs->stat) & MMC_STAT_ERRORS)
	208	return -EIO;
	209	}
	210
	211	/* Wait for the transmission-done interrupt */
	212	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
	213	if (ret)
	214	return ret;
	215
	216	return 0;
	217	}
	218
	219	static int pxa_mmc_do_write_xfer(struct mmc mmc, struct mmc_data data)
	220	{
93bfd616	221	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	222	struct pxa_mmc_regs *regs = priv->regs;
	223	uint32_t len;
	224	uint32_t buf = (uint32_t )data->src;
	225	int size;
	226	int ret;
	227
	228	len = data->blocks * data->blocksize;
	229
	230	while (len) {
	231	/* The controller is ready to receive data */
	232	if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
b4141195	233	size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
07133f2e MV	234	len -= size;
	235	size /= 4;
	236
	237	while (size--)
	238	writel(*buf++, &regs->txfifo);
	239
b4141195	240	if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
07133f2e MV	241	writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
	242	}
	243
	244	if (readl(&regs->stat) & MMC_STAT_ERRORS)
	245	return -EIO;
	246	}
	247
	248	/* Wait for the transmission-done interrupt */
	249	ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
	250	if (ret)
	251	return ret;
	252
	253	/* Wait until the data are really written to the card */
	254	ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
	255	if (ret)
	256	return ret;
	257
	258	return 0;
	259	}
	260
	261	static int pxa_mmc_request(struct mmc mmc, struct mmc_cmd cmd,
	262	struct mmc_data *data)
	263	{
93bfd616	264	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	265	struct pxa_mmc_regs *regs = priv->regs;
	266	uint32_t cmdat = 0;
	267	int ret;
	268
	269	/* Stop the controller */
	270	ret = pxa_mmc_stop_clock(mmc);
	271	if (ret)
	272	return ret;
	273
	274	/* If we're doing data transfer, configure the controller accordingly */
	275	if (data) {
	276	writel(data->blocks, &regs->nob);
	277	writel(data->blocksize, &regs->blklen);
	278	/* This delay can be optimized, but stick with max value */
	279	writel(0xffff, &regs->rdto);
	280	cmdat \|= MMC_CMDAT_DATA_EN;
	281	if (data->flags & MMC_DATA_WRITE)
	282	cmdat \|= MMC_CMDAT_WRITE;
	283	}
	284
	285	/* Run in 4bit mode if the card can do it */
	286	if (mmc->bus_width == 4)
	287	cmdat \|= MMC_CMDAT_SD_4DAT;
	288
	289	/* Execute the command */
	290	ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
	291	if (ret)
	292	return ret;
	293
	294	/* Wait until the command completes */
	295	ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
	296	if (ret)
	297	return ret;
	298
	299	/* Read back the result */
	300	ret = pxa_mmc_cmd_done(mmc, cmd);
	301	if (ret)
	302	return ret;
	303
	304	/* In case there was a data transfer scheduled, do it */
	305	if (data) {
	306	if (data->flags & MMC_DATA_WRITE)
	307	pxa_mmc_do_write_xfer(mmc, data);
	308	else
	309	pxa_mmc_do_read_xfer(mmc, data);
	310	}
	311
	312	return 0;
	313	}
	314
07b0b9c0	315	static int pxa_mmc_set_ios(struct mmc *mmc)
07133f2e	316	{
93bfd616	317	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	318	struct pxa_mmc_regs *regs = priv->regs;
	319	uint32_t tmp;
	320	uint32_t pxa_mmc_clock;
	321
	322	if (!mmc->clock) {
	323	pxa_mmc_stop_clock(mmc);
07b0b9c0	324	return 0;
07133f2e MV	325	}
	326
	327	/* PXA3xx can do 26MHz with special settings. */
	328	if (mmc->clock == 26000000) {
	329	writel(0x7, &regs->clkrt);
07b0b9c0	330	return 0;
07133f2e MV	331	}
	332
	333	/* Set clock to the card the usual way. */
	334	pxa_mmc_clock = 0;
93bfd616	335	tmp = mmc->cfg->f_max / mmc->clock;
07133f2e MV	336	tmp += tmp % 2;
	337
	338	while (tmp > 1) {
	339	pxa_mmc_clock++;
	340	tmp >>= 1;
	341	}
	342
	343	writel(pxa_mmc_clock, &regs->clkrt);
07b0b9c0 JC	344
07b0b9c0 JC	345	return 0;
07133f2e MV	346	}
	347
	348	static int pxa_mmc_init(struct mmc *mmc)
	349	{
93bfd616	350	struct pxa_mmc_priv *priv = mmc->priv;
07133f2e MV	351	struct pxa_mmc_regs *regs = priv->regs;
	352
	353	/* Make sure the clock are stopped */
	354	pxa_mmc_stop_clock(mmc);
	355
	356	/* Turn off SPI mode */
	357	writel(0, &regs->spi);
	358
	359	/* Set up maximum timeout to wait for command response */
	360	writel(MMC_RES_TO_MAX_MASK, &regs->resto);
	361
	362	/* Mask all interrupts */
	363	writel(~(MMC_I_MASK_TXFIFO_WR_REQ \| MMC_I_MASK_RXFIFO_RD_REQ),
	364	&regs->i_mask);
	365	return 0;
	366	}
	367
ab769f22 PA	368	static const struct mmc_ops pxa_mmc_ops = {
	369	.send_cmd = pxa_mmc_request,
	370	.set_ios = pxa_mmc_set_ios,
	371	.init = pxa_mmc_init,
	372	};
	373
93bfd616 PA	374	static struct mmc_config pxa_mmc_cfg = {
	375	.name = "PXA MMC",
	376	.ops = &pxa_mmc_ops,
	377	.voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
	378	.f_max = PXAMMC_MAX_SPEED,
	379	.f_min = PXAMMC_MIN_SPEED,
	380	.host_caps = PXAMMC_HOST_CAPS,
	381	.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
	382	};
	383
07133f2e MV	384	int pxa_mmc_register(int card_index)
	385	{
	386	struct mmc *mmc;
	387	struct pxa_mmc_priv *priv;
	388	uint32_t reg;
	389	int ret = -ENOMEM;
	390
07133f2e MV	391	priv = malloc(sizeof(struct pxa_mmc_priv));
07133f2e MV	392	if (!priv)
93bfd616 PA	393	goto err0;
	394
	395	memset(priv, 0, sizeof(*priv));
07133f2e MV	396
	397	switch (card_index) {
	398	case 0:
	399	priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
	400	break;
	401	case 1:
	402	priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
	403	break;
	404	default:
93bfd616	405	ret = -EINVAL;
07133f2e MV	406	printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
07133f2e MV	407	card_index);
93bfd616	408	goto err1;
07133f2e MV	409	}
07133f2e MV	410
07133f2e MV	411	#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
	412	reg = readl(CKEN);
	413	reg \|= CKEN12_MMC;
	414	writel(reg, CKEN);
	415	#else /* PXA3xx */
	416	reg = readl(CKENA);
	417	reg \|= CKENA_12_MMC0 \| CKENA_13_MMC1;
	418	writel(reg, CKENA);
	419	#endif
	420
93bfd616 PA	421	mmc = mmc_create(&pxa_mmc_cfg, priv);
	422	if (mmc == NULL)
	423	goto err1;
07133f2e MV	424
	425	return 0;
	426
07133f2e	427	err1:
93bfd616	428	free(priv);
07133f2e MV	429	err0:
	430	return ret;
	431	}