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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * Copyright (C) 2015 Atmel Corporation
4 * Wenyou.Yang <[email protected]>
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5 */
6
7#include <common.h>
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8#include <clk.h>
9#include <dm.h>
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10#include <malloc.h>
11#include <sdhci.h>
12#include <asm/arch/clk.h>
13
14#define ATMEL_SDHC_MIN_FREQ 400000
327713a6 15#define ATMEL_SDHC_GCK_RATE 240000000
a3b59b15 16
a0d0d86f 17#ifndef CONFIG_DM_MMC
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18int atmel_sdhci_init(void *regbase, u32 id)
19{
20 struct sdhci_host *host;
21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
22
23 host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
24 if (!host) {
25 printf("%s: sdhci_host calloc failed\n", __func__);
26 return -ENOMEM;
27 }
28
29 host->name = "atmel_sdhci";
30 host->ioaddr = regbase;
b3125088 31 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
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32 max_clk = at91_get_periph_generated_clk(id);
33 if (!max_clk) {
34 printf("%s: Failed to get the proper clock\n", __func__);
35 free(host);
36 return -ENODEV;
37 }
6d0e34bf 38 host->max_clk = max_clk;
a3b59b15 39
6d0e34bf 40 add_sdhci(host, 0, min_clk);
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41
42 return 0;
43}
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44
45#else
46
47DECLARE_GLOBAL_DATA_PTR;
48
49struct atmel_sdhci_plat {
50 struct mmc_config cfg;
51 struct mmc mmc;
52};
53
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54static int atmel_sdhci_probe(struct udevice *dev)
55{
56 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
57 struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
58 struct sdhci_host *host = dev_get_priv(dev);
59 u32 max_clk;
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60 struct clk clk;
61 int ret;
62
339cb073 63 ret = clk_get_by_index(dev, 0, &clk);
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64 if (ret)
65 return ret;
66
67 ret = clk_enable(&clk);
68 if (ret)
69 return ret;
70
71 host->name = dev->name;
a821c4af 72 host->ioaddr = (void *)devfdt_get_addr(dev);
a0d0d86f 73
b3125088 74 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
e160f7d4 75 host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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76 "bus-width", 4);
77
339cb073 78 ret = clk_get_by_index(dev, 1, &clk);
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79 if (ret)
80 return ret;
81
327713a6 82 ret = clk_set_rate(&clk, ATMEL_SDHC_GCK_RATE);
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83 if (ret)
84 return ret;
85
86 max_clk = clk_get_rate(&clk);
87 if (!max_clk)
88 return -EINVAL;
89
6d0e34bf 90 host->max_clk = max_clk;
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91 host->mmc = &plat->mmc;
92 host->mmc->dev = dev;
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93
94 ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
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95 if (ret)
96 return ret;
97
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98 host->mmc->priv = host;
99 upriv->mmc = host->mmc;
100
101 clk_free(&clk);
102
103 return sdhci_probe(dev);
104}
105
106static int atmel_sdhci_bind(struct udevice *dev)
107{
108 struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
a0d0d86f 109
24f5aec3 110 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
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111}
112
113static const struct udevice_id atmel_sdhci_ids[] = {
114 { .compatible = "atmel,sama5d2-sdhci" },
f5663740 115 { .compatible = "microchip,sam9x60-sdhci" },
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116 { }
117};
118
119U_BOOT_DRIVER(atmel_sdhci_drv) = {
120 .name = "atmel_sdhci",
121 .id = UCLASS_MMC,
122 .of_match = atmel_sdhci_ids,
123 .ops = &sdhci_ops,
124 .bind = atmel_sdhci_bind,
125 .probe = atmel_sdhci_probe,
126 .priv_auto_alloc_size = sizeof(struct sdhci_host),
127 .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
128};
129#endif
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