[J-u-boot.git] / board / gdsys / p1022 / controlcenterd.c

/*
 * (C) Copyright 2013
 * Dirk Eibach,  Guntermann & Drunck GmbH, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <env.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
#include <i2c.h>
#include <pca9698.h>
#include <watchdog.h>
#include "../common/dp501.h"
#include "controlcenterd-id.h"

enum {
	HWVER_100 = 0,
	HWVER_110 = 1,
	HWVER_120 = 2,
};

struct ihs_fpga {
	u32 reflection_low;	/* 0x0000 */
	u32 versions;		/* 0x0004 */
	u32 fpga_version;	/* 0x0008 */
	u32 fpga_features;	/* 0x000c */
	u32 reserved[4];	/* 0x0010 */
	u32 control;		/* 0x0020 */
};

#ifndef CONFIG_TRAILBLAZER
static struct pci_device_id hydra_supported[] = {
	{ 0x6d5e, 0xcdc0 },
	{}
};

static void hydra_initialize(void);
#endif

int board_early_init_f(void)
{
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);

	/* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
	clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);

	/* Set pmuxcr to allow both i2c1 and i2c2 */
	setbits_be32(&gur->pmuxcr, 0x00001000);

	/* Set pmuxcr to enable GPIO 3_11-3_13 */
	setbits_be32(&gur->pmuxcr, 0x00000010);

	/* Set pmuxcr to enable GPIO 2_31,3_9+10 */
	setbits_be32(&gur->pmuxcr, 0x00000020);

	/* Set pmuxcr to enable GPIO 2_28-2_30 */
	setbits_be32(&gur->pmuxcr, 0x000000c0);

	/* Set pmuxcr to enable GPIO 3_20-3_22 */
	setbits_be32(&gur->pmuxcr2, 0x03000000);

	/* Set pmuxcr to enable IRQ0-2 */
	clrbits_be32(&gur->pmuxcr, 0x00000300);

	/* Set pmuxcr to disable IRQ3-11 */
	setbits_be32(&gur->pmuxcr, 0x000000F0);

	/* Read back the register to synchronize the write. */
	in_be32(&gur->pmuxcr);

	/* Set the pin muxing to enable ETSEC2. */
	clrbits_be32(&gur->pmuxcr2, 0x001F8000);

#ifdef CONFIG_TRAILBLAZER
	/*
	 * GPIO3_10 SPERRTRIGGER
	 */
	setbits_be32(&pgpio->gpdir, 0x00200000);
	clrbits_be32(&pgpio->gpdat, 0x00200000);
	udelay(100);
	setbits_be32(&pgpio->gpdat, 0x00200000);
	udelay(100);
	clrbits_be32(&pgpio->gpdat, 0x00200000);
#endif

	/*
	 * GPIO3_11 CPU-TO-FPGA-RESET#
	 */
	setbits_be32(&pgpio->gpdir, 0x00100000);
	clrbits_be32(&pgpio->gpdat, 0x00100000);

	/*
	 * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
	 */
	setbits_be32(&pgpio->gpdir, 0x00000400);

	return 0;
}

int checkboard(void)
{
	printf("Board: ControlCenter DIGITAL\n");

	return 0;
}

int misc_init_r(void)
{
	return 0;
}

/*
 * A list of PCI and SATA slots
 */
enum slot_id {
	SLOT_PCIE1 = 1,
	SLOT_PCIE2,
	SLOT_PCIE3,
	SLOT_PCIE4,
	SLOT_PCIE5,
	SLOT_SATA1,
	SLOT_SATA2
};

/*
 * This array maps the slot identifiers to their names on the P1022DS board.
 */
static const char * const slot_names[] = {
	[SLOT_PCIE1] = "Slot 1",
	[SLOT_PCIE2] = "Slot 2",
	[SLOT_PCIE3] = "Slot 3",
	[SLOT_PCIE4] = "Slot 4",
	[SLOT_PCIE5] = "Mini-PCIe",
	[SLOT_SATA1] = "SATA 1",
	[SLOT_SATA2] = "SATA 2",
};

/*
 * This array maps a given SERDES configuration and SERDES device to the PCI or
 * SATA slot that it connects to.  This mapping is hard-coded in the FPGA.
 */
static u8 serdes_dev_slot[][SATA2 + 1] = {
	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
		   [PCIE2] = SLOT_PCIE5 },
	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
		   [PCIE2] = SLOT_PCIE3,
		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
		   [PCIE2] = SLOT_PCIE3 },
	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
		   [PCIE2] = SLOT_PCIE3,
		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
	[0x1c] = { [PCIE1] = SLOT_PCIE1,
		   [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
};


/*
 * Returns the name of the slot to which the PCIe or SATA controller is
 * connected
 */
const char *board_serdes_name(enum srds_prtcl device)
{
	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
	u32 pordevsr = in_be32(&gur->pordevsr);
	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;
	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
	const char *name = slot_names[slot];

	if (name)
		return name;
	else
		return "Nothing";
}

void hw_watchdog_reset(void)
{
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);

	clrbits_be32(&pgpio->gpdat, 0x00000400);
	setbits_be32(&pgpio->gpdat, 0x00000400);
}

#ifdef CONFIG_TRAILBLAZER
int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	return run_command(env_get("bootcmd"), flag);
}

int board_early_init_r(void)
{
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);

	/*
	 * GPIO3_12 PPC_SYSTEMREADY#
	 */
	setbits_be32(&pgpio->gpdir, 0x00080000);
	setbits_be32(&pgpio->gpodr, 0x00080000);
	clrbits_be32(&pgpio->gpdat, 0x00080000);

	return ccdm_compute_self_hash();
}

int last_stage_init(void)
{
	startup_ccdm_id_module();
	return 0;
}

#else
void pci_init_board(void)
{
	fsl_pcie_init_board(0);

	hydra_initialize();
}

int board_early_init_r(void)
{
	unsigned int k = 0;
	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);

	/* wait for FPGA configuration to finish */
	while (!pca9698_get_value(0x22, 11) && (k++ < 30))
		udelay(100000);

	if (k > 30) {
		puts("FPGA configuration timed out.\n");
	} else {
		/* clear FPGA reset */
		udelay(1000);
		setbits_be32(&pgpio->gpdat, 0x00100000);
	}

	/* give time for PCIe link training */
	udelay(100000);

	/*
	 * GPIO3_12 PPC_SYSTEMREADY#
	 */
	setbits_be32(&pgpio->gpdir, 0x00080000);
	setbits_be32(&pgpio->gpodr, 0x00080000);
	clrbits_be32(&pgpio->gpdat, 0x00080000);

	return 0;
}

int last_stage_init(void)
{
	/* Turn on Parade DP501 */
	pca9698_direction_output(0x22, 7, 1);
	udelay(500000);

	dp501_powerup(0x08);

	startup_ccdm_id_module();

	return 0;
}

/*
 * Initialize on-board and/or PCI Ethernet devices
 *
 * Returns:
 *      <0, error
 *       0, no ethernet devices found
 *      >0, number of ethernet devices initialized
 */
int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[2];
	unsigned int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;
#endif
#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;
	fsl_pq_mdio_init(bis, &mdio_info);

	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = env_get_bootm_low();
	size = env_get_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_HAS_FSL_DR_USB
	fsl_fdt_fixup_dr_usb(blob, bd);
#endif

	FT_FSL_PCI_SETUP;

	return 0;
}
#endif

static void hydra_initialize(void)
{
	unsigned int i;
	pci_dev_t devno;

	/* Find and probe all the matching PCI devices */
	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
		u32 val;
		struct ihs_fpga *fpga;
		u32 versions;
		u32 fpga_version;
		u32 fpga_features;

		unsigned hardware_version;
		unsigned feature_uart_channels;
		unsigned feature_sb_channels;

		/* Try to enable I/O accesses and bus-mastering */
		val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
		pci_write_config_dword(devno, PCI_COMMAND, val);

		/* Make sure it worked */
		pci_read_config_dword(devno, PCI_COMMAND, &val);
		if (!(val & PCI_COMMAND_MEMORY)) {
			puts("Can't enable I/O memory\n");
			continue;
		}
		if (!(val & PCI_COMMAND_MASTER)) {
			puts("Can't enable bus-mastering\n");
			continue;
		}

		/* read FPGA details */
		fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
			PCI_REGION_MEM);

		/* disable sideband clocks */
		writel(1, &fpga->control);

		versions = readl(&fpga->versions);
		fpga_version = readl(&fpga->fpga_version);
		fpga_features = readl(&fpga->fpga_features);

		hardware_version = versions & 0xf;
		feature_uart_channels = (fpga_features >> 6) & 0x1f;
		feature_sb_channels = fpga_features & 0x1f;

		printf("FPGA%d: ", i);

		switch (hardware_version) {
		case HWVER_100:
			printf("HW-Ver 1.00\n");
			break;

		case HWVER_110:
			printf("HW-Ver 1.10\n");
			break;

		case HWVER_120:
			printf("HW-Ver 1.20\n");
			break;

		default:
			printf("HW-Ver %d(not supported)\n",
			       hardware_version);
			break;
		}

		printf("       FPGA V %d.%02d, features:",
		       fpga_version / 100, fpga_version % 100);

		printf(" %d uart channel(s)", feature_uart_channels);
		printf(" %d sideband channel(s)\n", feature_sb_channels);
	}
}
#endif
Commit	Line	Data
b9944a77 DE	1	/*
	2	* (C) Copyright 2013
	3	* Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
7b51b576	26	#include <env.h>
4d72caa5	27	#include <image.h>
5255932f	28	#include <init.h>
90526e9f	29	#include <net.h>
b9944a77 DE	30	#include <pci.h>
	31	#include <asm/processor.h>
	32	#include <asm/mmu.h>
	33	#include <asm/cache.h>
	34	#include <asm/immap_85xx.h>
	35	#include <asm/fsl_pci.h>
5614e71b	36	#include <fsl_ddr_sdram.h>
b9944a77 DE	37	#include <asm/fsl_serdes.h>
b9944a77 DE	38	#include <asm/io.h>
b08c8c48	39	#include <linux/libfdt.h>
b9944a77 DE	40	#include <fdt_support.h>
	41	#include <fsl_mdio.h>
	42	#include <tsec.h>
	43	#include <asm/fsl_law.h>
	44	#include <netdev.h>
	45	#include <i2c.h>
	46	#include <pca9698.h>
	47	#include <watchdog.h>
	48	#include "../common/dp501.h"
	49	#include "controlcenterd-id.h"
	50
b9944a77 DE	51	enum {
	52	HWVER_100 = 0,
	53	HWVER_110 = 1,
	54	HWVER_120 = 2,
	55	};
	56
	57	struct ihs_fpga {
	58	u32 reflection_low; /* 0x0000 */
	59	u32 versions; /* 0x0004 */
	60	u32 fpga_version; /* 0x0008 */
	61	u32 fpga_features; /* 0x000c */
1c7639ae DE	62	u32 reserved[4]; /* 0x0010 */
1c7639ae DE	63	u32 control; /* 0x0020 */
b9944a77 DE	64	};
	65
	66	#ifndef CONFIG_TRAILBLAZER
	67	static struct pci_device_id hydra_supported[] = {
	68	{ 0x6d5e, 0xcdc0 },
	69	{}
	70	};
	71
	72	static void hydra_initialize(void);
	73	#endif
	74
	75	int board_early_init_f(void)
	76	{
	77	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	78	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
	79
	80	/* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
	81	clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
	82
	83	/* Set pmuxcr to allow both i2c1 and i2c2 */
	84	setbits_be32(&gur->pmuxcr, 0x00001000);
	85
	86	/* Set pmuxcr to enable GPIO 3_11-3_13 */
	87	setbits_be32(&gur->pmuxcr, 0x00000010);
	88
	89	/* Set pmuxcr to enable GPIO 2_31,3_9+10 */
	90	setbits_be32(&gur->pmuxcr, 0x00000020);
	91
	92	/* Set pmuxcr to enable GPIO 2_28-2_30 */
	93	setbits_be32(&gur->pmuxcr, 0x000000c0);
	94
	95	/* Set pmuxcr to enable GPIO 3_20-3_22 */
	96	setbits_be32(&gur->pmuxcr2, 0x03000000);
	97
	98	/* Set pmuxcr to enable IRQ0-2 */
	99	clrbits_be32(&gur->pmuxcr, 0x00000300);
	100
	101	/* Set pmuxcr to disable IRQ3-11 */
	102	setbits_be32(&gur->pmuxcr, 0x000000F0);
	103
	104	/* Read back the register to synchronize the write. */
	105	in_be32(&gur->pmuxcr);
	106
	107	/* Set the pin muxing to enable ETSEC2. */
	108	clrbits_be32(&gur->pmuxcr2, 0x001F8000);
	109
	110	#ifdef CONFIG_TRAILBLAZER
	111	/*
	112	* GPIO3_10 SPERRTRIGGER
	113	*/
	114	setbits_be32(&pgpio->gpdir, 0x00200000);
	115	clrbits_be32(&pgpio->gpdat, 0x00200000);
	116	udelay(100);
	117	setbits_be32(&pgpio->gpdat, 0x00200000);
	118	udelay(100);
	119	clrbits_be32(&pgpio->gpdat, 0x00200000);
	120	#endif
	121
	122	/*
	123	* GPIO3_11 CPU-TO-FPGA-RESET#
	124	*/
	125	setbits_be32(&pgpio->gpdir, 0x00100000);
	126	clrbits_be32(&pgpio->gpdat, 0x00100000);
	127
128	/*
129	* GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
130	*/
131	setbits_be32(&pgpio->gpdir, 0x00000400);
132
133	return 0;
134	}
135
136	int checkboard(void)
137	{
138	printf("Board: ControlCenter DIGITAL\n");
139
140	return 0;
141	}
142
143	int misc_init_r(void)
144	{
145	return 0;
146	}
147
148	/*
149	* A list of PCI and SATA slots
150	*/
151	enum slot_id {
152	SLOT_PCIE1 = 1,
153	SLOT_PCIE2,
154	SLOT_PCIE3,
155	SLOT_PCIE4,
156	SLOT_PCIE5,
157	SLOT_SATA1,
158	SLOT_SATA2
159	};
160
161	/*
162	* This array maps the slot identifiers to their names on the P1022DS board.
163	*/
164	static const char * const slot_names[] = {
165	[SLOT_PCIE1] = "Slot 1",
166	[SLOT_PCIE2] = "Slot 2",
167	[SLOT_PCIE3] = "Slot 3",
168	[SLOT_PCIE4] = "Slot 4",
169	[SLOT_PCIE5] = "Mini-PCIe",
170	[SLOT_SATA1] = "SATA 1",
171	[SLOT_SATA2] = "SATA 2",
172	};
173
174	/*
175	* This array maps a given SERDES configuration and SERDES device to the PCI or
176	* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
177	*/
178	static u8 serdes_dev_slot[][SATA2 + 1] = {
179	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
180	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
181	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
182	[PCIE2] = SLOT_PCIE5 },
183	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
184	[PCIE2] = SLOT_PCIE3,
185	[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
186	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
187	[PCIE2] = SLOT_PCIE3 },
188	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
189	[PCIE2] = SLOT_PCIE3,
190	[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
191	[0x1c] = { [PCIE1] = SLOT_PCIE1,
192	[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
193	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
194	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
195	};
196
197
198	/*
199	* Returns the name of the slot to which the PCIe or SATA controller is
200	* connected
201	*/
202	const char *board_serdes_name(enum srds_prtcl device)
203	{
204	ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
205	u32 pordevsr = in_be32(&gur->pordevsr);
206	unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
207	MPC85xx_PORDEVSR_IO_SEL_SHIFT;
208	enum slot_id slot = serdes_dev_slot[srds_cfg][device];
209	const char *name = slot_names[slot];
210
211	if (name)
212	return name;
213	else
214	return "Nothing";
215	}
216
217	void hw_watchdog_reset(void)
218	{
219	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
220
221	clrbits_be32(&pgpio->gpdat, 0x00000400);
222	setbits_be32(&pgpio->gpdat, 0x00000400);
223	}
224
225	#ifdef CONFIG_TRAILBLAZER
09140113	226	int do_bootd(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
b9944a77	227	{
00caae6d	228	return run_command(env_get("bootcmd"), flag);
b9944a77 DE	229	}
	230
	231	int board_early_init_r(void)
	232	{
	233	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
	234
	235	/*
	236	* GPIO3_12 PPC_SYSTEMREADY#
	237	*/
	238	setbits_be32(&pgpio->gpdir, 0x00080000);
	239	setbits_be32(&pgpio->gpodr, 0x00080000);
	240	clrbits_be32(&pgpio->gpdat, 0x00080000);
	241
	242	return ccdm_compute_self_hash();
	243	}
	244
	245	int last_stage_init(void)
	246	{
	247	startup_ccdm_id_module();
	248	return 0;
	249	}
	250
	251	#else
	252	void pci_init_board(void)
	253	{
	254	fsl_pcie_init_board(0);
	255
	256	hydra_initialize();
	257	}
	258
	259	int board_early_init_r(void)
	260	{
	261	unsigned int k = 0;
	262	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
	263
	264	/* wait for FPGA configuration to finish */
	265	while (!pca9698_get_value(0x22, 11) && (k++ < 30))
	266	udelay(100000);
	267
	268	if (k > 30) {
	269	puts("FPGA configuration timed out.\n");
	270	} else {
	271	/* clear FPGA reset */
	272	udelay(1000);
	273	setbits_be32(&pgpio->gpdat, 0x00100000);
	274	}
	275
	276	/* give time for PCIe link training */
	277	udelay(100000);
	278
	279	/*
	280	* GPIO3_12 PPC_SYSTEMREADY#
	281	*/
	282	setbits_be32(&pgpio->gpdir, 0x00080000);
	283	setbits_be32(&pgpio->gpodr, 0x00080000);
	284	clrbits_be32(&pgpio->gpdat, 0x00080000);
	285
	286	return 0;
	287	}
	288
	289	int last_stage_init(void)
	290	{
	291	/* Turn on Parade DP501 */
	292	pca9698_direction_output(0x22, 7, 1);
293	udelay(500000);
294
295	dp501_powerup(0x08);
296
297	startup_ccdm_id_module();
298
299	return 0;
300	}
301
302	/*
303	* Initialize on-board and/or PCI Ethernet devices
304	*
305	* Returns:
306	* <0, error
307	* 0, no ethernet devices found
308	* >0, number of ethernet devices initialized
309	*/
310	int board_eth_init(bd_t *bis)
311	{
312	struct fsl_pq_mdio_info mdio_info;
313	struct tsec_info_struct tsec_info[2];
314	unsigned int num = 0;
315
316	#ifdef CONFIG_TSEC1
317	SET_STD_TSEC_INFO(tsec_info[num], 1);
318	num++;
319	#endif
320	#ifdef CONFIG_TSEC2
321	SET_STD_TSEC_INFO(tsec_info[num], 2);
322	num++;
323	#endif
324
325	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
326	mdio_info.name = DEFAULT_MII_NAME;
327	fsl_pq_mdio_init(bis, &mdio_info);
328
329	return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
330	}
331
332	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	333	int ft_board_setup(void blob, bd_t bd)
b9944a77 DE	334	{
	335	phys_addr_t base;
	336	phys_size_t size;
	337
	338	ft_cpu_setup(blob, bd);
	339
723806cc SG	340	base = env_get_bootm_low();
723806cc SG	341	size = env_get_bootm_size();
b9944a77 DE	342
	343	fdt_fixup_memory(blob, (u64)base, (u64)size);
	344
	345	#ifdef CONFIG_HAS_FSL_DR_USB
a5c289b9	346	fsl_fdt_fixup_dr_usb(blob, bd);
b9944a77 DE	347	#endif
	348
	349	FT_FSL_PCI_SETUP;
e895a4b0 SG	350
e895a4b0 SG	351	return 0;
b9944a77 DE	352	}
	353	#endif
	354
	355	static void hydra_initialize(void)
	356	{
	357	unsigned int i;
	358	pci_dev_t devno;
	359
	360	/* Find and probe all the matching PCI devices */
	361	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
	362	u32 val;
	363	struct ihs_fpga *fpga;
	364	u32 versions;
	365	u32 fpga_version;
	366	u32 fpga_features;
	367
	368	unsigned hardware_version;
	369	unsigned feature_uart_channels;
	370	unsigned feature_sb_channels;
	371
	372	/* Try to enable I/O accesses and bus-mastering */
	373	val = PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER;
	374	pci_write_config_dword(devno, PCI_COMMAND, val);
	375
	376	/* Make sure it worked */
	377	pci_read_config_dword(devno, PCI_COMMAND, &val);
	378	if (!(val & PCI_COMMAND_MEMORY)) {
	379	puts("Can't enable I/O memory\n");
	380	continue;
	381	}
	382	if (!(val & PCI_COMMAND_MASTER)) {
	383	puts("Can't enable bus-mastering\n");
	384	continue;
	385	}
	386
	387	/* read FPGA details */
	388	fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
	389	PCI_REGION_MEM);
	390
1c7639ae DE	391	/* disable sideband clocks */
	392	writel(1, &fpga->control);
	393
c2b951b0 DE	394	versions = readl(&fpga->versions);
	395	fpga_version = readl(&fpga->fpga_version);
	396	fpga_features = readl(&fpga->fpga_features);
b9944a77 DE	397
	398	hardware_version = versions & 0xf;
	399	feature_uart_channels = (fpga_features >> 6) & 0x1f;
	400	feature_sb_channels = fpga_features & 0x1f;
	401
	402	printf("FPGA%d: ", i);
	403
	404	switch (hardware_version) {
	405	case HWVER_100:
	406	printf("HW-Ver 1.00\n");
	407	break;
	408
	409	case HWVER_110:
	410	printf("HW-Ver 1.10\n");
	411	break;
	412
	413	case HWVER_120:
	414	printf("HW-Ver 1.20\n");
	415	break;
	416
	417	default:
	418	printf("HW-Ver %d(not supported)\n",
	419	hardware_version);
	420	break;
	421	}
	422
	423	printf(" FPGA V %d.%02d, features:",
	424	fpga_version / 100, fpga_version % 100);
	425
	426	printf(" %d uart channel(s)", feature_uart_channels);
	427	printf(" %d sideband channel(s)\n", feature_sb_channels);
	428	}
	429	}
	430	#endif