[J-u-boot.git] / board / gdsys / common / cmd_ioloop.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014
 * Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
 */

#include <common.h>
#include <command.h>
#include <console.h>

#include <gdsys_fpga.h>

#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
#include <dm.h>
#include <misc.h>
#include <regmap.h>
#include <board.h>

#include "../../../drivers/misc/gdsys_soc.h"
#include "../../../drivers/misc/gdsys_ioep.h"
#include "../../../drivers/misc/ihs_fpga.h"

const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */

enum status_print_type {
	STATUS_LOUD = 0,
	STATUS_SILENT = 1,
};

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
enum {
	STATE_TX_PACKET_BUILDING = BIT(0),
	STATE_TX_TRANSMITTING = BIT(1),
	STATE_TX_BUFFER_FULL = BIT(2),
	STATE_TX_ERR = BIT(3),
	STATE_RECEIVE_TIMEOUT = BIT(4),
	STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
	STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
	STATE_RX_DIST_ERR = BIT(7),
	STATE_RX_LENGTH_ERR = BIT(8),
	STATE_RX_FRAME_CTR_ERR = BIT(9),
	STATE_RX_FCS_ERR = BIT(10),
	STATE_RX_PACKET_DROPPED = BIT(11),
	STATE_RX_DATA_LAST = BIT(12),
	STATE_RX_DATA_FIRST = BIT(13),
	STATE_RX_DATA_AVAILABLE = BIT(15),
};

enum {
	IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
	IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
	IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
	IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
};

enum {
	CTRL_PROC_RECEIVE_ENABLE = BIT(12),
	CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
};

struct io_generic_packet {
	u16 target_address;
	u16 source_address;
	u8 packet_type;
	u8 bc;
	u16 packet_length;
} __attribute__((__packed__));
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

unsigned long long rx_ctr;
unsigned long long tx_ctr;
unsigned long long err_ctr;
#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
struct udevice *dev;
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_check_status(uint fpga, u16 status, enum status_print_type type)
{
	u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR |
		   STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR |
		   STATE_RX_PACKET_DROPPED | STATE_TX_ERR;

	if (!(status & mask)) {
		FPGA_SET_REG(fpga, ep.rx_tx_status, status);
		return;
	}

	err_ctr++;
	FPGA_SET_REG(fpga, ep.rx_tx_status, status);

	if (type == STATUS_SILENT)
		return;

	if (status & STATE_RX_PACKET_DROPPED)
		printf("RX_PACKET_DROPPED, status %04x\n", status);

	if (status & STATE_RX_DIST_ERR)
		printf("RX_DIST_ERR\n");
	if (status & STATE_RX_LENGTH_ERR)
		printf("RX_LENGTH_ERR\n");
	if (status & STATE_RX_FRAME_CTR_ERR)
		printf("RX_FRAME_CTR_ERR\n");
	if (status & STATE_RX_FCS_ERR)
		printf("RX_FCS_ERR\n");

	if (status & STATE_TX_ERR)
		printf("TX_ERR\n");
}
#else
static void io_check_status(struct udevice *dev, enum status_print_type type)
{
	u16 status = 0;
	int ret;

	ret = misc_call(dev, 0, NULL, 0, &status, 0);
	if (!ret)
		return;

	err_ctr++;

	if (type != STATUS_LOUD)
		return;

	if (status & STATE_RX_PACKET_DROPPED)
		printf("RX_PACKET_DROPPED, status %04x\n", status);

	if (status & STATE_RX_DIST_ERR)
		printf("RX_DIST_ERR\n");
	if (status & STATE_RX_LENGTH_ERR)
		printf("RX_LENGTH_ERR\n");
	if (status & STATE_RX_FRAME_CTR_ERR)
		printf("RX_FRAME_CTR_ERR\n");
	if (status & STATE_RX_FCS_ERR)
		printf("RX_FCS_ERR\n");

	if (status & STATE_TX_ERR)
		printf("TX_ERR\n");
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_send(uint fpga, uint size)
{
	uint k;
	struct io_generic_packet packet = {
		.source_address = 1,
		.packet_type = 1,
		.packet_length = size,
	};
	u16 *p = (u16 *)&packet;

	for (k = 0; k < sizeof(packet) / 2; ++k)
		FPGA_SET_REG(fpga, ep.transmit_data, *p++);

	for (k = 0; k < (size + 1) / 2; ++k)
		FPGA_SET_REG(fpga, ep.transmit_data, k);

	FPGA_SET_REG(fpga, ep.rx_tx_control,
		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);

	tx_ctr++;
}
#else
static void io_send(struct udevice *dev, uint size)
{
	uint k;
	u16 buffer[HEADER_WORDS + 128];
	struct io_generic_packet header = {
		.source_address = 1,
		.packet_type = 1,
		.packet_length = size,
	};
	const uint words = (size + 1) / 2;

	memcpy(buffer, &header, 2 * HEADER_WORDS);
	for (k = 0; k < words; ++k)
		buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);

	misc_write(dev, 0, buffer, HEADER_WORDS + words);

	tx_ctr++;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_receive(uint fpga)
{
	u16 rx_tx_status;

	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
		u16 rx;

		if (rx_tx_status & STATE_RX_DATA_LAST)
			rx_ctr++;

		FPGA_GET_REG(fpga, ep.receive_data, &rx);

		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	}
}
#else
static void io_receive(struct udevice *dev)
{
	u16 buffer[HEADER_WORDS + 128];

	if (!misc_read(dev, 0, buffer, 0))
		rx_ctr++;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
static void io_reflect(uint fpga)
{
	u16 buffer[128];

	uint k = 0;
	uint n;
	u16 rx_tx_status;

	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
		FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
		if (rx_tx_status & STATE_RX_DATA_LAST)
			break;

		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	}

	if (!k)
		return;

	for (n = 0; n < k; ++n)
		FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);

	FPGA_SET_REG(fpga, ep.rx_tx_control,
		     CTRL_PROC_RECEIVE_ENABLE | CTRL_FLUSH_TRANSMIT_BUFFER);

	tx_ctr++;
}
#else
static void io_reflect(struct udevice *dev)
{
	u16 buffer[HEADER_WORDS + 128];
	struct io_generic_packet *header;

	if (misc_read(dev, 0, buffer, 0))
		return;

	header = (struct io_generic_packet *)&buffer;

	misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
 * FPGA io-endpoint reflector
 *
 * Syntax:
 *	ioreflect {fpga} {reportrate}
 */
int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	uint fpga;
	uint rate = 0;
	unsigned long long last_seen = 0;

	if (argc < 2)
		return CMD_RET_USAGE;

	fpga = simple_strtoul(argv[1], NULL, 10);

	/*
	 * If another parameter, it is the report rate in packets.
	 */
	if (argc > 2)
		rate = simple_strtoul(argv[2], NULL, 10);

	/* Enable receive path */
	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);

	/* Set device address to dummy 1*/
	FPGA_SET_REG(fpga, ep.device_address, 1);

	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;

	while (1) {
		u16 top_int;
		u16 rx_tx_status;

		FPGA_GET_REG(fpga, top_interrupt, &top_int);
		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

		io_check_status(fpga, rx_tx_status, STATUS_SILENT);
		if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
		    (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
			io_reflect(fpga);

		if (rate) {
			if (!(tx_ctr % rate) && (tx_ctr != last_seen))
				printf("refl %llu, err %llu\n", tx_ctr,
				       err_ctr);
			last_seen = tx_ctr;
		}

		if (ctrlc())
			break;
	}

	return 0;
}
#else
/*
 * FPGA io-endpoint reflector
 *
 * Syntax:
 *	ioreflect {reportrate}
 */
int do_ioreflect(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	struct udevice *fpga;
	struct regmap *map;
	uint rate = 0;
	unsigned long long last_seen = 0;

	if (!dev) {
		printf("No device selected\n");
		return 1;
	}

	gdsys_soc_get_fpga(dev, &fpga);
	regmap_init_mem(dev_ofnode(dev), &map);

	/* Enable receive path */
	misc_set_enabled(dev, true);

	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;

	while (1) {
		uint top_int;

		ihs_fpga_get(map, top_interrupt, &top_int);
		io_check_status(dev, STATUS_SILENT);
		if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
		    (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
			io_reflect(dev);

		if (rate) {
			if (!(tx_ctr % rate) && (tx_ctr != last_seen))
				printf("refl %llu, err %llu\n", tx_ctr,
				       err_ctr);
			last_seen = tx_ctr;
		}

		if (ctrlc())
			break;
	}

	return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#define DISP_LINE_LEN	16

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
/*
 * FPGA io-endpoint looptest
 *
 * Syntax:
 *	ioloop {fpga} {size} {rate}
 */
int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	uint fpga;
	uint size;
	uint rate = 0;

	if (argc < 3)
		return CMD_RET_USAGE;

	/*
	 * FPGA is specified since argc > 2
	 */
	fpga = simple_strtoul(argv[1], NULL, 10);

	/*
	 * packet size is specified since argc > 2
	 */
	size = simple_strtoul(argv[2], NULL, 10);

	/*
	 * If another parameter, it is the test rate in packets per second.
	 */
	if (argc > 3)
		rate = simple_strtoul(argv[3], NULL, 10);

	/* enable receive path */
	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);

	/* set device address to dummy 1*/
	FPGA_SET_REG(fpga, ep.device_address, 1);

	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;

	while (1) {
		u16 top_int;
		u16 rx_tx_status;

		FPGA_GET_REG(fpga, top_interrupt, &top_int);
		FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

		io_check_status(fpga, rx_tx_status, STATUS_LOUD);
		if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
			io_send(fpga, size);
		if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
			io_receive(fpga);

		if (rate) {
			if (ctrlc())
				break;
			udelay(1000000 / rate);
			if (!(tx_ctr % rate))
				printf("d %llu, tx %llu, rx %llu, err %llu\n",
				       tx_ctr - rx_ctr, tx_ctr, rx_ctr,
				       err_ctr);
		}
	}

	return 0;
}
#else
/*
 * FPGA io-endpoint looptest
 *
 * Syntax:
 *	ioloop {size} {rate}
 */
int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	uint size;
	uint rate = 0;
	struct udevice *fpga;
	struct regmap *map;

	if (!dev) {
		printf("No device selected\n");
		return 1;
	}

	gdsys_soc_get_fpga(dev, &fpga);
	regmap_init_mem(dev_ofnode(dev), &map);

	if (argc < 2)
		return CMD_RET_USAGE;

	/*
	 * packet size is specified since argc > 1
	 */
	size = simple_strtoul(argv[2], NULL, 10);

	/*
	 * If another parameter, it is the test rate in packets per second.
	 */
	if (argc > 2)
		rate = simple_strtoul(argv[3], NULL, 10);

	/* Enable receive path */
	misc_set_enabled(dev, true);

	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;

	while (1) {
		uint top_int;

		if (ctrlc())
			break;

		ihs_fpga_get(map, top_interrupt, &top_int);

		io_check_status(dev, STATUS_LOUD);
		if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
			io_send(dev, size);
		if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
			io_receive(dev);

		if (rate) {
			udelay(1000000 / rate);
			if (!(tx_ctr % rate))
				printf("d %llu, tx %llu, rx %llu, err %llu\n",
				       tx_ctr - rx_ctr, tx_ctr, rx_ctr,
				       err_ctr);
		}
	}
	return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	struct udevice *ioep = NULL;
	struct udevice *board;
	char name[8];
	int ret;

	if (board_get(&board))
		return CMD_RET_FAILURE;

	if (argc > 1) {
		int i = simple_strtoul(argv[1], NULL, 10);

		snprintf(name, sizeof(name), "ioep%d", i);

		ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);

		if (ret || !ioep) {
			printf("Invalid IOEP %d\n", i);
			return CMD_RET_FAILURE;
		}

		dev = ioep;
	} else {
		int i = 0;

		while (1) {
			snprintf(name, sizeof(name), "ioep%d", i);

			ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);

			if (ret || !ioep)
				break;

			printf("IOEP %d:\t%s\n", i++, ioep->name);
		}

		if (dev)
			printf("\nSelected IOEP: %s\n", dev->name);
		else
			puts("\nNo IOEP selected.\n");
	}

	return 0;
}
#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
U_BOOT_CMD(
	ioloop,	4,	0,	do_ioloop,
	"fpga io-endpoint looptest",
	"fpga packetsize [packets/sec]"
);

U_BOOT_CMD(
	ioreflect, 3,	0,	do_ioreflect,
	"fpga io-endpoint reflector",
	"fpga reportrate"
);
#else
U_BOOT_CMD(
	ioloop,	3,	0,	do_ioloop,
	"fpga io-endpoint looptest",
	"packetsize [packets/sec]"
);

U_BOOT_CMD(
	ioreflect, 2,	0,	do_ioreflect,
	"fpga io-endpoint reflector",
	"reportrate"
);

U_BOOT_CMD(
	iodev, 2,	0,	do_iodev,
	"fpga io-endpoint listing/selection",
	"[ioep device to select]"
);
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
50dcf89d DE	2	/*
	3	* (C) Copyright 2014
	4	* Dirk Eibach, Guntermann & Drunck GmbH, [email protected]
50dcf89d DE	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
24b852a7	9	#include <console.h>
50dcf89d DE	10
	11	#include <gdsys_fpga.h>
	12
df8e5fb3 MS	13	#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
	14	#include <dm.h>
	15	#include <misc.h>
	16	#include <regmap.h>
	17	#include <board.h>
	18
	19	#include "../../../drivers/misc/gdsys_soc.h"
	20	#include "../../../drivers/misc/gdsys_ioep.h"
	21	#include "../../../drivers/misc/ihs_fpga.h"
	22
	23	const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2;
	24	#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
	25
ba75772f MS	26	enum status_print_type {
	27	STATUS_LOUD = 0,
	28	STATUS_SILENT = 1,
	29	};
	30
df8e5fb3	31	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
50dcf89d	32	enum {
db1d03a2 MS	33	STATE_TX_PACKET_BUILDING = BIT(0),
	34	STATE_TX_TRANSMITTING = BIT(1),
	35	STATE_TX_BUFFER_FULL = BIT(2),
	36	STATE_TX_ERR = BIT(3),
	37	STATE_RECEIVE_TIMEOUT = BIT(4),
	38	STATE_PROC_RX_STORE_TIMEOUT = BIT(5),
	39	STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6),
	40	STATE_RX_DIST_ERR = BIT(7),
	41	STATE_RX_LENGTH_ERR = BIT(8),
	42	STATE_RX_FRAME_CTR_ERR = BIT(9),
	43	STATE_RX_FCS_ERR = BIT(10),
	44	STATE_RX_PACKET_DROPPED = BIT(11),
	45	STATE_RX_DATA_LAST = BIT(12),
	46	STATE_RX_DATA_FIRST = BIT(13),
	47	STATE_RX_DATA_AVAILABLE = BIT(15),
50dcf89d DE	48	};
50dcf89d DE	49
50dcf89d	50	enum {
db1d03a2 MS	51	IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5),
	52	IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6),
	53	IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7),
	54	IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8),
50dcf89d DE	55	};
50dcf89d DE	56
df8e5fb3 MS	57	enum {
	58	CTRL_PROC_RECEIVE_ENABLE = BIT(12),
	59	CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15),
	60	};
	61
50dcf89d DE	62	struct io_generic_packet {
	63	u16 target_address;
	64	u16 source_address;
	65	u8 packet_type;
	66	u8 bc;
	67	u16 packet_length;
	68	} __attribute__((__packed__));
df8e5fb3	69	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
50dcf89d DE	70
	71	unsigned long long rx_ctr;
	72	unsigned long long tx_ctr;
	73	unsigned long long err_ctr;
df8e5fb3 MS	74	#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
	75	struct udevice *dev;
	76	#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
50dcf89d	77
df8e5fb3	78	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
ba75772f	79	static void io_check_status(uint fpga, u16 status, enum status_print_type type)
50dcf89d DE	80	{
	81	u16 mask = STATE_RX_DIST_ERR \| STATE_RX_LENGTH_ERR \|
	82	STATE_RX_FRAME_CTR_ERR \| STATE_RX_FCS_ERR \|
	83	STATE_RX_PACKET_DROPPED \| STATE_TX_ERR;
	84
	85	if (!(status & mask)) {
	86	FPGA_SET_REG(fpga, ep.rx_tx_status, status);
	87	return;
	88	}
	89
	90	err_ctr++;
	91	FPGA_SET_REG(fpga, ep.rx_tx_status, status);
	92
ba75772f	93	if (type == STATUS_SILENT)
50dcf89d DE	94	return;
	95
	96	if (status & STATE_RX_PACKET_DROPPED)
	97	printf("RX_PACKET_DROPPED, status %04x\n", status);
	98
	99	if (status & STATE_RX_DIST_ERR)
	100	printf("RX_DIST_ERR\n");
	101	if (status & STATE_RX_LENGTH_ERR)
	102	printf("RX_LENGTH_ERR\n");
	103	if (status & STATE_RX_FRAME_CTR_ERR)
	104	printf("RX_FRAME_CTR_ERR\n");
	105	if (status & STATE_RX_FCS_ERR)
	106	printf("RX_FCS_ERR\n");
	107
	108	if (status & STATE_TX_ERR)
	109	printf("TX_ERR\n");
	110	}
df8e5fb3 MS	111	#else
	112	static void io_check_status(struct udevice *dev, enum status_print_type type)
	113	{
	114	u16 status = 0;
	115	int ret;
50dcf89d	116
df8e5fb3 MS	117	ret = misc_call(dev, 0, NULL, 0, &status, 0);
	118	if (!ret)
	119	return;
	120
	121	err_ctr++;
	122
	123	if (type != STATUS_LOUD)
	124	return;
	125
	126	if (status & STATE_RX_PACKET_DROPPED)
	127	printf("RX_PACKET_DROPPED, status %04x\n", status);
	128
	129	if (status & STATE_RX_DIST_ERR)
	130	printf("RX_DIST_ERR\n");
	131	if (status & STATE_RX_LENGTH_ERR)
	132	printf("RX_LENGTH_ERR\n");
	133	if (status & STATE_RX_FRAME_CTR_ERR)
	134	printf("RX_FRAME_CTR_ERR\n");
	135	if (status & STATE_RX_FCS_ERR)
	136	printf("RX_FCS_ERR\n");
	137
	138	if (status & STATE_TX_ERR)
	139	printf("TX_ERR\n");
	140	}
	141	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
	142
	143	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
db1d03a2	144	static void io_send(uint fpga, uint size)
50dcf89d	145	{
db1d03a2	146	uint k;
50dcf89d DE	147	struct io_generic_packet packet = {
	148	.source_address = 1,
	149	.packet_type = 1,
	150	.packet_length = size,
	151	};
	152	u16 p = (u16 )&packet;
	153
	154	for (k = 0; k < sizeof(packet) / 2; ++k)
	155	FPGA_SET_REG(fpga, ep.transmit_data, *p++);
	156
	157	for (k = 0; k < (size + 1) / 2; ++k)
	158	FPGA_SET_REG(fpga, ep.transmit_data, k);
	159
	160	FPGA_SET_REG(fpga, ep.rx_tx_control,
	161	CTRL_PROC_RECEIVE_ENABLE \| CTRL_FLUSH_TRANSMIT_BUFFER);
	162
	163	tx_ctr++;
	164	}
df8e5fb3 MS	165	#else
	166	static void io_send(struct udevice *dev, uint size)
	167	{
	168	uint k;
	169	u16 buffer[HEADER_WORDS + 128];
	170	struct io_generic_packet header = {
	171	.source_address = 1,
	172	.packet_type = 1,
	173	.packet_length = size,
	174	};
	175	const uint words = (size + 1) / 2;
	176
	177	memcpy(buffer, &header, 2 * HEADER_WORDS);
	178	for (k = 0; k < words; ++k)
	179	buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);
50dcf89d	180
df8e5fb3 MS	181	misc_write(dev, 0, buffer, HEADER_WORDS + words);
	182
	183	tx_ctr++;
	184	}
	185	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
	186
	187	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
db1d03a2	188	static void io_receive(uint fpga)
50dcf89d	189	{
50dcf89d DE	190	u16 rx_tx_status;
	191
	192	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	193
	194	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
	195	u16 rx;
	196
	197	if (rx_tx_status & STATE_RX_DATA_LAST)
	198	rx_ctr++;
	199
	200	FPGA_GET_REG(fpga, ep.receive_data, &rx);
	201
	202	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
50dcf89d DE	203	}
50dcf89d DE	204	}
df8e5fb3 MS	205	#else
	206	static void io_receive(struct udevice *dev)
	207	{
	208	u16 buffer[HEADER_WORDS + 128];
50dcf89d	209
df8e5fb3 MS	210	if (!misc_read(dev, 0, buffer, 0))
	211	rx_ctr++;
	212	}
	213	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
	214
	215	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
db1d03a2	216	static void io_reflect(uint fpga)
50dcf89d DE	217	{
	218	u16 buffer[128];
	219
db1d03a2 MS	220	uint k = 0;
db1d03a2 MS	221	uint n;
50dcf89d DE	222	u16 rx_tx_status;
	223
	224	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	225
	226	while (rx_tx_status & STATE_RX_DATA_AVAILABLE) {
	227	FPGA_GET_REG(fpga, ep.receive_data, &buffer[k++]);
	228	if (rx_tx_status & STATE_RX_DATA_LAST)
	229	break;
	230
	231	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	232	}
	233
	234	if (!k)
	235	return;
	236
	237	for (n = 0; n < k; ++n)
	238	FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]);
	239
	240	FPGA_SET_REG(fpga, ep.rx_tx_control,
	241	CTRL_PROC_RECEIVE_ENABLE \| CTRL_FLUSH_TRANSMIT_BUFFER);
	242
	243	tx_ctr++;
	244	}
df8e5fb3 MS	245	#else
	246	static void io_reflect(struct udevice *dev)
	247	{
	248	u16 buffer[HEADER_WORDS + 128];
	249	struct io_generic_packet *header;
	250
	251	if (misc_read(dev, 0, buffer, 0))
	252	return;
	253
	254	header = (struct io_generic_packet *)&buffer;
50dcf89d	255
df8e5fb3 MS	256	misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length);
	257	}
	258	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
	259
	260	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
50dcf89d DE	261	/*
	262	* FPGA io-endpoint reflector
	263	*
	264	* Syntax:
	265	* ioreflect {fpga} {reportrate}
	266	*/
09140113	267	int do_ioreflect(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
50dcf89d	268	{
db1d03a2 MS	269	uint fpga;
db1d03a2 MS	270	uint rate = 0;
50dcf89d DE	271	unsigned long long last_seen = 0;
	272
	273	if (argc < 2)
	274	return CMD_RET_USAGE;
	275
	276	fpga = simple_strtoul(argv[1], NULL, 10);
	277
	278	/*
	279	* If another parameter, it is the report rate in packets.
	280	*/
	281	if (argc > 2)
	282	rate = simple_strtoul(argv[2], NULL, 10);
	283
db1d03a2	284	/* Enable receive path */
50dcf89d DE	285	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
50dcf89d DE	286
db1d03a2	287	/* Set device address to dummy 1*/
50dcf89d DE	288	FPGA_SET_REG(fpga, ep.device_address, 1);
	289
	290	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
	291
	292	while (1) {
	293	u16 top_int;
	294	u16 rx_tx_status;
	295
	296	FPGA_GET_REG(fpga, top_interrupt, &top_int);
	297	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	298
ba75772f	299	io_check_status(fpga, rx_tx_status, STATUS_SILENT);
50dcf89d DE	300	if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
	301	(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
	302	io_reflect(fpga);
	303
	304	if (rate) {
	305	if (!(tx_ctr % rate) && (tx_ctr != last_seen))
	306	printf("refl %llu, err %llu\n", tx_ctr,
	307	err_ctr);
	308	last_seen = tx_ctr;
	309	}
	310
	311	if (ctrlc())
	312	break;
	313	}
	314
	315	return 0;
	316	}
df8e5fb3 MS	317	#else
	318	/*
	319	* FPGA io-endpoint reflector
	320	*
	321	* Syntax:
	322	* ioreflect {reportrate}
	323	*/
09140113	324	int do_ioreflect(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
df8e5fb3 MS	325	{
	326	struct udevice *fpga;
	327	struct regmap *map;
	328	uint rate = 0;
	329	unsigned long long last_seen = 0;
	330
	331	if (!dev) {
	332	printf("No device selected\n");
	333	return 1;
	334	}
	335
	336	gdsys_soc_get_fpga(dev, &fpga);
	337	regmap_init_mem(dev_ofnode(dev), &map);
	338
	339	/* Enable receive path */
	340	misc_set_enabled(dev, true);
	341
	342	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
	343
	344	while (1) {
	345	uint top_int;
	346
	347	ihs_fpga_get(map, top_interrupt, &top_int);
	348	io_check_status(dev, STATUS_SILENT);
	349	if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) &&
	350	(top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS))
	351	io_reflect(dev);
	352
	353	if (rate) {
	354	if (!(tx_ctr % rate) && (tx_ctr != last_seen))
	355	printf("refl %llu, err %llu\n", tx_ctr,
	356	err_ctr);
	357	last_seen = tx_ctr;
	358	}
	359
	360	if (ctrlc())
	361	break;
	362	}
	363
	364	return 0;
	365	}
	366	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
50dcf89d	367
db1d03a2 MS	368	#define DISP_LINE_LEN 16
db1d03a2 MS	369
df8e5fb3	370	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
50dcf89d DE	371	/*
	372	* FPGA io-endpoint looptest
	373	*
	374	* Syntax:
	375	* ioloop {fpga} {size} {rate}
	376	*/
09140113	377	int do_ioloop(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
50dcf89d	378	{
db1d03a2 MS	379	uint fpga;
	380	uint size;
	381	uint rate = 0;
50dcf89d DE	382
	383	if (argc < 3)
	384	return CMD_RET_USAGE;
	385
	386	/*
	387	* FPGA is specified since argc > 2
	388	*/
	389	fpga = simple_strtoul(argv[1], NULL, 10);
	390
	391	/*
	392	* packet size is specified since argc > 2
	393	*/
	394	size = simple_strtoul(argv[2], NULL, 10);
	395
	396	/*
	397	* If another parameter, it is the test rate in packets per second.
	398	*/
	399	if (argc > 3)
	400	rate = simple_strtoul(argv[3], NULL, 10);
	401
	402	/* enable receive path */
	403	FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);
	404
	405	/* set device address to dummy 1*/
	406	FPGA_SET_REG(fpga, ep.device_address, 1);
	407
	408	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
	409
	410	while (1) {
	411	u16 top_int;
	412	u16 rx_tx_status;
	413
	414	FPGA_GET_REG(fpga, top_interrupt, &top_int);
	415	FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);
	416
ba75772f	417	io_check_status(fpga, rx_tx_status, STATUS_LOUD);
50dcf89d DE	418	if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
	419	io_send(fpga, size);
	420	if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
	421	io_receive(fpga);
	422
	423	if (rate) {
	424	if (ctrlc())
	425	break;
	426	udelay(1000000 / rate);
	427	if (!(tx_ctr % rate))
db1d03a2	428	printf("d %llu, tx %llu, rx %llu, err %llu\n",
50dcf89d DE	429	tx_ctr - rx_ctr, tx_ctr, rx_ctr,
	430	err_ctr);
	431	}
	432	}
	433
	434	return 0;
	435	}
df8e5fb3 MS	436	#else
	437	/*
	438	* FPGA io-endpoint looptest
	439	*
	440	* Syntax:
	441	* ioloop {size} {rate}
	442	*/
09140113	443	int do_ioloop(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
df8e5fb3 MS	444	{
	445	uint size;
	446	uint rate = 0;
	447	struct udevice *fpga;
	448	struct regmap *map;
	449
	450	if (!dev) {
	451	printf("No device selected\n");
	452	return 1;
	453	}
50dcf89d	454
df8e5fb3 MS	455	gdsys_soc_get_fpga(dev, &fpga);
	456	regmap_init_mem(dev_ofnode(dev), &map);
	457
	458	if (argc < 2)
	459	return CMD_RET_USAGE;
	460
	461	/*
	462	* packet size is specified since argc > 1
	463	*/
	464	size = simple_strtoul(argv[2], NULL, 10);
	465
	466	/*
	467	* If another parameter, it is the test rate in packets per second.
	468	*/
	469	if (argc > 2)
	470	rate = simple_strtoul(argv[3], NULL, 10);
	471
	472	/* Enable receive path */
	473	misc_set_enabled(dev, true);
	474
	475	rx_ctr = 0; tx_ctr = 0; err_ctr = 0;
	476
	477	while (1) {
	478	uint top_int;
	479
	480	if (ctrlc())
	481	break;
	482
	483	ihs_fpga_get(map, top_interrupt, &top_int);
	484
	485	io_check_status(dev, STATUS_LOUD);
	486	if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)
	487	io_send(dev, size);
	488	if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)
	489	io_receive(dev);
	490
	491	if (rate) {
	492	udelay(1000000 / rate);
	493	if (!(tx_ctr % rate))
	494	printf("d %llu, tx %llu, rx %llu, err %llu\n",
	495	tx_ctr - rx_ctr, tx_ctr, rx_ctr,
	496	err_ctr);
	497	}
	498	}
	499	return 0;
	500	}
	501	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
	502
	503	#ifndef CONFIG_GDSYS_LEGACY_DRIVERS
09140113	504	int do_iodev(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
df8e5fb3 MS	505	{
	506	struct udevice *ioep = NULL;
	507	struct udevice *board;
	508	char name[8];
	509	int ret;
	510
	511	if (board_get(&board))
	512	return CMD_RET_FAILURE;
	513
	514	if (argc > 1) {
	515	int i = simple_strtoul(argv[1], NULL, 10);
	516
	517	snprintf(name, sizeof(name), "ioep%d", i);
	518
	519	ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
	520
	521	if (ret \|\| !ioep) {
	522	printf("Invalid IOEP %d\n", i);
	523	return CMD_RET_FAILURE;
	524	}
	525
	526	dev = ioep;
	527	} else {
	528	int i = 0;
	529
	530	while (1) {
	531	snprintf(name, sizeof(name), "ioep%d", i);
	532
	533	ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
	534
	535	if (ret \|\| !ioep)
	536	break;
	537
	538	printf("IOEP %d:\t%s\n", i++, ioep->name);
	539	}
	540
	541	if (dev)
	542	printf("\nSelected IOEP: %s\n", dev->name);
	543	else
	544	puts("\nNo IOEP selected.\n");
	545	}
	546
	547	return 0;
	548	}
	549	#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */
	550
	551	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
50dcf89d DE	552	U_BOOT_CMD(
	553	ioloop, 4, 0, do_ioloop,
	554	"fpga io-endpoint looptest",
	555	"fpga packetsize [packets/sec]"
	556	);
	557
	558	U_BOOT_CMD(
	559	ioreflect, 3, 0, do_ioreflect,
	560	"fpga io-endpoint reflector",
	561	"fpga reportrate"
	562	);
df8e5fb3 MS	563	#else
	564	U_BOOT_CMD(
	565	ioloop, 3, 0, do_ioloop,
	566	"fpga io-endpoint looptest",
	567	"packetsize [packets/sec]"
	568	);
	569
	570	U_BOOT_CMD(
	571	ioreflect, 2, 0, do_ioreflect,
	572	"fpga io-endpoint reflector",
	573	"reportrate"
	574	);
	575
	576	U_BOOT_CMD(
	577	iodev, 2, 0, do_iodev,
	578	"fpga io-endpoint listing/selection",
	579	"[ioep device to select]"
	580	);
	581	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */