[J-u-boot.git] / arch / powerpc / cpu / mpc86xx / mp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <cpu_func.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <ioports.h>
#include <lmb.h>
#include <asm/io.h>
#include <asm/mp.h>

DECLARE_GLOBAL_DATA_PTR;

int cpu_reset(u32 nr)
{
	/* dummy function so common/cmd_mp.c will build
	 * should be implemented in the future, when cpu_release()
	 * is supported.  Be aware there may be a similiar bug
	 * as exists on MPC85xx w/its PIC having a timing window
	 * associated to resetting the core */
	return 1;
}

int cpu_status(u32 nr)
{
	/* dummy function so common/cmd_mp.c will build */
	return 0;
}

int cpu_disable(u32 nr)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;

	switch (nr) {
	case 0:
		setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
		break;
	case 1:
		setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
		break;
	default:
		printf("Invalid cpu number for disable %d\n", nr);
		return 1;
	}

	return 0;
}

int is_core_disabled(int nr) {
	immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	ccsr_gur_t *gur = &immap->im_gur;
	u32 devdisr = in_be32(&gur->devdisr);

	switch (nr) {
	case 0:
		return (devdisr & MPC86xx_DEVDISR_CPU0);
	case 1:
		return (devdisr & MPC86xx_DEVDISR_CPU1);
	default:
		printf("Invalid cpu number for disable %d\n", nr);
	}

	return 0;
}

int cpu_release(u32 nr, int argc, char *const argv[])
{
	/* dummy function so common/cmd_mp.c will build
	 * should be implemented in the future */
	return 1;
}

u32 determine_mp_bootpg(unsigned int *pagesize)
{
	if (pagesize)
		*pagesize = 4096;

	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
	if ((u64)gd->ram_size > 0xfffff000)
		return (0xfff00000);

	return (gd->ram_size - (1024 * 1024));
}

void cpu_mp_lmb_reserve(struct lmb *lmb)
{
	u32 bootpg = determine_mp_bootpg(NULL);

	/* tell u-boot we stole a page */
	lmb_reserve(lmb, bootpg, 4096);
}

/*
 * Copy the code for other cpus to execute into an
 * aligned location accessible via BPTR
 */
void setup_mp(void)
{
	extern ulong __secondary_start_page;
	ulong fixup = (ulong)&__secondary_start_page;
	u32 bootpg = determine_mp_bootpg(NULL);
	u32 bootpg_va;

	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
		/* We're not covered by the DDR mapping, set up BAT  */
		write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
			  BATU_VS | BATU_VP,
			  bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
		bootpg_va = CONFIG_SYS_SCRATCH_VA;
	} else {
		bootpg_va = bootpg;
	}

	memcpy((void *)bootpg_va, (void *)fixup, 4096);
	flush_cache(bootpg_va, 4096);

	/* remove the temporary BAT mapping */
	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
		write_bat(DBAT7, 0, 0);

	/* If the physical location of bootpg is not at fff00000, set BPTR */
	if (bootpg != 0xfff00000)
		out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
			 (bootpg >> 12));
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4194b366 KG	2	/*
4194b366 KG	3	* Copyright 2008-2010 Freescale Semiconductor, Inc.
4194b366 KG	4	*/
4194b366 KG	5
1266df88	6	#include <common.h>
62f9b654	7	#include <cpu_func.h>
1266df88 BB	8	#include <asm/processor.h>
	9	#include <asm/mmu.h>
	10	#include <ioports.h>
	11	#include <lmb.h>
	12	#include <asm/io.h>
7649a590	13	#include <asm/mp.h>
1266df88 BB	14
	15	DECLARE_GLOBAL_DATA_PTR;
	16
20b016a3	17	int cpu_reset(u32 nr)
7649a590 KG	18	{
	19	/* dummy function so common/cmd_mp.c will build
	20	* should be implemented in the future, when cpu_release()
	21	* is supported. Be aware there may be a similiar bug
	22	* as exists on MPC85xx w/its PIC having a timing window
	23	* associated to resetting the core */
	24	return 1;
	25	}
	26
20b016a3	27	int cpu_status(u32 nr)
1266df88	28	{
7649a590 KG	29	/* dummy function so common/cmd_mp.c will build */
	30	return 0;
	31	}
	32
20b016a3	33	int cpu_disable(u32 nr)
4194b366	34	{
c894852b KG	35	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
	36	volatile ccsr_gur_t *gur = &immap->im_gur;
	37
	38	switch (nr) {
	39	case 0:
	40	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
	41	break;
	42	case 1:
	43	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
	44	break;
	45	default:
	46	printf("Invalid cpu number for disable %d\n", nr);
	47	return 1;
	48	}
	49
	50	return 0;
4194b366 KG	51	}
4194b366 KG	52
8f3a7fa4 KG	53	int is_core_disabled(int nr) {
	54	immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
	55	ccsr_gur_t *gur = &immap->im_gur;
	56	u32 devdisr = in_be32(&gur->devdisr);
	57
	58	switch (nr) {
	59	case 0:
	60	return (devdisr & MPC86xx_DEVDISR_CPU0);
	61	case 1:
	62	return (devdisr & MPC86xx_DEVDISR_CPU1);
	63	default:
	64	printf("Invalid cpu number for disable %d\n", nr);
	65	}
	66
	67	return 0;
	68	}
	69
09140113	70	int cpu_release(u32 nr, int argc, char *const argv[])
7649a590 KG	71	{
	72	/* dummy function so common/cmd_mp.c will build
	73	* should be implemented in the future */
	74	return 1;
	75	}
1266df88	76
eb539412	77	u32 determine_mp_bootpg(unsigned int *pagesize)
7649a590	78	{
eb539412 YS	79	if (pagesize)
	80	*pagesize = 4096;
	81
1266df88 BB	82	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
1266df88 BB	83	if ((u64)gd->ram_size > 0xfffff000)
7649a590 KG	84	return (0xfff00000);
	85
	86	return (gd->ram_size - (1024 * 1024));
	87	}
	88
	89	void cpu_mp_lmb_reserve(struct lmb *lmb)
	90	{
eb539412	91	u32 bootpg = determine_mp_bootpg(NULL);
1266df88 BB	92
	93	/* tell u-boot we stole a page */
	94	lmb_reserve(lmb, bootpg, 4096);
	95	}
	96
	97	/*
	98	* Copy the code for other cpus to execute into an
	99	* aligned location accessible via BPTR
	100	*/
	101	void setup_mp(void)
	102	{
	103	extern ulong __secondary_start_page;
	104	ulong fixup = (ulong)&__secondary_start_page;
eb539412	105	u32 bootpg = determine_mp_bootpg(NULL);
1266df88 BB	106	u32 bootpg_va;
1266df88 BB	107
1266df88 BB	108	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
	109	/* We're not covered by the DDR mapping, set up BAT */
	110	write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA \| BATU_BL_128K \|
	111	BATU_VS \| BATU_VP,
	112	bootpg \| BATL_PP_RW \| BATL_MEMCOHERENCE);
	113	bootpg_va = CONFIG_SYS_SCRATCH_VA;
	114	} else {
	115	bootpg_va = bootpg;
	116	}
	117
	118	memcpy((void )bootpg_va, (void )fixup, 4096);
	119	flush_cache(bootpg_va, 4096);
	120
	121	/* remove the temporary BAT mapping */
	122	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
	123	write_bat(DBAT7, 0, 0);
	124
	125	/* If the physical location of bootpg is not at fff00000, set BPTR */
	126	if (bootpg != 0xfff00000)
	127	out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 \|
	128	(bootpg >> 12));
	129	}