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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
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2/*
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, [email protected].
5 *
6 * (C) Copyright 2002 (440 port)
7 * Scott McNutt, Artesyn Communication Producs, [email protected]
8 *
9 * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
10 * Xianghua Xiao ([email protected])
11 *
cfc7a7f5 12 * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
c934f655 13 * Jeff Brown
debb7354 14 * Srikanth Srinivasan ([email protected])
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15 */
16
17#include <common.h>
c30b7adb 18#include <irq_func.h>
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19#include <mpc86xx.h>
20#include <command.h>
049f8d6f 21#include <time.h>
debb7354 22#include <asm/processor.h>
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23#ifdef CONFIG_POST
24#include <post.h>
25#endif
debb7354 26
deff9b1d 27void interrupt_init_cpu(unsigned *decrementer_count)
debb7354 28{
6d0f6bcf 29 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
5c7cbcd3 30 volatile ccsr_pic_t *pic = &immr->im_pic;
debb7354 31
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32#ifdef CONFIG_POST
33 /*
34 * The POST word is stored in the PIC's TFRR register which gets
35 * cleared when the PIC is reset. Save it off so we can restore it
36 * later.
37 */
38 ulong post_word = post_word_load();
39#endif
40
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41 pic->gcr = MPC86xx_PICGCR_RST;
42 while (pic->gcr & MPC86xx_PICGCR_RST)
43 ;
44 pic->gcr = MPC86xx_PICGCR_MODE;
debb7354 45
6d0f6bcf 46 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
08dd988b 47 debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n",
ffff3ae5 48 (get_tbclk() / 1000000),
5c7cbcd3 49 *decrementer_count);
5c9efb36 50
cfc7a7f5 51#ifdef CONFIG_INTERRUPTS
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52
53 pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
7f2229b5 54 debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
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55
56 pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
7f2229b5 57 debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
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58
59 pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
7f2229b5 60 debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
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61
62#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
63 pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
7f2229b5 64 debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
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65#endif
66#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
67 pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
7f2229b5 68 debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
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69#endif
70
71 pic->ctpr = 0; /* 40080 clear current task priority register */
72#endif
73
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74#ifdef CONFIG_POST
75 post_word_store(post_word);
76#endif
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77}
78
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79/*
80 * timer_interrupt - gets called when the decrementer overflows,
81 * with interrupts disabled.
82 * Trivial implementation - no need to be really accurate.
83 */
ffff3ae5 84void timer_interrupt_cpu(struct pt_regs *regs)
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85{
86 /* nothing to do here */
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87}
88
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89/*
90 * Install and free a interrupt handler. Not implemented yet.
91 */
ffff3ae5 92void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
debb7354 93{
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94}
95
ffff3ae5 96void irq_free_handler(int vec)
debb7354 97{
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98}
99
c934f655 100/*
debb7354 101 * irqinfo - print information about PCI devices,not implemented.
debb7354 102 */
09140113 103int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
debb7354 104{
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105 return 0;
106}
107
108/*
109 * Handle external interrupts
110 */
ffff3ae5 111void external_interrupt(struct pt_regs *regs)
debb7354 112{
9d3915b2 113 puts("external_interrupt(oops!)\n");
debb7354 114}
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