[J-u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch3_serdes.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2016-2018 NXP
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <env.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <fsl-mc/ldpaa_wriop.h>

#ifdef CONFIG_SYS_FSL_SRDS_1
static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif

#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_ARCH_LX2160A
int xfi_dpmac[XFI14 + 1];
int sgmii_dpmac[SGMII18 + 1];
int a25gaui_dpmac[_25GE10 + 1];
int xlaui_dpmac[_40GE2 + 1];
int caui2_dpmac[_50GE2 + 1];
int caui4_dpmac[_100GE2 + 1];
#else
int xfi_dpmac[XFI8 + 1];
int sgmii_dpmac[SGMII16 + 1];
#endif
#endif

__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
	return;
}

/*
 *The return value of this func is the serdes protocol used.
 *Typically this function is called number of times depending
 *upon the number of serdes blocks in the Silicon.
 *Zero is used to denote that no serdes was enabled,
 *this is the case when golden RCW was used where DPAA2 bring was
 *intentionally removed to achieve boot to prompt
*/

__weak int serdes_get_number(int serdes, int cfg)
{
	return cfg;
}

int is_serdes_configured(enum srds_prtcl device)
{
	int ret = 0;

#ifdef CONFIG_SYS_FSL_SRDS_1
	if (!serdes1_prtcl_map[NONE])
		fsl_serdes_init();

	ret |= serdes1_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	if (!serdes2_prtcl_map[NONE])
		fsl_serdes_init();

	ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	if (!serdes3_prtcl_map[NONE])
		fsl_serdes_init();

	ret |= serdes3_prtcl_map[device];
#endif

	return !!ret;
}

int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 cfg = 0;
	int i;

	switch (sd) {
#ifdef CONFIG_SYS_FSL_SRDS_1
	case FSL_SRDS_1:
		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
		cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
		cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
		break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	case FSL_SRDS_2:
		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
		cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
		cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
		break;
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	case NXP_SRDS_3:
		cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
		cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
		cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
		break;
#endif
	default:
		printf("invalid SerDes%d\n", sd);
		break;
	}

	cfg = serdes_get_number(sd, cfg);

	/* Is serdes enabled at all? */
	if (cfg == 0)
		return -ENODEV;

	for (i = 0; i < SRDS_MAX_LANES; i++) {
		if (serdes_get_prtcl(sd, cfg, i) == device)
			return i;
	}

	return -ENODEV;
}

void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
		 u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 cfg;
	int lane;

	if (serdes_prtcl_map[NONE])
		return;

	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);

	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
	cfg >>= sd_prctl_shift;

	cfg = serdes_get_number(sd, cfg);
	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);

	if (!is_serdes_prtcl_valid(sd, cfg))
		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);

	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
		else {
			serdes_prtcl_map[lane_prtcl] = 1;
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_ARCH_LX2160A
			if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
				wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
						 (int)lane_prtcl);

			if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
				wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
						 (int)lane_prtcl);

			if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
				wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
						 (int)lane_prtcl);

			if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
				wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
						 (int)lane_prtcl);

			if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
				wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
						 (int)lane_prtcl);

			if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
				wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
						 (int)lane_prtcl);

#else
			switch (lane_prtcl) {
			case QSGMII_A:
			case QSGMII_B:
			case QSGMII_C:
			case QSGMII_D:
				wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
				break;
			default:
				if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
					wriop_init_dpmac(sd,
							 xfi_dpmac[lane_prtcl],
							 (int)lane_prtcl);

				 if (lane_prtcl >= SGMII1 &&
				     lane_prtcl <= SGMII16)
					wriop_init_dpmac(sd, sgmii_dpmac[
							 lane_prtcl],
							 (int)lane_prtcl);
				break;
			}
#endif
#endif
		}
	}

	/* Set the first element to indicate serdes has been initialized */
	serdes_prtcl_map[NONE] = 1;
}

__weak int get_serdes_volt(void)
{
	return -1;
}

__weak int set_serdes_volt(int svdd)
{
	return -1;
}

#define LNAGCR0_RT_RSTB		0x00600000

#define RSTCTL_RESET_MASK	0x000000E0

#define RSTCTL_RSTREQ		0x80000000
#define RSTCTL_RST_DONE		0x40000000
#define RSTCTL_RSTERR		0x20000000

#define RSTCTL_SDEN		0x00000020
#define RSTCTL_SDRST_B		0x00000040
#define RSTCTL_PLLRST_B		0x00000080

#define TCALCR_CALRST_B		0x08000000

struct serdes_prctl_info {
	u32 id;
	u32 mask;
	u32 shift;
};

struct serdes_prctl_info srds_prctl_info[] = {
#ifdef CONFIG_SYS_FSL_SRDS_1
	{.id = 1,
	 .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
	 .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
	},

#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	{.id = 2,
	 .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
	 .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
	},
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	{.id = 3,
	 .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
	 .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
	},
#endif
	{} /* NULL ENTRY */
};

static int get_serdes_prctl_info_idx(u32 serdes_id)
{
	int pos = 0;
	struct serdes_prctl_info *srds_info;

	/* loop until NULL ENTRY defined by .id=0 */
	for (srds_info = srds_prctl_info; srds_info->id != 0;
	     srds_info++, pos++) {
		if (srds_info->id == serdes_id)
			return pos;
	}

	return -1;
}

static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
				   struct ccsr_serdes __iomem *serdes_base,
				   bool cmplt)
{
	int i, pos;
	u32 cfg_tmp;

	pos = get_serdes_prctl_info_idx(serdes_id);
	if (pos == -1) {
		printf("invalid serdes_id %d\n", serdes_id);
		return;
	}

	cfg_tmp = cfg & srds_prctl_info[pos].mask;
	cfg_tmp >>= srds_prctl_info[pos].shift;

	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
		if (cmplt)
			setbits_le32(&serdes_base->lane[i].gcr0,
				     LNAGCR0_RT_RSTB);
		else
			clrbits_le32(&serdes_base->lane[i].gcr0,
				     LNAGCR0_RT_RSTB);
	}
}

static void do_pll_reset(u32 cfg,
			 struct ccsr_serdes __iomem *serdes_base)
{
	int i;

	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
		clrbits_le32(&serdes_base->bank[i].rstctl,
			     RSTCTL_RESET_MASK);
		udelay(1);

		setbits_le32(&serdes_base->bank[i].rstctl,
			     RSTCTL_RSTREQ);
	}
	udelay(1);
}

static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
{
	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
}

static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
				    struct ccsr_serdes __iomem *serdes_base)
{
	if (!(cfg == 0x3 && i == 1)) {
		udelay(1);
		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
		setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
	}
	udelay(1);
}

static void do_pll_reset_done(u32 cfg,
			      struct ccsr_serdes __iomem *serdes_base)
{
	int i;
	u32 reg = 0;

	for (i = 0; i < 2; i++) {
		reg = in_le32(&serdes_base->bank[i].pllcr0);
		if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
			setbits_le32(&serdes_base->bank[i].rstctl,
				     RSTCTL_RST_DONE);
		}
	}
}

static void do_serdes_enable(u32 cfg,
			     struct ccsr_serdes __iomem *serdes_base)
{
	int i;

	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
		udelay(1);

		setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
		udelay(1);
		/* Take the Rx/Tx calibration out of reset */
		do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
	}
}

static void do_pll_lock(u32 cfg,
			struct ccsr_serdes __iomem *serdes_base)
{
	int i;
	u32 reg = 0;

	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
		/* if the PLL is not locked, set RST_ERR */
		reg = in_le32(&serdes_base->bank[i].pllcr0);
		if (!((reg >> 23) & 0x1)) {
			setbits_le32(&serdes_base->bank[i].rstctl,
				     RSTCTL_RSTERR);
		} else {
			udelay(1);
			setbits_le32(&serdes_base->bank[i].rstctl,
				     RSTCTL_SDRST_B);
			udelay(1);
		}
	}
}

int setup_serdes_volt(u32 svdd)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	struct ccsr_serdes __iomem *serdes1_base =
			(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2
	struct ccsr_serdes __iomem *serdes2_base =
			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	struct ccsr_serdes __iomem *serdes3_base =
			(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
	u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif
	u32 cfg_tmp;
	int svdd_cur, svdd_tar;
	int ret = 1;

	/* Only support switch SVDD to 900mV */
	if (svdd != 900)
		return -EINVAL;

	/* Scale up to the LTC resolution is 1/4096V */
	svdd = (svdd * 4096) / 1000;

	svdd_tar = svdd;
	svdd_cur = get_serdes_volt();
	if (svdd_cur < 0)
		return -EINVAL;

	debug("%s: current SVDD: %x; target SVDD: %x\n",
	      __func__, svdd_cur, svdd_tar);
	if (svdd_cur == svdd_tar)
		return 0;

	/* Put the all enabled lanes in reset */
#ifdef CONFIG_SYS_FSL_SRDS_1
	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
#endif

#ifdef CONFIG_SYS_FSL_SRDS_2
	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
#endif

	/* Put the all enabled PLL in reset */
#ifdef CONFIG_SYS_FSL_SRDS_1
	cfg_tmp = cfg_rcwsrds1 & 0x3;
	do_pll_reset(cfg_tmp, serdes1_base);
#endif

#ifdef CONFIG_SYS_FSL_SRDS_2
	cfg_tmp = cfg_rcwsrds1 & 0xC;
	cfg_tmp >>= 2;
	do_pll_reset(cfg_tmp, serdes2_base);
#endif

#ifdef CONFIG_SYS_NXP_SRDS_3
	cfg_tmp = cfg_rcwsrds3 & 0x30;
	cfg_tmp >>= 4;
	do_pll_reset(cfg_tmp, serdes3_base);
#endif

	/* Put the Rx/Tx calibration into reset */
#ifdef CONFIG_SYS_FSL_SRDS_1
	do_rx_tx_cal_reset(serdes1_base);
#endif

#ifdef CONFIG_SYS_FSL_SRDS_2
	do_rx_tx_cal_reset(serdes2_base);
#endif

#ifdef CONFIG_SYS_NXP_SRDS_3
	do_rx_tx_cal_reset(serdes3_base);
#endif

	ret = set_serdes_volt(svdd);
	if (ret < 0) {
		printf("could not change SVDD\n");
		ret = -1;
	}

	/* For each PLL that’s not disabled via RCW enable the SERDES */
#ifdef CONFIG_SYS_FSL_SRDS_1
	cfg_tmp = cfg_rcwsrds1 & 0x3;
	do_serdes_enable(cfg_tmp, serdes1_base);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	cfg_tmp = cfg_rcwsrds1 & 0xC;
	cfg_tmp >>= 2;
	do_serdes_enable(cfg_tmp, serdes2_base);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	cfg_tmp = cfg_rcwsrds3 & 0x30;
	cfg_tmp >>= 4;
	do_serdes_enable(cfg_tmp, serdes3_base);
#endif

	/* Wait for at at least 625us, ensure the PLLs being reset are locked */
	udelay(800);

#ifdef CONFIG_SYS_FSL_SRDS_1
	cfg_tmp = cfg_rcwsrds1 & 0x3;
	do_pll_lock(cfg_tmp, serdes1_base);
#endif

#ifdef CONFIG_SYS_FSL_SRDS_2
	cfg_tmp = cfg_rcwsrds1 & 0xC;
	cfg_tmp >>= 2;
	do_pll_lock(cfg_tmp, serdes2_base);
#endif

#ifdef CONFIG_SYS_NXP_SRDS_3
	cfg_tmp = cfg_rcwsrds3 & 0x30;
	cfg_tmp >>= 4;
	do_pll_lock(cfg_tmp, serdes3_base);
#endif

	/* Take the all enabled lanes out of reset */
#ifdef CONFIG_SYS_FSL_SRDS_1
	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
#endif

#ifdef CONFIG_SYS_NXP_SRDS_3
	do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
#endif

	/* For each PLL being reset, and achieved PLL lock set RST_DONE */
#ifdef CONFIG_SYS_FSL_SRDS_1
	cfg_tmp = cfg_rcwsrds1 & 0x3;
	do_pll_reset_done(cfg_tmp, serdes1_base);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	cfg_tmp = cfg_rcwsrds1 & 0xC;
	cfg_tmp >>= 2;
	do_pll_reset_done(cfg_tmp, serdes2_base);
#endif

#ifdef CONFIG_SYS_NXP_SRDS_3
	cfg_tmp = cfg_rcwsrds3 & 0x30;
	cfg_tmp >>= 4;
	do_pll_reset_done(cfg_tmp, serdes3_base);
#endif

	return ret;
}

void fsl_serdes_init(void)
{
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
	int i , j;

#ifdef CONFIG_ARCH_LX2160A
	for (i = XFI1, j = 1; i <= XFI14; i++, j++)
		xfi_dpmac[i] = j;

	for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
		sgmii_dpmac[i] = j;

	for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
		a25gaui_dpmac[i] = j;

	for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
		xlaui_dpmac[i] = j;

	for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
		caui2_dpmac[i] = j;

	for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
		caui4_dpmac[i] = j;
#else
	for (i = XFI1, j = 1; i <= XFI8; i++, j++)
		xfi_dpmac[i] = j;

	for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
		sgmii_dpmac[i] = j;
#endif
#endif

#ifdef CONFIG_SYS_FSL_SRDS_1
	serdes_init(FSL_SRDS_1,
		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
		    FSL_CHASSIS3_SRDS1_REGSR,
		    FSL_CHASSIS3_SRDS1_PRTCL_MASK,
		    FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
		    serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	serdes_init(FSL_SRDS_2,
		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
		    FSL_CHASSIS3_SRDS2_REGSR,
		    FSL_CHASSIS3_SRDS2_PRTCL_MASK,
		    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
		    serdes2_prtcl_map);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	serdes_init(NXP_SRDS_3,
		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
		    FSL_CHASSIS3_SRDS3_REGSR,
		    FSL_CHASSIS3_SRDS3_PRTCL_MASK,
		    FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
		    serdes3_prtcl_map);
#endif
}

int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	char scfg[16], snum[16];
	int cfgr = 0;
	u32 cfg;

	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
	cfg >>= sd_prctl_shift;
	cfg = serdes_get_number(sd, cfg);

#if defined(SRDS_BITS_PER_LANE)
	/*
	 * reverse lanes, lane 0 should be printed first so it must be moved to
	 * high order bits.
	 * For example bb58 should read 85bb, lane 0 being protocol 8.
	 * This only applies to SoCs that define SRDS_BITS_PER_LANE and have
	 * independent per-lane protocol configuration, at this time LS1028A and
	 * LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
	 * lanes as a single value.
	 */
	for (int i = 0; i < SRDS_MAX_LANES; i++) {
		int tmp;

		tmp = cfg >> (i * SRDS_BITS_PER_LANE);
		tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
		tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
		cfgr |= tmp;
	}
#endif /* SRDS_BITS_PER_LANE */

	snprintf(snum, 16, "serdes%d", sd);
	snprintf(scfg, 16, "%x", cfgr);
	env_set(snum, scfg);

	return 0;
}

int serdes_misc_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
	serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
		       FSL_CHASSIS3_SRDS1_PRTCL_MASK,
		       FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
	serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
		       FSL_CHASSIS3_SRDS2_PRTCL_MASK,
		       FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
	serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
		       FSL_CHASSIS3_SRDS3_PRTCL_MASK,
		       FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
#endif

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
31d34c6c	2	/*
6252faa0	3	* Copyright 2016-2018 NXP
9f3183d2	4	* Copyright 2014-2015 Freescale Semiconductor, Inc.
31d34c6c ML	5	*/
	6
	7	#include <common.h>
09140113	8	#include <env.h>
31d34c6c	9	#include <asm/io.h>
1221ce45	10	#include <linux/errno.h>
31d34c6c	11	#include <asm/arch/fsl_serdes.h>
9f3183d2	12	#include <asm/arch/soc.h>
9cc2c471	13	#include <fsl-mc/ldpaa_wriop.h>
31d34c6c ML	14
	15	#ifdef CONFIG_SYS_FSL_SRDS_1
	16	static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
	17	#endif
	18	#ifdef CONFIG_SYS_FSL_SRDS_2
	19	static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
	20	#endif
6252faa0 PJ	21	#ifdef CONFIG_SYS_NXP_SRDS_3
	22	static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
	23	#endif
31d34c6c	24
1f55a938	25	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
4909b89e PJ	26	#ifdef CONFIG_ARCH_LX2160A
	27	int xfi_dpmac[XFI14 + 1];
	28	int sgmii_dpmac[SGMII18 + 1];
	29	int a25gaui_dpmac[_25GE10 + 1];
	30	int xlaui_dpmac[_40GE2 + 1];
	31	int caui2_dpmac[_50GE2 + 1];
	32	int caui4_dpmac[_100GE2 + 1];
	33	#else
99e904c1 PK	34	int xfi_dpmac[XFI8 + 1];
	35	int sgmii_dpmac[SGMII16 + 1];
	36	#endif
4909b89e	37	#endif
99e904c1	38
1b7dba99 PK	39	__weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
	40	{
	41	return;
	42	}
	43
6d9b82d0 AK	44	/*
	45	*The return value of this func is the serdes protocol used.
	46	*Typically this function is called number of times depending
	47	*upon the number of serdes blocks in the Silicon.
	48	*Zero is used to denote that no serdes was enabled,
	49	*this is the case when golden RCW was used where DPAA2 bring was
	50	*intentionally removed to achieve boot to prompt
	51	*/
	52
	53	__weak int serdes_get_number(int serdes, int cfg)
	54	{
	55	return cfg;
	56	}
	57
31d34c6c ML	58	int is_serdes_configured(enum srds_prtcl device)
	59	{
	60	int ret = 0;
	61
	62	#ifdef CONFIG_SYS_FSL_SRDS_1
71fe2225 HZ	63	if (!serdes1_prtcl_map[NONE])
	64	fsl_serdes_init();
	65
31d34c6c ML	66	ret \|= serdes1_prtcl_map[device];
	67	#endif
	68	#ifdef CONFIG_SYS_FSL_SRDS_2
71fe2225 HZ	69	if (!serdes2_prtcl_map[NONE])
	70	fsl_serdes_init();
	71
31d34c6c ML	72	ret \|= serdes2_prtcl_map[device];
31d34c6c ML	73	#endif
6252faa0 PJ	74	#ifdef CONFIG_SYS_NXP_SRDS_3
	75	if (!serdes3_prtcl_map[NONE])
	76	fsl_serdes_init();
	77
	78	ret \|= serdes3_prtcl_map[device];
	79	#endif
31d34c6c ML	80
	81	return !!ret;
	82	}
	83
	84	int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
	85	{
	86	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
7b45b383	87	u32 cfg = 0;
31d34c6c ML	88	int i;
	89
	90	switch (sd) {
	91	#ifdef CONFIG_SYS_FSL_SRDS_1
	92	case FSL_SRDS_1:
7b45b383 PK	93	cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
	94	cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK;
	95	cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
31d34c6c ML	96	break;
	97	#endif
	98	#ifdef CONFIG_SYS_FSL_SRDS_2
	99	case FSL_SRDS_2:
7b45b383 PK	100	cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
	101	cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK;
	102	cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
31d34c6c	103	break;
6252faa0 PJ	104	#endif
	105	#ifdef CONFIG_SYS_NXP_SRDS_3
	106	case NXP_SRDS_3:
	107	cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
	108	cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
	109	cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
	110	break;
31d34c6c ML	111	#endif
	112	default:
	113	printf("invalid SerDes%d\n", sd);
	114	break;
	115	}
6d9b82d0 AK	116
	117	cfg = serdes_get_number(sd, cfg);
	118
31d34c6c ML	119	/* Is serdes enabled at all? */
	120	if (cfg == 0)
	121	return -ENODEV;
	122
	123	for (i = 0; i < SRDS_MAX_LANES; i++) {
	124	if (serdes_get_prtcl(sd, cfg, i) == device)
	125	return i;
	126	}
	127
	128	return -ENODEV;
	129	}
	130
7b45b383 PK	131	void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
7b45b383 PK	132	u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
31d34c6c ML	133	{
	134	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	135	u32 cfg;
	136	int lane;
	137
71fe2225 HZ	138	if (serdes_prtcl_map[NONE])
	139	return;
	140
1a338921	141	memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT);
31d34c6c	142
7b45b383	143	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
31d34c6c	144	cfg >>= sd_prctl_shift;
6d9b82d0 AK	145
6d9b82d0 AK	146	cfg = serdes_get_number(sd, cfg);
31d34c6c ML	147	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
	148
	149	if (!is_serdes_prtcl_valid(sd, cfg))
	150	printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
	151
	152	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
	153	enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
	154	if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
	155	debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
9cc2c471	156	else {
31d34c6c	157	serdes_prtcl_map[lane_prtcl] = 1;
1f55a938	158	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
4909b89e PJ	159	#ifdef CONFIG_ARCH_LX2160A
	160	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
	161	wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
	162	(int)lane_prtcl);
	163
	164	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
	165	wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
	166	(int)lane_prtcl);
	167
	168	if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
	169	wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
	170	(int)lane_prtcl);
	171
	172	if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
	173	wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
	174	(int)lane_prtcl);
	175
	176	if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
	177	wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
	178	(int)lane_prtcl);
	179
	180	if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
	181	wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
	182	(int)lane_prtcl);
	183
	184	#else
b1caae1b PK	185	switch (lane_prtcl) {
b1caae1b PK	186	case QSGMII_A:
b1caae1b	187	case QSGMII_B:
b1caae1b	188	case QSGMII_C:
b1caae1b	189	case QSGMII_D:
1b7dba99	190	wriop_init_dpmac_qsgmii(sd, (int)lane_prtcl);
b1caae1b PK	191	break;
b1caae1b PK	192	default:
99e904c1 PK	193	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
	194	wriop_init_dpmac(sd,
	195	xfi_dpmac[lane_prtcl],
	196	(int)lane_prtcl);
	197
b1caae1b	198	if (lane_prtcl >= SGMII1 &&
99e904c1 PK	199	lane_prtcl <= SGMII16)
	200	wriop_init_dpmac(sd, sgmii_dpmac[
	201	lane_prtcl],
b1caae1b PK	202	(int)lane_prtcl);
	203	break;
	204	}
4909b89e	205	#endif
9cc2c471 PK	206	#endif
9cc2c471 PK	207	}
31d34c6c	208	}
71fe2225 HZ	209
	210	/* Set the first element to indicate serdes has been initialized */
	211	serdes_prtcl_map[NONE] = 1;
31d34c6c ML	212	}
31d34c6c ML	213
a1f95ff7 RB	214	__weak int get_serdes_volt(void)
	215	{
	216	return -1;
	217	}
	218
	219	__weak int set_serdes_volt(int svdd)
	220	{
	221	return -1;
	222	}
	223
	224	#define LNAGCR0_RT_RSTB 0x00600000
	225
	226	#define RSTCTL_RESET_MASK 0x000000E0
	227
	228	#define RSTCTL_RSTREQ 0x80000000
	229	#define RSTCTL_RST_DONE 0x40000000
	230	#define RSTCTL_RSTERR 0x20000000
	231
	232	#define RSTCTL_SDEN 0x00000020
	233	#define RSTCTL_SDRST_B 0x00000040
	234	#define RSTCTL_PLLRST_B 0x00000080
	235
	236	#define TCALCR_CALRST_B 0x08000000
	237
	238	struct serdes_prctl_info {
	239	u32 id;
	240	u32 mask;
	241	u32 shift;
	242	};
	243
	244	struct serdes_prctl_info srds_prctl_info[] = {
	245	#ifdef CONFIG_SYS_FSL_SRDS_1
	246	{.id = 1,
	247	.mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
	248	.shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
	249	},
	250
	251	#endif
	252	#ifdef CONFIG_SYS_FSL_SRDS_2
	253	{.id = 2,
	254	.mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
	255	.shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
	256	},
6252faa0 PJ	257	#endif
	258	#ifdef CONFIG_SYS_NXP_SRDS_3
	259	{.id = 3,
	260	.mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
	261	.shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
	262	},
a1f95ff7 RB	263	#endif
	264	{} /* NULL ENTRY */
	265	};
	266
	267	static int get_serdes_prctl_info_idx(u32 serdes_id)
	268	{
	269	int pos = 0;
	270	struct serdes_prctl_info *srds_info;
	271
	272	/* loop until NULL ENTRY defined by .id=0 */
	273	for (srds_info = srds_prctl_info; srds_info->id != 0;
	274	srds_info++, pos++) {
	275	if (srds_info->id == serdes_id)
	276	return pos;
	277	}
	278
	279	return -1;
	280	}
	281
	282	static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
	283	struct ccsr_serdes __iomem *serdes_base,
	284	bool cmplt)
	285	{
	286	int i, pos;
	287	u32 cfg_tmp;
	288
	289	pos = get_serdes_prctl_info_idx(serdes_id);
	290	if (pos == -1) {
	291	printf("invalid serdes_id %d\n", serdes_id);
	292	return;
	293	}
	294
	295	cfg_tmp = cfg & srds_prctl_info[pos].mask;
	296	cfg_tmp >>= srds_prctl_info[pos].shift;
	297
	298	for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
	299	if (cmplt)
	300	setbits_le32(&serdes_base->lane[i].gcr0,
	301	LNAGCR0_RT_RSTB);
	302	else
	303	clrbits_le32(&serdes_base->lane[i].gcr0,
	304	LNAGCR0_RT_RSTB);
	305	}
	306	}
	307
	308	static void do_pll_reset(u32 cfg,
	309	struct ccsr_serdes __iomem *serdes_base)
	310	{
	311	int i;
	312
	313	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
	314	clrbits_le32(&serdes_base->bank[i].rstctl,
	315	RSTCTL_RESET_MASK);
	316	udelay(1);
	317
	318	setbits_le32(&serdes_base->bank[i].rstctl,
	319	RSTCTL_RSTREQ);
	320	}
	321	udelay(1);
	322	}
	323
	324	static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
	325	{
	326	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
327	clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
328	}
329
330	static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
331	struct ccsr_serdes __iomem *serdes_base)
332	{
333	if (!(cfg == 0x3 && i == 1)) {
334	udelay(1);
335	setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
336	setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
337	}
338	udelay(1);
339	}
340
341	static void do_pll_reset_done(u32 cfg,
342	struct ccsr_serdes __iomem *serdes_base)
343	{
344	int i;
345	u32 reg = 0;
346
347	for (i = 0; i < 2; i++) {
348	reg = in_le32(&serdes_base->bank[i].pllcr0);
349	if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
350	setbits_le32(&serdes_base->bank[i].rstctl,
351	RSTCTL_RST_DONE);
352	}
353	}
354	}
355
356	static void do_serdes_enable(u32 cfg,
357	struct ccsr_serdes __iomem *serdes_base)
358	{
359	int i;
360
361	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
362	setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
363	udelay(1);
364
365	setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
366	udelay(1);
367	/* Take the Rx/Tx calibration out of reset */
368	do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
369	}
370	}
371
372	static void do_pll_lock(u32 cfg,
373	struct ccsr_serdes __iomem *serdes_base)
374	{
375	int i;
376	u32 reg = 0;
377
378	for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
379	/* if the PLL is not locked, set RST_ERR */
380	reg = in_le32(&serdes_base->bank[i].pllcr0);
381	if (!((reg >> 23) & 0x1)) {
382	setbits_le32(&serdes_base->bank[i].rstctl,
383	RSTCTL_RSTERR);
384	} else {
385	udelay(1);
386	setbits_le32(&serdes_base->bank[i].rstctl,
387	RSTCTL_SDRST_B);
388	udelay(1);
389	}
390	}
391	}
392
393	int setup_serdes_volt(u32 svdd)
394	{
395	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
396	struct ccsr_serdes __iomem *serdes1_base =
397	(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
398	u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
399	#ifdef CONFIG_SYS_FSL_SRDS_2
400	struct ccsr_serdes __iomem *serdes2_base =
401	(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
402	u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
6252faa0 PJ	403	#endif
	404	#ifdef CONFIG_SYS_NXP_SRDS_3
	405	struct ccsr_serdes __iomem *serdes3_base =
	406	(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
	407	u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
a1f95ff7 RB	408	#endif
	409	u32 cfg_tmp;
	410	int svdd_cur, svdd_tar;
	411	int ret = 1;
	412
	413	/* Only support switch SVDD to 900mV */
	414	if (svdd != 900)
	415	return -EINVAL;
	416
	417	/* Scale up to the LTC resolution is 1/4096V */
	418	svdd = (svdd * 4096) / 1000;
	419
	420	svdd_tar = svdd;
	421	svdd_cur = get_serdes_volt();
	422	if (svdd_cur < 0)
	423	return -EINVAL;
	424
	425	debug("%s: current SVDD: %x; target SVDD: %x\n",
	426	__func__, svdd_cur, svdd_tar);
	427	if (svdd_cur == svdd_tar)
	428	return 0;
	429
	430	/* Put the all enabled lanes in reset */
	431	#ifdef CONFIG_SYS_FSL_SRDS_1
	432	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
	433	#endif
	434
	435	#ifdef CONFIG_SYS_FSL_SRDS_2
	436	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
	437	#endif
6252faa0 PJ	438	#ifdef CONFIG_SYS_NXP_SRDS_3
	439	do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
	440	#endif
a1f95ff7 RB	441
	442	/* Put the all enabled PLL in reset */
	443	#ifdef CONFIG_SYS_FSL_SRDS_1
	444	cfg_tmp = cfg_rcwsrds1 & 0x3;
	445	do_pll_reset(cfg_tmp, serdes1_base);
	446	#endif
	447
	448	#ifdef CONFIG_SYS_FSL_SRDS_2
	449	cfg_tmp = cfg_rcwsrds1 & 0xC;
	450	cfg_tmp >>= 2;
	451	do_pll_reset(cfg_tmp, serdes2_base);
	452	#endif
	453
6252faa0 PJ	454	#ifdef CONFIG_SYS_NXP_SRDS_3
	455	cfg_tmp = cfg_rcwsrds3 & 0x30;
	456	cfg_tmp >>= 4;
	457	do_pll_reset(cfg_tmp, serdes3_base);
	458	#endif
	459
a1f95ff7 RB	460	/* Put the Rx/Tx calibration into reset */
	461	#ifdef CONFIG_SYS_FSL_SRDS_1
	462	do_rx_tx_cal_reset(serdes1_base);
	463	#endif
	464
	465	#ifdef CONFIG_SYS_FSL_SRDS_2
	466	do_rx_tx_cal_reset(serdes2_base);
	467	#endif
	468
6252faa0 PJ	469	#ifdef CONFIG_SYS_NXP_SRDS_3
	470	do_rx_tx_cal_reset(serdes3_base);
	471	#endif
	472
a1f95ff7 RB	473	ret = set_serdes_volt(svdd);
	474	if (ret < 0) {
	475	printf("could not change SVDD\n");
	476	ret = -1;
	477	}
	478
	479	/* For each PLL that’s not disabled via RCW enable the SERDES */
	480	#ifdef CONFIG_SYS_FSL_SRDS_1
	481	cfg_tmp = cfg_rcwsrds1 & 0x3;
	482	do_serdes_enable(cfg_tmp, serdes1_base);
	483	#endif
	484	#ifdef CONFIG_SYS_FSL_SRDS_2
	485	cfg_tmp = cfg_rcwsrds1 & 0xC;
	486	cfg_tmp >>= 2;
	487	do_serdes_enable(cfg_tmp, serdes2_base);
	488	#endif
6252faa0 PJ	489	#ifdef CONFIG_SYS_NXP_SRDS_3
	490	cfg_tmp = cfg_rcwsrds3 & 0x30;
	491	cfg_tmp >>= 4;
	492	do_serdes_enable(cfg_tmp, serdes3_base);
	493	#endif
a1f95ff7 RB	494
	495	/* Wait for at at least 625us, ensure the PLLs being reset are locked */
	496	udelay(800);
	497
	498	#ifdef CONFIG_SYS_FSL_SRDS_1
	499	cfg_tmp = cfg_rcwsrds1 & 0x3;
	500	do_pll_lock(cfg_tmp, serdes1_base);
	501	#endif
	502
	503	#ifdef CONFIG_SYS_FSL_SRDS_2
	504	cfg_tmp = cfg_rcwsrds1 & 0xC;
	505	cfg_tmp >>= 2;
	506	do_pll_lock(cfg_tmp, serdes2_base);
	507	#endif
6252faa0 PJ	508
	509	#ifdef CONFIG_SYS_NXP_SRDS_3
	510	cfg_tmp = cfg_rcwsrds3 & 0x30;
	511	cfg_tmp >>= 4;
	512	do_pll_lock(cfg_tmp, serdes3_base);
	513	#endif
	514
a1f95ff7 RB	515	/* Take the all enabled lanes out of reset */
	516	#ifdef CONFIG_SYS_FSL_SRDS_1
	517	do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
	518	#endif
	519	#ifdef CONFIG_SYS_FSL_SRDS_2
	520	do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
	521	#endif
	522
6252faa0 PJ	523	#ifdef CONFIG_SYS_NXP_SRDS_3
	524	do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
	525	#endif
	526
a1f95ff7 RB	527	/* For each PLL being reset, and achieved PLL lock set RST_DONE */
	528	#ifdef CONFIG_SYS_FSL_SRDS_1
	529	cfg_tmp = cfg_rcwsrds1 & 0x3;
	530	do_pll_reset_done(cfg_tmp, serdes1_base);
	531	#endif
	532	#ifdef CONFIG_SYS_FSL_SRDS_2
	533	cfg_tmp = cfg_rcwsrds1 & 0xC;
	534	cfg_tmp >>= 2;
	535	do_pll_reset_done(cfg_tmp, serdes2_base);
	536	#endif
	537
6252faa0 PJ	538	#ifdef CONFIG_SYS_NXP_SRDS_3
	539	cfg_tmp = cfg_rcwsrds3 & 0x30;
	540	cfg_tmp >>= 4;
	541	do_pll_reset_done(cfg_tmp, serdes3_base);
	542	#endif
	543
a1f95ff7 RB	544	return ret;
	545	}
	546
31d34c6c ML	547	void fsl_serdes_init(void)
31d34c6c ML	548	{
1f55a938	549	#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
99e904c1 PK	550	int i , j;
99e904c1 PK	551
8c487539 PJ	552	#ifdef CONFIG_ARCH_LX2160A
	553	for (i = XFI1, j = 1; i <= XFI14; i++, j++)
	554	xfi_dpmac[i] = j;
	555
	556	for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
	557	sgmii_dpmac[i] = j;
	558
	559	for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
	560	a25gaui_dpmac[i] = j;
	561
	562	for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
	563	xlaui_dpmac[i] = j;
	564
	565	for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
	566	caui2_dpmac[i] = j;
	567
	568	for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
	569	caui4_dpmac[i] = j;
	570	#else
99e904c1 PK	571	for (i = XFI1, j = 1; i <= XFI8; i++, j++)
	572	xfi_dpmac[i] = j;
	573
	574	for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
	575	sgmii_dpmac[i] = j;
	576	#endif
8c487539	577	#endif
99e904c1	578
31d34c6c ML	579	#ifdef CONFIG_SYS_FSL_SRDS_1
	580	serdes_init(FSL_SRDS_1,
	581	CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
7b45b383 PK	582	FSL_CHASSIS3_SRDS1_REGSR,
	583	FSL_CHASSIS3_SRDS1_PRTCL_MASK,
	584	FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
31d34c6c ML	585	serdes1_prtcl_map);
	586	#endif
	587	#ifdef CONFIG_SYS_FSL_SRDS_2
	588	serdes_init(FSL_SRDS_2,
	589	CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
7b45b383 PK	590	FSL_CHASSIS3_SRDS2_REGSR,
	591	FSL_CHASSIS3_SRDS2_PRTCL_MASK,
	592	FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
31d34c6c ML	593	serdes2_prtcl_map);
31d34c6c ML	594	#endif
6252faa0 PJ	595	#ifdef CONFIG_SYS_NXP_SRDS_3
	596	serdes_init(NXP_SRDS_3,
	597	CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
	598	FSL_CHASSIS3_SRDS3_REGSR,
	599	FSL_CHASSIS3_SRDS3_PRTCL_MASK,
	600	FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
	601	serdes3_prtcl_map);
	602	#endif
31d34c6c	603	}
0d9d557d AM	604
	605	int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
	606	{
	607	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
	608	char scfg[16], snum[16];
	609	int cfgr = 0;
	610	u32 cfg;
	611
	612	cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
	613	cfg >>= sd_prctl_shift;
	614	cfg = serdes_get_number(sd, cfg);
	615
	616	#if defined(SRDS_BITS_PER_LANE)
	617	/*
	618	* reverse lanes, lane 0 should be printed first so it must be moved to
	619	* high order bits.
	620	* For example bb58 should read 85bb, lane 0 being protocol 8.
	621	* This only applies to SoCs that define SRDS_BITS_PER_LANE and have
	622	* independent per-lane protocol configuration, at this time LS1028A and
	623	* LS1088A. LS2 and LX2 SoCs encode the full protocol mix across all
	624	* lanes as a single value.
	625	*/
	626	for (int i = 0; i < SRDS_MAX_LANES; i++) {
	627	int tmp;
	628
	629	tmp = cfg >> (i * SRDS_BITS_PER_LANE);
	630	tmp &= GENMASK(SRDS_BITS_PER_LANE - 1, 0);
	631	tmp <<= (SRDS_MAX_LANES - i - 1) * SRDS_BITS_PER_LANE;
	632	cfgr \|= tmp;
	633	}
	634	#endif /* SRDS_BITS_PER_LANE */
	635
	636	snprintf(snum, 16, "serdes%d", sd);
	637	snprintf(scfg, 16, "%x", cfgr);
	638	env_set(snum, scfg);
	639
	640	return 0;
	641	}
	642
	643	int serdes_misc_init(void)
	644	{
	645	#ifdef CONFIG_SYS_FSL_SRDS_1
	646	serdes_set_env(FSL_SRDS_1, FSL_CHASSIS3_SRDS1_REGSR,
	647	FSL_CHASSIS3_SRDS1_PRTCL_MASK,
	648	FSL_CHASSIS3_SRDS1_PRTCL_SHIFT);
	649	#endif
	650	#ifdef CONFIG_SYS_FSL_SRDS_2
	651	serdes_set_env(FSL_SRDS_2, FSL_CHASSIS3_SRDS2_REGSR,
	652	FSL_CHASSIS3_SRDS2_PRTCL_MASK,
	653	FSL_CHASSIS3_SRDS2_PRTCL_SHIFT);
	654	#endif
	655	#ifdef CONFIG_SYS_NXP_SRDS_3
	656	serdes_set_env(NXP_SRDS_3, FSL_CHASSIS3_SRDS3_REGSR,
	657	FSL_CHASSIS3_SRDS3_PRTCL_MASK,
	658	FSL_CHASSIS3_SRDS3_PRTCL_SHIFT);
	659	#endif
	660
	661	return 0;
	662	}