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ca831f49 SG |
1 | /* |
2 | * Copyright (c) 2015 Google, Inc | |
3 | * Written by Simon Glass <[email protected]> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #ifndef __pch_h | |
9 | #define __pch_h | |
10 | ||
1ff4f321 SG |
11 | #define PCH_RCBA 0xf0 |
12 | ||
13 | #define BIOS_CTRL_BIOSWE BIT(0) | |
14 | ||
ca831f49 SG |
15 | /* Operations for the Platform Controller Hub */ |
16 | struct pch_ops { | |
17 | /** | |
3e389d8b | 18 | * get_spi_base() - get the address of SPI base |
ca831f49 SG |
19 | * |
20 | * @dev: PCH device to check | |
21 | * @sbasep: Returns address of SPI base if available, else 0 | |
22 | * @return 0 if OK, -ve on error (e.g. there is no SPI base) | |
23 | */ | |
3e389d8b | 24 | int (*get_spi_base)(struct udevice *dev, ulong *sbasep); |
ca831f49 | 25 | |
ca831f49 SG |
26 | /** |
27 | * set_spi_protect() - set whether SPI flash is protected or not | |
28 | * | |
29 | * @dev: PCH device to adjust | |
30 | * @protect: true to protect, false to unprotect | |
31 | * | |
32 | * @return 0 on success, -ENOSYS if not implemented | |
33 | */ | |
34 | int (*set_spi_protect)(struct udevice *dev, bool protect); | |
384980c6 BM |
35 | |
36 | /** | |
37 | * get_gpio_base() - get the address of GPIO base | |
38 | * | |
39 | * @dev: PCH device to check | |
40 | * @gbasep: Returns address of GPIO base if available, else 0 | |
41 | * @return 0 if OK, -ve on error (e.g. there is no GPIO base) | |
42 | */ | |
43 | int (*get_gpio_base)(struct udevice *dev, u32 *gbasep); | |
79d4eb62 BM |
44 | |
45 | /** | |
46 | * get_io_base() - get the address of IO base | |
47 | * | |
48 | * @dev: PCH device to check | |
49 | * @iobasep: Returns address of IO base if available, else 0 | |
50 | * @return 0 if OK, -ve on error (e.g. there is no IO base) | |
51 | */ | |
52 | int (*get_io_base)(struct udevice *dev, u32 *iobasep); | |
ca831f49 SG |
53 | }; |
54 | ||
55 | #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) | |
56 | ||
57 | /** | |
3e389d8b | 58 | * pch_get_spi_base() - get the address of SPI base |
ca831f49 SG |
59 | * |
60 | * @dev: PCH device to check | |
61 | * @sbasep: Returns address of SPI base if available, else 0 | |
62 | * @return 0 if OK, -ve on error (e.g. there is no SPI base) | |
63 | */ | |
3e389d8b | 64 | int pch_get_spi_base(struct udevice *dev, ulong *sbasep); |
ca831f49 | 65 | |
ca831f49 SG |
66 | /** |
67 | * set_spi_protect() - set whether SPI flash is protected or not | |
68 | * | |
69 | * @dev: PCH device to adjust | |
70 | * @protect: true to protect, false to unprotect | |
71 | * | |
72 | * @return 0 on success, -ENOSYS if not implemented | |
73 | */ | |
74 | int pch_set_spi_protect(struct udevice *dev, bool protect); | |
75 | ||
384980c6 BM |
76 | /** |
77 | * pch_get_gpio_base() - get the address of GPIO base | |
78 | * | |
79 | * @dev: PCH device to check | |
80 | * @gbasep: Returns address of GPIO base if available, else 0 | |
81 | * @return 0 if OK, -ve on error (e.g. there is no GPIO base) | |
82 | */ | |
83 | int pch_get_gpio_base(struct udevice *dev, u32 *gbasep); | |
84 | ||
79d4eb62 BM |
85 | /** |
86 | * pch_get_io_base() - get the address of IO base | |
87 | * | |
88 | * @dev: PCH device to check | |
89 | * @iobasep: Returns address of IO base if available, else 0 | |
90 | * @return 0 if OK, -ve on error (e.g. there is no IO base) | |
91 | */ | |
92 | int pch_get_io_base(struct udevice *dev, u32 *iobasep); | |
93 | ||
ca831f49 | 94 | #endif |