[J-u-boot.git] / drivers / ne2000.h

/*
Ported to U-Boot  by Christian Pellegrin <[email protected]>

Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.


==========================================================================

      dev/dp83902a.h

      National Semiconductor DP83902a ethernet chip

==========================================================================
####ECOSGPLCOPYRIGHTBEGIN####
 -------------------------------------------
 This file is part of eCos, the Embedded Configurable Operating System.
 Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

 eCos is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free
 Software Foundation; either version 2 or (at your option) any later version.

 eCos is distributed in the hope that it will be useful, but WITHOUT ANY
 WARRANTY; without even the implied warranty of MERCHANTABILITY or
 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 for more details.

 You should have received a copy of the GNU General Public License along
 with eCos; if not, write to the Free Software Foundation, Inc.,
 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

 As a special exception, if other files instantiate templates or use macros
 or inline functions from this file, or you compile this file and link it
 with other works to produce a work based on this file, this file does not
 by itself cause the resulting work to be covered by the GNU General Public
 License. However the source code for this file must still be made available
 in accordance with section (3) of the GNU General Public License.

 This exception does not invalidate any other reasons why a work based on
 this file might be covered by the GNU General Public License.

 Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
 at http://sources.redhat.com/ecos/ecos-license/ */
 -------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####

 -------------------------------------------

 Portions of this software may have been derived from OpenBSD or other sources,
 and are covered by the appropriate copyright disclaimers included herein.

 -------------------------------------------

####BSDCOPYRIGHTEND####
==========================================================================
#####DESCRIPTIONBEGIN####

 Author(s):    gthomas
 Contributors: gthomas, jskov
 Date:         2001-06-13
 Purpose:
 Description:

####DESCRIPTIONEND####

==========================================================================

*/

/*
 ------------------------------------------------------------------------
 Macros for accessing DP registers
 These can be overridden by the platform header
*/

#define DP_IN(_b_, _o_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)

#define DP_IN_DATA(_b_, _d_)  (_d_) = *( (volatile unsigned char *) ((_b_)))
#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)


/* here is all the data */

#define cyg_uint8 unsigned char
#define cyg_uint16 unsigned short
#define bool int

#define false 0
#define true 1

#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)

typedef struct dp83902a_priv_data {
    cyg_uint8* base;
    cyg_uint8* data;
    cyg_uint8* reset;
    int tx_next;           /* First free Tx page */
    int tx_int;            /* Expecting interrupt from this buffer */
    int rx_next;           /* First free Rx page */
    int tx1, tx2;          /* Page numbers for Tx buffers */
    unsigned long tx1_key, tx2_key;   /* Used to ack when packet sent */
    int tx1_len, tx2_len;
    bool tx_started, running, hardwired_esa;
    cyg_uint8 esa[6];
    void* plf_priv;

    /* Buffer allocation */
    int tx_buf1, tx_buf2;
    int rx_buf_start, rx_buf_end;
} dp83902a_priv_data_t;

/*
 ------------------------------------------------------------------------
 Some forward declarations
*/
static void dp83902a_poll(void);

/* ------------------------------------------------------------------------ */
/* Register offsets */

#define DP_CR          0x00
#define DP_CLDA0       0x01
#define DP_PSTART      0x01             /* write */
#define DP_CLDA1       0x02
#define DP_PSTOP       0x02             /* write */
#define DP_BNDRY       0x03
#define DP_TSR         0x04
#define DP_TPSR        0x04             /* write */
#define DP_NCR         0x05
#define DP_TBCL        0x05             /* write */
#define DP_FIFO        0x06
#define DP_TBCH        0x06             /* write */
#define DP_ISR         0x07
#define DP_CRDA0       0x08
#define DP_RSAL        0x08             /* write */
#define DP_CRDA1       0x09
#define DP_RSAH        0x09             /* write */
#define DP_RBCL        0x0a             /* write */
#define DP_RBCH        0x0b             /* write */
#define DP_RSR         0x0c
#define DP_RCR         0x0c             /* write */
#define DP_FER         0x0d
#define DP_TCR         0x0d             /* write */
#define DP_CER         0x0e
#define DP_DCR         0x0e             /* write */
#define DP_MISSED      0x0f
#define DP_IMR         0x0f             /* write */
#define DP_DATAPORT    0x10             /* "eprom" data port */

#define DP_P1_CR       0x00
#define DP_P1_PAR0     0x01
#define DP_P1_PAR1     0x02
#define DP_P1_PAR2     0x03
#define DP_P1_PAR3     0x04
#define DP_P1_PAR4     0x05
#define DP_P1_PAR5     0x06
#define DP_P1_CURP     0x07
#define DP_P1_MAR0     0x08
#define DP_P1_MAR1     0x09
#define DP_P1_MAR2     0x0a
#define DP_P1_MAR3     0x0b
#define DP_P1_MAR4     0x0c
#define DP_P1_MAR5     0x0d
#define DP_P1_MAR6     0x0e
#define DP_P1_MAR7     0x0f

#define DP_P2_CR       0x00
#define DP_P2_PSTART   0x01
#define DP_P2_CLDA0    0x01             /* write */
#define DP_P2_PSTOP    0x02
#define DP_P2_CLDA1    0x02             /* write */
#define DP_P2_RNPP     0x03
#define DP_P2_TPSR     0x04
#define DP_P2_LNPP     0x05
#define DP_P2_ACH      0x06
#define DP_P2_ACL      0x07
#define DP_P2_RCR      0x0c
#define DP_P2_TCR      0x0d
#define DP_P2_DCR      0x0e
#define DP_P2_IMR      0x0f

/* Command register - common to all pages */

#define DP_CR_STOP    0x01   /* Stop: software reset */
#define DP_CR_START   0x02   /* Start: initialize device */
#define DP_CR_TXPKT   0x04   /* Transmit packet */
#define DP_CR_RDMA    0x08   /* Read DMA  (recv data from device) */
#define DP_CR_WDMA    0x10   /* Write DMA (send data to device) */
#define DP_CR_SEND    0x18   /* Send packet */
#define DP_CR_NODMA   0x20   /* Remote (or no) DMA */
#define DP_CR_PAGE0   0x00   /* Page select */
#define DP_CR_PAGE1   0x40
#define DP_CR_PAGE2   0x80
#define DP_CR_PAGEMSK 0x3F   /* Used to mask out page bits */

/* Data configuration register */

#define DP_DCR_WTS    0x01   /* 1=16 bit word transfers */
#define DP_DCR_BOS    0x02   /* 1=Little Endian */
#define DP_DCR_LAS    0x04   /* 1=Single 32 bit DMA mode */
#define DP_DCR_LS     0x08   /* 1=normal mode, 0=loopback */
#define DP_DCR_ARM    0x10   /* 0=no send command (program I/O) */
#define DP_DCR_FIFO_1 0x00   /* FIFO threshold */
#define DP_DCR_FIFO_2 0x20
#define DP_DCR_FIFO_4 0x40
#define DP_DCR_FIFO_6 0x60

#define DP_DCR_INIT   (DP_DCR_LS|DP_DCR_FIFO_4)

/* Interrupt status register */

#define DP_ISR_RxP    0x01   /* Packet received */
#define DP_ISR_TxP    0x02   /* Packet transmitted */
#define DP_ISR_RxE    0x04   /* Receive error */
#define DP_ISR_TxE    0x08   /* Transmit error */
#define DP_ISR_OFLW   0x10   /* Receive overflow */
#define DP_ISR_CNT    0x20   /* Tally counters need emptying */
#define DP_ISR_RDC    0x40   /* Remote DMA complete */
#define DP_ISR_RESET  0x80   /* Device has reset (shutdown, error) */

/* Interrupt mask register */

#define DP_IMR_RxP    0x01   /* Packet received */
#define DP_IMR_TxP    0x02   /* Packet transmitted */
#define DP_IMR_RxE    0x04   /* Receive error */
#define DP_IMR_TxE    0x08   /* Transmit error */
#define DP_IMR_OFLW   0x10   /* Receive overflow */
#define DP_IMR_CNT    0x20   /* Tall counters need emptying */
#define DP_IMR_RDC    0x40   /* Remote DMA complete */

#define DP_IMR_All    0x3F   /* Everything but remote DMA */

/* Receiver control register */

#define DP_RCR_SEP    0x01   /* Save bad(error) packets */
#define DP_RCR_AR     0x02   /* Accept runt packets */
#define DP_RCR_AB     0x04   /* Accept broadcast packets */
#define DP_RCR_AM     0x08   /* Accept multicast packets */
#define DP_RCR_PROM   0x10   /* Promiscuous mode */
#define DP_RCR_MON    0x20   /* Monitor mode - 1=accept no packets */

/* Receiver status register */

#define DP_RSR_RxP    0x01   /* Packet received */
#define DP_RSR_CRC    0x02   /* CRC error */
#define DP_RSR_FRAME  0x04   /* Framing error */
#define DP_RSR_FO     0x08   /* FIFO overrun */
#define DP_RSR_MISS   0x10   /* Missed packet */
#define DP_RSR_PHY    0x20   /* 0=pad match, 1=mad match */
#define DP_RSR_DIS    0x40   /* Receiver disabled */
#define DP_RSR_DFR    0x80   /* Receiver processing deferred */

/* Transmitter control register */

#define DP_TCR_NOCRC  0x01   /* 1=inhibit CRC */
#define DP_TCR_NORMAL 0x00   /* Normal transmitter operation */
#define DP_TCR_LOCAL  0x02   /* Internal NIC loopback */
#define DP_TCR_INLOOP 0x04   /* Full internal loopback */
#define DP_TCR_OUTLOOP 0x08  /* External loopback */
#define DP_TCR_ATD    0x10   /* Auto transmit disable */
#define DP_TCR_OFFSET 0x20   /* Collision offset adjust */

/* Transmit status register */

#define DP_TSR_TxP    0x01   /* Packet transmitted */
#define DP_TSR_COL    0x04   /* Collision (at least one) */
#define DP_TSR_ABT    0x08   /* Aborted because of too many collisions */
#define DP_TSR_CRS    0x10   /* Lost carrier */
#define DP_TSR_FU     0x20   /* FIFO underrun */
#define DP_TSR_CDH    0x40   /* Collision Detect Heartbeat */
#define DP_TSR_OWC    0x80   /* Collision outside normal window */

#define IEEE_8023_MAX_FRAME         1518    /* Largest possible ethernet frame */
#define IEEE_8023_MIN_FRAME           64    /* Smallest possible ethernet frame */
Commit	Line	Data
8ed96046 WD	1	/*
	2	Ported to U-Boot by Christian Pellegrin <[email protected]>
	3
	4	Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
	5	eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
	6	are GPL, so this is, of course, GPL.
	7
	8
	9	==========================================================================
	10
	11	dev/dp83902a.h
	12
	13	National Semiconductor DP83902a ethernet chip
	14
	15	==========================================================================
	16	####ECOSGPLCOPYRIGHTBEGIN####
	17	-------------------------------------------
	18	This file is part of eCos, the Embedded Configurable Operating System.
	19	Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
	20
	21	eCos is free software; you can redistribute it and/or modify it under
	22	the terms of the GNU General Public License as published by the Free
	23	Software Foundation; either version 2 or (at your option) any later version.
	24
	25	eCos is distributed in the hope that it will be useful, but WITHOUT ANY
	26	WARRANTY; without even the implied warranty of MERCHANTABILITY or
	27	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	28	for more details.
	29
	30	You should have received a copy of the GNU General Public License along
	31	with eCos; if not, write to the Free Software Foundation, Inc.,
	32	59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
	33
	34	As a special exception, if other files instantiate templates or use macros
	35	or inline functions from this file, or you compile this file and link it
	36	with other works to produce a work based on this file, this file does not
	37	by itself cause the resulting work to be covered by the GNU General Public
	38	License. However the source code for this file must still be made available
	39	in accordance with section (3) of the GNU General Public License.
	40
	41	This exception does not invalidate any other reasons why a work based on
	42	this file might be covered by the GNU General Public License.
	43
	44	Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
	45	at http://sources.redhat.com/ecos/ecos-license/ */
	46	-------------------------------------------
	47	####ECOSGPLCOPYRIGHTEND####
	48	####BSDCOPYRIGHTBEGIN####
	49
	50	-------------------------------------------
	51
	52	Portions of this software may have been derived from OpenBSD or other sources,
	53	and are covered by the appropriate copyright disclaimers included herein.
	54
	55	-------------------------------------------
	56
	57	####BSDCOPYRIGHTEND####
	58	==========================================================================
	59	#####DESCRIPTIONBEGIN####
	60
	61	Author(s): gthomas
	62	Contributors: gthomas, jskov
	63	Date: 2001-06-13
	64	Purpose:
65	Description:
66
67	####DESCRIPTIONEND####
68
69	==========================================================================
70
71	*/
72
73	/*
74	------------------------------------------------------------------------
75	Macros for accessing DP registers
76	These can be overridden by the platform header
77	*/
78
79	#define DP_IN(_b_, _o_, _d_) (_d_) = ( (volatile unsigned char ) ((_b_)+(_o_)))
80	#define DP_OUT(_b_, _o_, _d_) ( (volatile unsigned char ) ((_b_)+(_o_))) = (_d_)
81
82	#define DP_IN_DATA(_b_, _d_) (_d_) = ( (volatile unsigned char ) ((_b_)))
83	#define DP_OUT_DATA(_b_, _d_) ( (volatile unsigned char ) ((_b_))) = (_d_)
84
85
86	/* here is all the data */
87
88	#define cyg_uint8 unsigned char
89	#define cyg_uint16 unsigned short
90	#define bool int
91
92	#define false 0
93	#define true 1
94
95	#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
96	#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
97
98	typedef struct dp83902a_priv_data {
99	cyg_uint8* base;
100	cyg_uint8* data;
101	cyg_uint8* reset;
102	int tx_next; /* First free Tx page */
103	int tx_int; /* Expecting interrupt from this buffer */
104	int rx_next; /* First free Rx page */
105	int tx1, tx2; /* Page numbers for Tx buffers */
106	unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */
107	int tx1_len, tx2_len;
108	bool tx_started, running, hardwired_esa;
109	cyg_uint8 esa[6];
110	void* plf_priv;
111
112	/* Buffer allocation */
113	int tx_buf1, tx_buf2;
114	int rx_buf_start, rx_buf_end;
115	} dp83902a_priv_data_t;
116
117	/*
118	------------------------------------------------------------------------
119	Some forward declarations
120	*/
121	static void dp83902a_poll(void);
122
123	/* ------------------------------------------------------------------------ */
124	/* Register offsets */
125
126	#define DP_CR 0x00
127	#define DP_CLDA0 0x01
128	#define DP_PSTART 0x01 /* write */
129	#define DP_CLDA1 0x02
130	#define DP_PSTOP 0x02 /* write */
131	#define DP_BNDRY 0x03
132	#define DP_TSR 0x04
133	#define DP_TPSR 0x04 /* write */
134	#define DP_NCR 0x05
135	#define DP_TBCL 0x05 /* write */
136	#define DP_FIFO 0x06
137	#define DP_TBCH 0x06 /* write */
138	#define DP_ISR 0x07
139	#define DP_CRDA0 0x08
140	#define DP_RSAL 0x08 /* write */
141	#define DP_CRDA1 0x09
142	#define DP_RSAH 0x09 /* write */
143	#define DP_RBCL 0x0a /* write */
144	#define DP_RBCH 0x0b /* write */
145	#define DP_RSR 0x0c
146	#define DP_RCR 0x0c /* write */
147	#define DP_FER 0x0d
148	#define DP_TCR 0x0d /* write */
149	#define DP_CER 0x0e
150	#define DP_DCR 0x0e /* write */
151	#define DP_MISSED 0x0f
152	#define DP_IMR 0x0f /* write */
153	#define DP_DATAPORT 0x10 /* "eprom" data port */
154
155	#define DP_P1_CR 0x00
156	#define DP_P1_PAR0 0x01
157	#define DP_P1_PAR1 0x02
158	#define DP_P1_PAR2 0x03
159	#define DP_P1_PAR3 0x04
160	#define DP_P1_PAR4 0x05
161	#define DP_P1_PAR5 0x06
162	#define DP_P1_CURP 0x07
163	#define DP_P1_MAR0 0x08
164	#define DP_P1_MAR1 0x09
165	#define DP_P1_MAR2 0x0a
166	#define DP_P1_MAR3 0x0b
167	#define DP_P1_MAR4 0x0c
168	#define DP_P1_MAR5 0x0d
169	#define DP_P1_MAR6 0x0e
170	#define DP_P1_MAR7 0x0f
171
172	#define DP_P2_CR 0x00
173	#define DP_P2_PSTART 0x01
174	#define DP_P2_CLDA0 0x01 /* write */
175	#define DP_P2_PSTOP 0x02
176	#define DP_P2_CLDA1 0x02 /* write */
177	#define DP_P2_RNPP 0x03
178	#define DP_P2_TPSR 0x04
179	#define DP_P2_LNPP 0x05
180	#define DP_P2_ACH 0x06
181	#define DP_P2_ACL 0x07
182	#define DP_P2_RCR 0x0c
183	#define DP_P2_TCR 0x0d
184	#define DP_P2_DCR 0x0e
185	#define DP_P2_IMR 0x0f
186
187	/* Command register - common to all pages */
188
189	#define DP_CR_STOP 0x01 /* Stop: software reset */
190	#define DP_CR_START 0x02 /* Start: initialize device */
191	#define DP_CR_TXPKT 0x04 /* Transmit packet */
192	#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
193	#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
194	#define DP_CR_SEND 0x18 /* Send packet */
195	#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
196	#define DP_CR_PAGE0 0x00 /* Page select */
197	#define DP_CR_PAGE1 0x40
198	#define DP_CR_PAGE2 0x80
199	#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
200
201	/* Data configuration register */
202
203	#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
204	#define DP_DCR_BOS 0x02 /* 1=Little Endian */
205	#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
206	#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
207	#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
208	#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
209	#define DP_DCR_FIFO_2 0x20
210	#define DP_DCR_FIFO_4 0x40
211	#define DP_DCR_FIFO_6 0x60
212
213	#define DP_DCR_INIT (DP_DCR_LS\|DP_DCR_FIFO_4)
214
215	/* Interrupt status register */
216
217	#define DP_ISR_RxP 0x01 /* Packet received */
218	#define DP_ISR_TxP 0x02 /* Packet transmitted */
219	#define DP_ISR_RxE 0x04 /* Receive error */
220	#define DP_ISR_TxE 0x08 /* Transmit error */
221	#define DP_ISR_OFLW 0x10 /* Receive overflow */
222	#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
223	#define DP_ISR_RDC 0x40 /* Remote DMA complete */
224	#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
225
226	/* Interrupt mask register */
227
228	#define DP_IMR_RxP 0x01 /* Packet received */
229	#define DP_IMR_TxP 0x02 /* Packet transmitted */
230	#define DP_IMR_RxE 0x04 /* Receive error */
231	#define DP_IMR_TxE 0x08 /* Transmit error */
232	#define DP_IMR_OFLW 0x10 /* Receive overflow */
233	#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
234	#define DP_IMR_RDC 0x40 /* Remote DMA complete */
235
236	#define DP_IMR_All 0x3F /* Everything but remote DMA */
237
238	/* Receiver control register */
239
240	#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
241	#define DP_RCR_AR 0x02 /* Accept runt packets */
242	#define DP_RCR_AB 0x04 /* Accept broadcast packets */
243	#define DP_RCR_AM 0x08 /* Accept multicast packets */
244	#define DP_RCR_PROM 0x10 /* Promiscuous mode */
245	#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
246
247	/* Receiver status register */
248
249	#define DP_RSR_RxP 0x01 /* Packet received */
250	#define DP_RSR_CRC 0x02 /* CRC error */
251	#define DP_RSR_FRAME 0x04 /* Framing error */
252	#define DP_RSR_FO 0x08 /* FIFO overrun */
253	#define DP_RSR_MISS 0x10 /* Missed packet */
254	#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
255	#define DP_RSR_DIS 0x40 /* Receiver disabled */
256	#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
257
258	/* Transmitter control register */
259
260	#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
261	#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
262	#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
263	#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
264	#define DP_TCR_OUTLOOP 0x08 /* External loopback */
265	#define DP_TCR_ATD 0x10 /* Auto transmit disable */
266	#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
267
268	/* Transmit status register */
269
270	#define DP_TSR_TxP 0x01 /* Packet transmitted */
271	#define DP_TSR_COL 0x04 /* Collision (at least one) */
272	#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
273	#define DP_TSR_CRS 0x10 /* Lost carrier */
274	#define DP_TSR_FU 0x20 /* FIFO underrun */
275	#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
276	#define DP_TSR_OWC 0x80 /* Collision outside normal window */
277
278	#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
279	#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */