projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| bafcf2db | 1 | CONFIG_ARM=y |
| a2ac2b96 | 2 | CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y |
| f76750d1 | 3 | CONFIG_SYS_ARCH_TIMER=y |
| bafcf2db | 4 | CONFIG_ARCH_ROCKCHIP=y |
| 98463903 | 5 | CONFIG_TEXT_BASE=0x00000000 |
| 554e5514 | 6 | CONFIG_NR_DRAM_BANKS=1 |
| fcb5117d TR |
7 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 8 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 | |
| c960c0fd | 9 | CONFIG_SF_DEFAULT_SPEED=20000000 |
| 052170c6 | 10 | CONFIG_ENV_OFFSET=0x3F8000 |
| a78224c1 | 11 | CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3288-phycore-rdk" |
| c90e1893 | 12 | CONFIG_SYS_MONITOR_LEN=614400 |
| bafcf2db | 13 | CONFIG_ROCKCHIP_RK3288=y |
| ee14d29d | 14 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
| bafcf2db | 15 | CONFIG_TARGET_PHYCORE_RK3288=y |
| d168bcb6 | 16 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| fcb5117d | 17 | CONFIG_SPL_STACK=0xff718000 |
| 867e16ae | 18 | CONFIG_SPL_TEXT_BASE=0xff704000 |
| a78224c1 WE |
19 | CONFIG_SPL_STACK_R=y |
| 20 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 | |
| d8927020 TR |
21 | CONFIG_SYS_BOOTM_LEN=0x4000000 |
| 22 | CONFIG_SYS_LOAD_ADDR=0x800800 | |
| 358b6a20 TR |
23 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 24 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
| d46e86d2 | 25 | CONFIG_DEBUG_UART=y |
| 14421e87 | 26 | CONFIG_LTO=y |
| 48f6232e | 27 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| 37304aaf | 28 | CONFIG_USE_PREBOOT=y |
| 0817daa7 | 29 | CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" |
| bafcf2db WE |
30 | CONFIG_SILENT_CONSOLE=y |
| 31 | CONFIG_CONSOLE_MUX=y | |
| 78eba69d | 32 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| ca8a329a | 33 | CONFIG_SPL_PAD_TO=0x7f8000 |
| 9b5f9aeb | 34 | CONFIG_SPL_NO_BSS_LIMIT=y |
| f113d7d3 | 35 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 88663126 | 36 | CONFIG_CMD_GPIO=y |
| bafcf2db | 37 | CONFIG_CMD_GPT=y |
| 88663126 | 38 | CONFIG_CMD_I2C=y |
| bafcf2db | 39 | CONFIG_CMD_MMC=y |
| bafcf2db | 40 | CONFIG_CMD_SPI=y |
| bafcf2db | 41 | CONFIG_CMD_USB=y |
| a186e8aa | 42 | CONFIG_CMD_USB_MASS_STORAGE=y |
| bafcf2db WE |
43 | # CONFIG_CMD_SETEXPR is not set |
| 44 | CONFIG_CMD_CACHE=y | |
| 45 | CONFIG_CMD_TIME=y | |
| 46 | CONFIG_CMD_PMIC=y | |
| 47 | CONFIG_CMD_REGULATOR=y | |
| 48 | # CONFIG_SPL_DOS_PARTITION is not set | |
| bafcf2db | 49 | # CONFIG_SPL_EFI_PARTITION is not set |
| bafcf2db | 50 | CONFIG_SPL_OF_CONTROL=y |
| a78224c1 | 51 | CONFIG_OF_UPSTREAM=y |
| bafcf2db | 52 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 5dc4dfd2 | 53 | CONFIG_ENV_IS_IN_MMC=y |
| 8d8ee47e | 54 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 7d080773 | 55 | CONFIG_SYS_MMC_ENV_DEV=1 |
| bafcf2db WE |
56 | CONFIG_REGMAP=y |
| 57 | CONFIG_SPL_REGMAP=y | |
| 58 | CONFIG_SYSCON=y | |
| 59 | CONFIG_SPL_SYSCON=y | |
| 60 | # CONFIG_SPL_SIMPLE_BUS is not set | |
| 61 | CONFIG_CLK=y | |
| 62 | CONFIG_SPL_CLK=y | |
| 65c96757 | 63 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y |
| bafcf2db WE |
64 | CONFIG_ROCKCHIP_GPIO=y |
| 65 | CONFIG_SYS_I2C_ROCKCHIP=y | |
| 32191a39 WE |
66 | CONFIG_MISC=y |
| 67 | CONFIG_I2C_EEPROM=y | |
| bafcf2db WE |
68 | CONFIG_MMC_DW=y |
| 69 | CONFIG_MMC_DW_ROCKCHIP=y | |
| bafcf2db WE |
70 | CONFIG_ETH_DESIGNWARE=y |
| 71 | CONFIG_GMAC_ROCKCHIP=y | |
| 72 | CONFIG_PINCTRL=y | |
| 73 | CONFIG_SPL_PINCTRL=y | |
| bafcf2db WE |
74 | CONFIG_DM_PMIC=y |
| 75 | CONFIG_PMIC_RK8XX=y | |
| 76 | CONFIG_DM_REGULATOR_FIXED=y | |
| 77 | CONFIG_REGULATOR_RK8XX=y | |
| 78 | CONFIG_PWM_ROCKCHIP=y | |
| 79 | CONFIG_RAM=y | |
| 80 | CONFIG_SPL_RAM=y | |
| bafcf2db | 81 | CONFIG_DEBUG_UART_SHIFT=2 |
| 9591b635 | 82 | CONFIG_SYS_NS16550_MEM32=y |
| bafcf2db WE |
83 | CONFIG_SYSRESET=y |
| 84 | CONFIG_USB=y | |
| c3d098e7 | 85 | CONFIG_USB_DWC2=y |
| 7c8f00e4 | 86 | CONFIG_ROCKCHIP_USB2_PHY=y |
| ae358449 | 87 | CONFIG_USB_HOST_ETHER=y |
| f58ad98a CP |
88 | CONFIG_USB_ETHER_ASIX=y |
| 89 | CONFIG_USB_ETHER_SMSC95XX=y | |
| df59b7d2 TR |
90 | CONFIG_USB_GADGET=y |
| 91 | CONFIG_USB_GADGET_DWC2_OTG=y | |
| bafcf2db WE |
92 | CONFIG_CMD_DHRYSTONE=y |
| 93 | CONFIG_ERRNO_STR=y |