]>
Commit | Line | Data |
---|---|---|
7666cccf II |
1 | CONFIG_ARM=y |
2 | CONFIG_ARCH_IMX8M=y | |
98463903 | 3 | CONFIG_TEXT_BASE=0x40200000 |
9802154a | 4 | CONFIG_SYS_MALLOC_LEN=0x600000 |
83061dbd | 5 | CONFIG_SPL_GPIO=y |
7666cccf II |
6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
8 | CONFIG_ENV_SIZE=0x1000 | |
9 | CONFIG_ENV_OFFSET=0x400000 | |
10 | CONFIG_SYS_I2C_MXC_I2C1=y | |
11 | CONFIG_SYS_I2C_MXC_I2C2=y | |
12 | CONFIG_SYS_I2C_MXC_I2C3=y | |
13 | CONFIG_DM_GPIO=y | |
2bba7807 | 14 | CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm" |
7666cccf | 15 | CONFIG_TARGET_IMX8MQ_CM=y |
c90e1893 | 16 | CONFIG_SYS_MONITOR_LEN=524288 |
103c5f18 | 17 | CONFIG_SPL_MMC=y |
2a736066 | 18 | CONFIG_SPL_SERIAL=y |
fcb5117d | 19 | CONFIG_SPL_STACK=0x187ff0 |
867e16ae | 20 | CONFIG_SPL_TEXT_BASE=0x7E1000 |
18e791c4 TR |
21 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
22 | CONFIG_SPL_BSS_START_ADDR=0x180000 | |
23 | CONFIG_SPL_BSS_MAX_SIZE=0x2000 | |
d8927020 TR |
24 | CONFIG_SYS_BOOTM_LEN=0x2000000 |
25 | CONFIG_SYS_LOAD_ADDR=0x40480000 | |
7666cccf | 26 | CONFIG_SPL=y |
b70b2bed | 27 | CONFIG_IMX_BOOTAUX=y |
a8c281d4 | 28 | CONFIG_REMAKE_ELF=y |
7666cccf II |
29 | CONFIG_FIT=y |
30 | CONFIG_SPL_FIT_PRINT=y | |
31 | CONFIG_SPL_LOAD_FIT=y | |
c358af81 | 32 | CONFIG_DISTRO_DEFAULTS=y |
ec6f06bd | 33 | CONFIG_OF_SYSTEM_SETUP=y |
42fb448a | 34 | CONFIG_SYS_PBSIZE=1050 |
7666cccf | 35 | CONFIG_BOARD_LATE_INIT=y |
ca8a329a | 36 | CONFIG_SPL_MAX_SIZE=0x1f000 |
7666cccf | 37 | CONFIG_SPL_BOARD_INIT=y |
f113d7d3 | 38 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
82e26e0d SG |
39 | CONFIG_SPL_SYS_MALLOC=y |
40 | CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y | |
41 | CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 | |
42 | CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 | |
2a00d73d | 43 | CONFIG_SPL_SYS_MMCSD_RAW_MODE=y |
f76750d1 | 44 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 |
975e7cf3 | 45 | CONFIG_SPL_I2C=y |
ba6d575e | 46 | CONFIG_SYS_PROMPT="u-boot=> " |
7666cccf II |
47 | CONFIG_CMD_FUSE=y |
48 | CONFIG_CMD_GPIO=y | |
49 | CONFIG_CMD_I2C=y | |
50 | CONFIG_CMD_MMC=y | |
51 | CONFIG_CMD_CACHE=y | |
52 | CONFIG_CMD_REGULATOR=y | |
53 | CONFIG_CMD_EXT4_WRITE=y | |
54 | CONFIG_OF_CONTROL=y | |
55 | CONFIG_SPL_OF_CONTROL=y | |
56 | CONFIG_ENV_OVERWRITE=y | |
57 | CONFIG_ENV_IS_IN_MMC=y | |
58 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
59 | CONFIG_SYS_MMC_ENV_DEV=1 | |
60 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
0e14cdfa TR |
61 | CONFIG_USE_ETHPRIME=y |
62 | CONFIG_ETHPRIME="FEC" | |
7666cccf II |
63 | CONFIG_NET_RANDOM_ETHADDR=y |
64 | CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 | |
65 | CONFIG_MXC_GPIO=y | |
66 | CONFIG_DM_I2C=y | |
55dabcc8 | 67 | CONFIG_SPL_SYS_I2C_LEGACY=y |
7666cccf II |
68 | CONFIG_SUPPORT_EMMC_BOOT=y |
69 | CONFIG_MMC_IO_VOLTAGE=y | |
70 | CONFIG_MMC_UHS_SUPPORT=y | |
71 | CONFIG_MMC_HS400_ES_SUPPORT=y | |
72 | CONFIG_MMC_HS400_SUPPORT=y | |
73 | CONFIG_FSL_USDHC=y | |
74 | CONFIG_MTD=y | |
75 | CONFIG_DM_MTD=y | |
76 | CONFIG_DM_SPI_FLASH=y | |
77 | CONFIG_SPI_FLASH_MACRONIX=y | |
78 | CONFIG_SPI_FLASH_SPANSION=y | |
79 | CONFIG_SPI_FLASH_STMICRO=y | |
80 | CONFIG_PHYLIB=y | |
81 | CONFIG_PHY_ATHEROS=y | |
7666cccf II |
82 | CONFIG_PHY_GIGE=y |
83 | CONFIG_FEC_MXC=y | |
84 | CONFIG_MII=y | |
85 | CONFIG_PINCTRL=y | |
86 | CONFIG_PINCTRL_IMX8M=y | |
87 | CONFIG_DM_PMIC=y | |
88 | CONFIG_DM_PMIC_BD71837=y | |
89 | CONFIG_DM_REGULATOR=y | |
90 | CONFIG_DM_REGULATOR_FIXED=y | |
91 | CONFIG_DM_REGULATOR_GPIO=y | |
23df340f | 92 | CONFIG_DM_SERIAL=y |
7666cccf II |
93 | CONFIG_MXC_UART=y |
94 | CONFIG_SPI=y | |
95 | CONFIG_DM_SPI=y | |
96 | CONFIG_FSL_QSPI=y | |
97 | CONFIG_DM_THERMAL=y | |
98 | CONFIG_IMX_WATCHDOG=y | |
99 | CONFIG_WDT=y |