[J-u-boot.git] / doc / README.imx5

U-Boot for Freescale i.MX5x

This file contains information for the port of U-Boot to the Freescale
i.MX5x SoCs.

1. CONFIGURATION OPTIONS/SETTINGS
---------------------------------

1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
    This option should be enabled by all boards using the i.MX51 silicon
    version up until (including) 3.0 running at 800MHz.
    The PLL's in the i.MX51 processor can go out of lock due to a metastable
    condition in an analog flip-flop when used at high frequencies.
    This workaround implements an undocumented feature in the PLL (dither
    mode), which causes the effect of this failure to be much lower (in terms
    of frequency deviation), avoiding system failure, or at least decreasing
    the likelihood of system failure.

1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
    reference designs.
Commit	Line	Data
9db1bfa1 DJ	1	U-Boot for Freescale i.MX5x
	2
	3	This file contains information for the port of U-Boot to the Freescale
	4	i.MX5x SoCs.
	5
	6	1. CONFIGURATION OPTIONS/SETTINGS
	7	---------------------------------
	8
	9	1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
	10	This option should be enabled by all boards using the i.MX51 silicon
	11	version up until (including) 3.0 running at 800MHz.
	12	The PLL's in the i.MX51 processor can go out of lock due to a metastable
	13	condition in an analog flip-flop when used at high frequencies.
	14	This workaround implements an undocumented feature in the PLL (dither
	15	mode), which causes the effect of this failure to be much lower (in terms
	16	of frequency deviation), avoiding system failure, or at least decreasing
	17	the likelihood of system failure.
39e85761 BT	18
	19	1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
	20	This option should be enabled for boards having a SYS_ON_OFF_CTL signal
	21	connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
	22	reference designs.