[J-u-boot.git] / include / linux / mtd / spi-nor.h

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 * Synced from Linux v4.19
 */

#ifndef __LINUX_MTD_SPI_NOR_H
#define __LINUX_MTD_SPI_NOR_H

#include <linux/bitops.h>
#include <linux/mtd/cfi.h>
#include <linux/mtd/mtd.h>

/*
 * Manufacturer IDs
 *
 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
 */
#define SNOR_MFR_ATMEL		CFI_MFR_ATMEL
#define SNOR_MFR_GIGADEVICE	0xc8
#define SNOR_MFR_INTEL		CFI_MFR_INTEL
#define SNOR_MFR_ST		CFI_MFR_ST /* ST Micro <--> Micron */
#define SNOR_MFR_MICRON		CFI_MFR_MICRON /* ST Micro <--> Micron */
#define SNOR_MFR_ISSI		CFI_MFR_PMC
#define SNOR_MFR_MACRONIX	CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION	CFI_MFR_AMD
#define SNOR_MFR_SST		CFI_MFR_SST
#define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */

/*
 * Note on opcode nomenclature: some opcodes have a format like
 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
 * of I/O lines used for the opcode, address, and data (respectively). The
 * FUNCTION has an optional suffix of '4', to represent an opcode which
 * requires a 4-byte (32-bit) address.
 */

/* Flash opcodes. */
#define SPINOR_OP_WREN		0x06	/* Write enable */
#define SPINOR_OP_RDSR		0x05	/* Read status register */
#define SPINOR_OP_WRSR		0x01	/* Write status register 1 byte */
#define SPINOR_OP_RDSR2		0x3f	/* Read status register 2 */
#define SPINOR_OP_WRSR2		0x3e	/* Write status register 2 */
#define SPINOR_OP_READ		0x03	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST	0x0b	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2	0x3b	/* Read data bytes (Dual Output SPI) */
#define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_READ_1_1_8	0x8b    /* Read data bytes (Octal Output SPI) */
#define SPINOR_OP_READ_1_8_8	0xcb    /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
#define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
#define SPINOR_OP_PP_1_1_8	0x82    /* Octal page program */
#define SPINOR_OP_PP_1_8_8	0xc2    /* Octal page program */
#define SPINOR_OP_BE_4K		0x20	/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC	0xd7	/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K	0x52	/* Erase 32KiB block */
#define SPINOR_OP_CHIP_ERASE	0xc7	/* Erase whole flash chip */
#define SPINOR_OP_SE		0xd8	/* Sector erase (usually 64KiB) */
#define SPINOR_OP_RDID		0x9f	/* Read JEDEC ID */
#define SPINOR_OP_RDSFDP	0x5a	/* Read SFDP */
#define SPINOR_OP_RDCR		0x35	/* Read configuration register */
#define SPINOR_OP_RDFSR		0x70	/* Read flag status register */
#define SPINOR_OP_CLFSR		0x50	/* Clear flag status register */
#define SPINOR_OP_RDEAR		0xc8	/* Read Extended Address Register */
#define SPINOR_OP_WREAR		0xc5	/* Write Extended Address Register */

/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
#define SPINOR_OP_READ_4B	0x13	/* Read data bytes (low frequency) */
#define SPINOR_OP_READ_FAST_4B	0x0c	/* Read data bytes (high frequency) */
#define SPINOR_OP_READ_1_1_2_4B	0x3c	/* Read data bytes (Dual Output SPI) */
#define SPINOR_OP_READ_1_2_2_4B	0xbc	/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B	0x6c	/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B	0xec	/* Read data bytes (Quad I/O SPI) */
#define SPINOR_OP_READ_1_1_8_4B	0x7c    /* Read data bytes (Octal Output SPI) */
#define SPINOR_OP_READ_1_8_8_4B	0xcc    /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B		0x12	/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B	0x34	/* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B	0x3e	/* Quad page program */
#define SPINOR_OP_PP_1_1_8_4B	0x84    /* Octal page program */
#define SPINOR_OP_PP_1_8_8_4B	0x8e    /* Octal page program */
#define SPINOR_OP_BE_4K_4B	0x21	/* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B	0x5c	/* Erase 32KiB block */
#define SPINOR_OP_SE_4B		0xdc	/* Sector erase (usually 64KiB) */

/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
#define SPINOR_OP_READ_1_1_1_DTR	0x0d
#define SPINOR_OP_READ_1_2_2_DTR	0xbd
#define SPINOR_OP_READ_1_4_4_DTR	0xed

#define SPINOR_OP_READ_1_1_1_DTR_4B	0x0e
#define SPINOR_OP_READ_1_2_2_DTR_4B	0xbe
#define SPINOR_OP_READ_1_4_4_DTR_4B	0xee

/* Used for SST flashes only. */
#define SPINOR_OP_BP		0x02	/* Byte program */
#define SPINOR_OP_WRDI		0x04	/* Write disable */
#define SPINOR_OP_AAI_WP	0xad	/* Auto address increment word program */

/* Used for SST26* flashes only. */
#define SPINOR_OP_READ_BPR	0x72	/* Read block protection register */
#define SPINOR_OP_WRITE_BPR	0x42	/* Write block protection register */

/* Used for S3AN flashes only */
#define SPINOR_OP_XSE		0x50	/* Sector erase */
#define SPINOR_OP_XPP		0x82	/* Page program */
#define SPINOR_OP_XRDSR		0xd7	/* Read status register */

#define XSR_PAGESIZE		BIT(0)	/* Page size in Po2 or Linear */
#define XSR_RDY			BIT(7)	/* Ready */

/* Used for Macronix and Winbond flashes. */
#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */

/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR		0x17	/* Bank register write */
#define SPINOR_OP_BRRD		0x16	/* Bank register read */
#define SPINOR_OP_CLSR		0x30	/* Clear status register 1 */

/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */

/* Status Register bits. */
#define SR_WIP			BIT(0)	/* Write in progress */
#define SR_WEL			BIT(1)	/* Write enable latch */
/* meaning of other SR_* bits may differ between vendors */
#define SR_BP0			BIT(2)	/* Block protect 0 */
#define SR_BP1			BIT(3)	/* Block protect 1 */
#define SR_BP2			BIT(4)	/* Block protect 2 */
#define SR_TB			BIT(5)	/* Top/Bottom protect */
#define SR_SRWD			BIT(7)	/* SR write protect */
/* Spansion/Cypress specific status bits */
#define SR_E_ERR		BIT(5)
#define SR_P_ERR		BIT(6)

#define SR_QUAD_EN_MX		BIT(6)	/* Macronix Quad I/O */

/* Enhanced Volatile Configuration Register bits */
#define EVCR_QUAD_EN_MICRON	BIT(7)	/* Micron Quad I/O */

/* Flag Status Register bits */
#define FSR_READY		BIT(7)	/* Device status, 0 = Busy, 1 = Ready */
#define FSR_E_ERR		BIT(5)	/* Erase operation status */
#define FSR_P_ERR		BIT(4)	/* Program operation status */
#define FSR_PT_ERR		BIT(1)	/* Protection error bit */

/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN		BIT(1)	/* Spansion Quad I/O */

/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT7	BIT(7)

/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK	GENMASK(23, 16)
#define SNOR_PROTO_INST_SHIFT	16
#define SNOR_PROTO_INST(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
	 SNOR_PROTO_INST_MASK)

#define SNOR_PROTO_ADDR_MASK	GENMASK(15, 8)
#define SNOR_PROTO_ADDR_SHIFT	8
#define SNOR_PROTO_ADDR(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
	 SNOR_PROTO_ADDR_MASK)

#define SNOR_PROTO_DATA_MASK	GENMASK(7, 0)
#define SNOR_PROTO_DATA_SHIFT	0
#define SNOR_PROTO_DATA(_nbits)	\
	((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
	 SNOR_PROTO_DATA_MASK)

#define SNOR_PROTO_IS_DTR	BIT(24)	/* Double Transfer Rate */

#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)	\
	(SNOR_PROTO_INST(_inst_nbits) |				\
	 SNOR_PROTO_ADDR(_addr_nbits) |				\
	 SNOR_PROTO_DATA(_data_nbits))
#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)	\
	(SNOR_PROTO_IS_DTR |					\
	 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))

enum spi_nor_protocol {
	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
	SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
	SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
	SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),

	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
};

static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
{
	return !!(proto & SNOR_PROTO_IS_DTR);
}

static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
		SNOR_PROTO_INST_SHIFT;
}

static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
		SNOR_PROTO_ADDR_SHIFT;
}

static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
{
	return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
		SNOR_PROTO_DATA_SHIFT;
}

static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
{
	return spi_nor_get_protocol_data_nbits(proto);
}

#define SPI_NOR_MAX_CMD_SIZE	8
enum spi_nor_ops {
	SPI_NOR_OPS_READ = 0,
	SPI_NOR_OPS_WRITE,
	SPI_NOR_OPS_ERASE,
	SPI_NOR_OPS_LOCK,
	SPI_NOR_OPS_UNLOCK,
};

enum spi_nor_option_flags {
	SNOR_F_USE_FSR		= BIT(0),
	SNOR_F_HAS_SR_TB	= BIT(1),
	SNOR_F_NO_OP_CHIP_ERASE	= BIT(2),
	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
	SNOR_F_READY_XSR_RDY	= BIT(4),
	SNOR_F_USE_CLSR		= BIT(5),
	SNOR_F_BROKEN_RESET	= BIT(6),
};

/**
 * struct flash_info - Forward declaration of a structure used internally by
 *		       spi_nor_scan()
 */
struct flash_info;

/*
 * TODO: Remove, once all users of spi_flash interface are moved to MTD
 *
 * struct spi_flash {
 *	Defined below (keep this text to enable searching for spi_flash decl)
 * }
 */
#define spi_flash spi_nor

/**
 * struct spi_nor - Structure for defining a the SPI NOR layer
 * @mtd:		point to a mtd_info structure
 * @lock:		the lock for the read/write/erase/lock/unlock operations
 * @dev:		point to a spi device, or a spi nor controller device.
 * @info:		spi-nor part JDEC MFR id and other info
 * @manufacturer_sfdp:	manufacturer specific SFDP table
 * @page_size:		the page size of the SPI NOR
 * @addr_width:		number of address bytes
 * @erase_opcode:	the opcode for erasing a sector
 * @read_opcode:	the read opcode
 * @read_dummy:		the dummy needed by the read operation
 * @program_opcode:	the program opcode
 * @bank_read_cmd:	Bank read cmd
 * @bank_write_cmd:	Bank write cmd
 * @bank_curr:		Current flash bank
 * @sst_write_second:	used by the SST write operation
 * @flags:		flag options for the current SPI-NOR (SNOR_F_*)
 * @read_proto:		the SPI protocol for read operations
 * @write_proto:	the SPI protocol for write operations
 * @reg_proto		the SPI protocol for read_reg/write_reg/erase operations
 * @cmd_buf:		used by the write_reg
 * @prepare:		[OPTIONAL] do some preparations for the
 *			read/write/erase/lock/unlock operations
 * @unprepare:		[OPTIONAL] do some post work after the
 *			read/write/erase/lock/unlock operations
 * @read_reg:		[DRIVER-SPECIFIC] read out the register
 * @write_reg:		[DRIVER-SPECIFIC] write data to the register
 * @read:		[DRIVER-SPECIFIC] read data from the SPI NOR
 * @write:		[DRIVER-SPECIFIC] write data to the SPI NOR
 * @erase:		[DRIVER-SPECIFIC] erase a sector of the SPI NOR
 *			at the offset @offs; if not provided by the driver,
 *			spi-nor will send the erase opcode via write_reg()
 * @flash_lock:		[FLASH-SPECIFIC] lock a region of the SPI NOR
 * @flash_unlock:	[FLASH-SPECIFIC] unlock a region of the SPI NOR
 * @flash_is_locked:	[FLASH-SPECIFIC] check if a region of the SPI NOR is
 * @quad_enable:	[FLASH-SPECIFIC] enables SPI NOR quad mode
 *			completely locked
 * @priv:		the private data
 */
struct spi_nor {
	struct mtd_info		mtd;
	struct udevice		*dev;
	struct spi_slave	*spi;
	const struct flash_info	*info;
	u8			*manufacturer_sfdp;
	u32			page_size;
	u8			addr_width;
	u8			erase_opcode;
	u8			read_opcode;
	u8			read_dummy;
	u8			program_opcode;
#ifdef CONFIG_SPI_FLASH_BAR
	u8			bank_read_cmd;
	u8			bank_write_cmd;
	u8			bank_curr;
#endif
	enum spi_nor_protocol	read_proto;
	enum spi_nor_protocol	write_proto;
	enum spi_nor_protocol	reg_proto;
	bool			sst_write_second;
	u32			flags;
	u8			cmd_buf[SPI_NOR_MAX_CMD_SIZE];

	int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
	int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
	int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);

	ssize_t (*read)(struct spi_nor *nor, loff_t from,
			size_t len, u_char *read_buf);
	ssize_t (*write)(struct spi_nor *nor, loff_t to,
			 size_t len, const u_char *write_buf);
	int (*erase)(struct spi_nor *nor, loff_t offs);

	int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
	int (*quad_enable)(struct spi_nor *nor);

	void *priv;
/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
	const char *name;
	u32 size;
	u32 sector_size;
	u32 erase_size;
};

static inline void spi_nor_set_flash_node(struct spi_nor *nor,
					  const struct device_node *np)
{
	mtd_set_of_node(&nor->mtd, np);
}

static inline const struct
device_node *spi_nor_get_flash_node(struct spi_nor *nor)
{
	return mtd_get_of_node(&nor->mtd);
}

/**
 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 * supported by the SPI controller (bus master).
 * @mask:		the bitmask listing all the supported hw capabilies
 */
struct spi_nor_hwcaps {
	u32	mask;
};

/*
 *(Fast) Read capabilities.
 * MUST be ordered by priority: the higher bit position, the higher priority.
 * As a matter of performances, it is relevant to use Octo SPI protocols first,
 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 * (Slow) Read.
 */
#define SNOR_HWCAPS_READ_MASK		GENMASK(14, 0)
#define SNOR_HWCAPS_READ		BIT(0)
#define SNOR_HWCAPS_READ_FAST		BIT(1)
#define SNOR_HWCAPS_READ_1_1_1_DTR	BIT(2)

#define SNOR_HWCAPS_READ_DUAL		GENMASK(6, 3)
#define SNOR_HWCAPS_READ_1_1_2		BIT(3)
#define SNOR_HWCAPS_READ_1_2_2		BIT(4)
#define SNOR_HWCAPS_READ_2_2_2		BIT(5)
#define SNOR_HWCAPS_READ_1_2_2_DTR	BIT(6)

#define SNOR_HWCAPS_READ_QUAD		GENMASK(10, 7)
#define SNOR_HWCAPS_READ_1_1_4		BIT(7)
#define SNOR_HWCAPS_READ_1_4_4		BIT(8)
#define SNOR_HWCAPS_READ_4_4_4		BIT(9)
#define SNOR_HWCAPS_READ_1_4_4_DTR	BIT(10)

#define SNOR_HWCPAS_READ_OCTO		GENMASK(14, 11)
#define SNOR_HWCAPS_READ_1_1_8		BIT(11)
#define SNOR_HWCAPS_READ_1_8_8		BIT(12)
#define SNOR_HWCAPS_READ_8_8_8		BIT(13)
#define SNOR_HWCAPS_READ_1_8_8_DTR	BIT(14)

/*
 * Page Program capabilities.
 * MUST be ordered by priority: the higher bit position, the higher priority.
 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
 * legacy SPI 1-1-1 protocol.
 * Note that Dual Page Programs are not supported because there is no existing
 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 * implements such commands.
 */
#define SNOR_HWCAPS_PP_MASK	GENMASK(22, 16)
#define SNOR_HWCAPS_PP		BIT(16)

#define SNOR_HWCAPS_PP_QUAD	GENMASK(19, 17)
#define SNOR_HWCAPS_PP_1_1_4	BIT(17)
#define SNOR_HWCAPS_PP_1_4_4	BIT(18)
#define SNOR_HWCAPS_PP_4_4_4	BIT(19)

#define SNOR_HWCAPS_PP_OCTO	GENMASK(22, 20)
#define SNOR_HWCAPS_PP_1_1_8	BIT(20)
#define SNOR_HWCAPS_PP_1_8_8	BIT(21)
#define SNOR_HWCAPS_PP_8_8_8	BIT(22)

/**
 * spi_nor_scan() - scan the SPI NOR
 * @nor:	the spi_nor structure
 *
 * The drivers can use this function to scan the SPI NOR.
 * In the scanning, it will try to get all the necessary information to
 * fill the mtd_info{} and the spi_nor{}.
 *
 * Return: 0 for success, others for failure.
 */
int spi_nor_scan(struct spi_nor *nor);

#endif
Commit	Line	Data
7aeedac0 V	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	4	* Synced from Linux v4.19
	5	*/
	6
	7	#ifndef __LINUX_MTD_SPI_NOR_H
	8	#define __LINUX_MTD_SPI_NOR_H
	9
	10	#include <linux/bitops.h>
	11	#include <linux/mtd/cfi.h>
	12	#include <linux/mtd/mtd.h>
	13
	14	/*
	15	* Manufacturer IDs
	16	*
	17	* The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
	18	* Sometimes these are the same as CFI IDs, but sometimes they aren't.
	19	*/
	20	#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
	21	#define SNOR_MFR_GIGADEVICE 0xc8
	22	#define SNOR_MFR_INTEL CFI_MFR_INTEL
	23	#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
	24	#define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
5bf3f3dd	25	#define SNOR_MFR_ISSI CFI_MFR_PMC
7aeedac0 V	26	#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
	27	#define SNOR_MFR_SPANSION CFI_MFR_AMD
	28	#define SNOR_MFR_SST CFI_MFR_SST
	29	#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
	30
	31	/*
	32	* Note on opcode nomenclature: some opcodes have a format like
	33	* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
	34	* of I/O lines used for the opcode, address, and data (respectively). The
	35	* FUNCTION has an optional suffix of '4', to represent an opcode which
	36	* requires a 4-byte (32-bit) address.
	37	*/
	38
	39	/* Flash opcodes. */
	40	#define SPINOR_OP_WREN 0x06 /* Write enable */
	41	#define SPINOR_OP_RDSR 0x05 /* Read status register */
	42	#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
	43	#define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
	44	#define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
	45	#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
	46	#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
	47	#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
	48	#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
	49	#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
	50	#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
658df8bd VR	51	#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
658df8bd VR	52	#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
7aeedac0 V	53	#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
	54	#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
	55	#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
658df8bd VR	56	#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
658df8bd VR	57	#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
7aeedac0 V	58	#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
	59	#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
	60	#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
	61	#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
	62	#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
	63	#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
	64	#define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
	65	#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
	66	#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
	67	#define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
	68	#define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
	69	#define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
	70
	71	/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
	72	#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
	73	#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
	74	#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
	75	#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
	76	#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
	77	#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
658df8bd VR	78	#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
658df8bd VR	79	#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
7aeedac0 V	80	#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
	81	#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
	82	#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
658df8bd VR	83	#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
658df8bd VR	84	#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
7aeedac0 V	85	#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
	86	#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
	87	#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
	88
	89	/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
	90	#define SPINOR_OP_READ_1_1_1_DTR 0x0d
	91	#define SPINOR_OP_READ_1_2_2_DTR 0xbd
	92	#define SPINOR_OP_READ_1_4_4_DTR 0xed
	93
	94	#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
	95	#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
	96	#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
	97
	98	/* Used for SST flashes only. */
	99	#define SPINOR_OP_BP 0x02 /* Byte program */
	100	#define SPINOR_OP_WRDI 0x04 /* Write disable */
	101	#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
	102
e0cacdcc EP	103	/* Used for SST26* flashes only. */
	104	#define SPINOR_OP_READ_BPR 0x72 /* Read block protection register */
	105	#define SPINOR_OP_WRITE_BPR 0x42 /* Write block protection register */
	106
7aeedac0 V	107	/* Used for S3AN flashes only */
	108	#define SPINOR_OP_XSE 0x50 /* Sector erase */
	109	#define SPINOR_OP_XPP 0x82 /* Page program */
	110	#define SPINOR_OP_XRDSR 0xd7 /* Read status register */
	111
	112	#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
	113	#define XSR_RDY BIT(7) /* Ready */
	114
	115	/* Used for Macronix and Winbond flashes. */
	116	#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
	117	#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
	118
	119	/* Used for Spansion flashes only. */
	120	#define SPINOR_OP_BRWR 0x17 /* Bank register write */
8c927809	121	#define SPINOR_OP_BRRD 0x16 /* Bank register read */
7aeedac0 V	122	#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
	123
	124	/* Used for Micron flashes only. */
	125	#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
	126	#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
	127
	128	/* Status Register bits. */
	129	#define SR_WIP BIT(0) /* Write in progress */
	130	#define SR_WEL BIT(1) /* Write enable latch */
	131	/* meaning of other SR_* bits may differ between vendors */
	132	#define SR_BP0 BIT(2) /* Block protect 0 */
	133	#define SR_BP1 BIT(3) /* Block protect 1 */
	134	#define SR_BP2 BIT(4) /* Block protect 2 */
	135	#define SR_TB BIT(5) /* Top/Bottom protect */
	136	#define SR_SRWD BIT(7) /* SR write protect */
	137	/* Spansion/Cypress specific status bits */
	138	#define SR_E_ERR BIT(5)
	139	#define SR_P_ERR BIT(6)
	140
	141	#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
	142
	143	/* Enhanced Volatile Configuration Register bits */
	144	#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
	145
	146	/* Flag Status Register bits */
	147	#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
	148	#define FSR_E_ERR BIT(5) /* Erase operation status */
	149	#define FSR_P_ERR BIT(4) /* Program operation status */
	150	#define FSR_PT_ERR BIT(1) /* Protection error bit */
	151
	152	/* Configuration Register bits. */
	153	#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
	154
	155	/* Status Register 2 bits. */
	156	#define SR2_QUAD_EN_BIT7 BIT(7)
	157
	158	/* Supported SPI protocols */
	159	#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
	160	#define SNOR_PROTO_INST_SHIFT 16
	161	#define SNOR_PROTO_INST(_nbits) \
	162	((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
	163	SNOR_PROTO_INST_MASK)
	164
	165	#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
	166	#define SNOR_PROTO_ADDR_SHIFT 8
	167	#define SNOR_PROTO_ADDR(_nbits) \
	168	((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
	169	SNOR_PROTO_ADDR_MASK)
	170
	171	#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
	172	#define SNOR_PROTO_DATA_SHIFT 0
	173	#define SNOR_PROTO_DATA(_nbits) \
	174	((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
	175	SNOR_PROTO_DATA_MASK)
	176
	177	#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
	178
	179	#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
	180	(SNOR_PROTO_INST(_inst_nbits) \| \
	181	SNOR_PROTO_ADDR(_addr_nbits) \| \
	182	SNOR_PROTO_DATA(_data_nbits))
	183	#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
	184	(SNOR_PROTO_IS_DTR \| \
	185	SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
186
187	enum spi_nor_protocol {
188	SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
189	SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
190	SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
191	SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
192	SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
193	SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
194	SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
195	SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
196	SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
197	SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
198
199	SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
200	SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
201	SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
202	SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
203	};
204
205	static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
206	{
207	return !!(proto & SNOR_PROTO_IS_DTR);
208	}
209
210	static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
211	{
212	return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
213	SNOR_PROTO_INST_SHIFT;
214	}
215
216	static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
217	{
218	return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
219	SNOR_PROTO_ADDR_SHIFT;
220	}
221
222	static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
223	{
224	return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
225	SNOR_PROTO_DATA_SHIFT;
226	}
227
228	static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
229	{
230	return spi_nor_get_protocol_data_nbits(proto);
231	}
232
233	#define SPI_NOR_MAX_CMD_SIZE 8
234	enum spi_nor_ops {
235	SPI_NOR_OPS_READ = 0,
236	SPI_NOR_OPS_WRITE,
237	SPI_NOR_OPS_ERASE,
238	SPI_NOR_OPS_LOCK,
239	SPI_NOR_OPS_UNLOCK,
240	};
241
242	enum spi_nor_option_flags {
243	SNOR_F_USE_FSR = BIT(0),
244	SNOR_F_HAS_SR_TB = BIT(1),
245	SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
246	SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
247	SNOR_F_READY_XSR_RDY = BIT(4),
248	SNOR_F_USE_CLSR = BIT(5),
249	SNOR_F_BROKEN_RESET = BIT(6),
250	};
251
252	/**
253	* struct flash_info - Forward declaration of a structure used internally by
254	* spi_nor_scan()
255	*/
256	struct flash_info;
257
7e45bb08 SG	258	/*
	259	* TODO: Remove, once all users of spi_flash interface are moved to MTD
	260	*
	261	* struct spi_flash {
	262	* Defined below (keep this text to enable searching for spi_flash decl)
	263	* }
	264	*/
7aeedac0 V	265	#define spi_flash spi_nor
	266
	267	/**
	268	* struct spi_nor - Structure for defining a the SPI NOR layer
	269	* @mtd: point to a mtd_info structure
	270	* @lock: the lock for the read/write/erase/lock/unlock operations
	271	* @dev: point to a spi device, or a spi nor controller device.
	272	* @info: spi-nor part JDEC MFR id and other info
a11c081d	273	* @manufacturer_sfdp: manufacturer specific SFDP table
7aeedac0 V	274	* @page_size: the page size of the SPI NOR
	275	* @addr_width: number of address bytes
	276	* @erase_opcode: the opcode for erasing a sector
	277	* @read_opcode: the read opcode
	278	* @read_dummy: the dummy needed by the read operation
	279	* @program_opcode: the program opcode
8c927809 V	280	* @bank_read_cmd: Bank read cmd
	281	* @bank_write_cmd: Bank write cmd
	282	* @bank_curr: Current flash bank
7aeedac0 V	283	* @sst_write_second: used by the SST write operation
	284	* @flags: flag options for the current SPI-NOR (SNOR_F_*)
	285	* @read_proto: the SPI protocol for read operations
	286	* @write_proto: the SPI protocol for write operations
	287	* @reg_proto the SPI protocol for read_reg/write_reg/erase operations
	288	* @cmd_buf: used by the write_reg
	289	* @prepare: [OPTIONAL] do some preparations for the
	290	* read/write/erase/lock/unlock operations
	291	* @unprepare: [OPTIONAL] do some post work after the
	292	* read/write/erase/lock/unlock operations
	293	* @read_reg: [DRIVER-SPECIFIC] read out the register
	294	* @write_reg: [DRIVER-SPECIFIC] write data to the register
	295	* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
	296	* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
	297	* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
	298	* at the offset @offs; if not provided by the driver,
	299	* spi-nor will send the erase opcode via write_reg()
	300	* @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
	301	* @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
	302	* @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
	303	* @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
	304	* completely locked
	305	* @priv: the private data
	306	*/
	307	struct spi_nor {
	308	struct mtd_info mtd;
	309	struct udevice *dev;
	310	struct spi_slave *spi;
	311	const struct flash_info *info;
a11c081d	312	u8 *manufacturer_sfdp;
7aeedac0 V	313	u32 page_size;
	314	u8 addr_width;
	315	u8 erase_opcode;
	316	u8 read_opcode;
	317	u8 read_dummy;
	318	u8 program_opcode;
8c927809 V	319	#ifdef CONFIG_SPI_FLASH_BAR
	320	u8 bank_read_cmd;
	321	u8 bank_write_cmd;
	322	u8 bank_curr;
	323	#endif
7aeedac0 V	324	enum spi_nor_protocol read_proto;
	325	enum spi_nor_protocol write_proto;
	326	enum spi_nor_protocol reg_proto;
	327	bool sst_write_second;
	328	u32 flags;
	329	u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
	330
	331	int (prepare)(struct spi_nor nor, enum spi_nor_ops ops);
	332	void (unprepare)(struct spi_nor nor, enum spi_nor_ops ops);
	333	int (read_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
	334	int (write_reg)(struct spi_nor nor, u8 opcode, u8 *buf, int len);
	335
	336	ssize_t (read)(struct spi_nor nor, loff_t from,
	337	size_t len, u_char *read_buf);
	338	ssize_t (write)(struct spi_nor nor, loff_t to,
	339	size_t len, const u_char *write_buf);
	340	int (erase)(struct spi_nor nor, loff_t offs);
	341
	342	int (flash_lock)(struct spi_nor nor, loff_t ofs, uint64_t len);
	343	int (flash_unlock)(struct spi_nor nor, loff_t ofs, uint64_t len);
	344	int (flash_is_locked)(struct spi_nor nor, loff_t ofs, uint64_t len);
	345	int (quad_enable)(struct spi_nor nor);
	346
	347	void *priv;
	348	/* Compatibility for spi_flash, remove once sf layer is merged with mtd */
	349	const char *name;
	350	u32 size;
	351	u32 sector_size;
	352	u32 erase_size;
	353	};
	354
	355	static inline void spi_nor_set_flash_node(struct spi_nor *nor,
	356	const struct device_node *np)
	357	{
	358	mtd_set_of_node(&nor->mtd, np);
	359	}
	360
	361	static inline const struct
	362	device_node spi_nor_get_flash_node(struct spi_nor nor)
	363	{
	364	return mtd_get_of_node(&nor->mtd);
	365	}
	366
	367	/**
	368	* struct spi_nor_hwcaps - Structure for describing the hardware capabilies
	369	* supported by the SPI controller (bus master).
	370	* @mask: the bitmask listing all the supported hw capabilies
	371	*/
	372	struct spi_nor_hwcaps {
	373	u32 mask;
	374	};
	375
	376	/*
	377	*(Fast) Read capabilities.
	378	* MUST be ordered by priority: the higher bit position, the higher priority.
	379	* As a matter of performances, it is relevant to use Octo SPI protocols first,
	380	* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
	381	* (Slow) Read.
	382	*/
	383	#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
	384	#define SNOR_HWCAPS_READ BIT(0)
	385	#define SNOR_HWCAPS_READ_FAST BIT(1)
	386	#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
	387
388	#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
389	#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
390	#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
391	#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
392	#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
393
394	#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
395	#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
396	#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
397	#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
398	#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
399
400	#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
401	#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
402	#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
403	#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
404	#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
405
406	/*
407	* Page Program capabilities.
408	* MUST be ordered by priority: the higher bit position, the higher priority.
409	* Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
410	* legacy SPI 1-1-1 protocol.
411	* Note that Dual Page Programs are not supported because there is no existing
412	* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
413	* implements such commands.
414	*/
415	#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
416	#define SNOR_HWCAPS_PP BIT(16)
417
418	#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
419	#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
420	#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
421	#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
422
423	#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
424	#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
425	#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
426	#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
427
428	/**
429	* spi_nor_scan() - scan the SPI NOR
430	* @nor: the spi_nor structure
431	*
432	* The drivers can use this function to scan the SPI NOR.
433	* In the scanning, it will try to get all the necessary information to
434	* fill the mtd_info{} and the spi_nor{}.
435	*
436	* Return: 0 for success, others for failure.
437	*/
438	int spi_nor_scan(struct spi_nor *nor);
439
440	#endif