[J-u-boot.git] / include / configs / alt.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/configs/alt.h
 *     This file is alt board configuration.
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 */

#ifndef __ALT_H
#define __ALT_H

#include "rcar-gen2-common.h"

#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
#define STACK_AREA_SIZE			0x00100000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* FLASH */
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"bootm_size=0x10000000\0"	\
	"usb_pgood_delay=2000\0"

/* SPL support */
#define CONFIG_SPL_STACK		0xe6340000
#define CONFIG_SPL_MAX_SIZE		0x4000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ		65000000
#endif

#endif /* __ALT_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
cff2f5f0 NI	2	/*
	3	* include/configs/alt.h
	4	* This file is alt board configuration.
	5	*
	6	* Copyright (C) 2014 Renesas Electronics Corporation
cff2f5f0 NI	7	*/
	8
	9	#ifndef __ALT_H
	10	#define __ALT_H
	11
5ca6dfe6	12	#include "rcar-gen2-common.h"
cff2f5f0	13
bb6d2ff2 MV	14	#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
bb6d2ff2 MV	15	#define STACK_AREA_SIZE 0x00100000
cff2f5f0 NI	16	#define LOW_LEVEL_MERAM_STACK \
	17	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	18
	19	/* MEMORY */
5ca6dfe6 NI	20	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	21	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	22	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
cff2f5f0	23
cff2f5f0	24	/* FLASH */
cff2f5f0	25	#define CONFIG_SPI_FLASH_QUAD
cff2f5f0	26
cff2f5f0	27	/* SH Ether */
cff2f5f0 NI	28	#define CONFIG_SH_ETHER_USE_PORT 0
	29	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	30	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	31	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	32	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
bb6d2ff2	33	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
cff2f5f0 NI	34	#define CONFIG_BITBANGMII_MULTI
	35
	36	/* Board Clock */
bb6d2ff2 MV	37	#define RMOBILE_XTAL_CLK 20000000u
bb6d2ff2 MV	38	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
bb6d2ff2 MV	39
bb6d2ff2 MV	40	#define CONFIG_EXTRA_ENV_SETTINGS \
8c563501 MV	41	"bootm_size=0x10000000\0" \
8c563501 MV	42	"usb_pgood_delay=2000\0"
bb6d2ff2 MV	43
bb6d2ff2 MV	44	/* SPL support */
bb6d2ff2 MV	45	#define CONFIG_SPL_STACK 0xe6340000
bb6d2ff2 MV	46	#define CONFIG_SPL_MAX_SIZE 0x4000
bb6d2ff2 MV	47	#ifdef CONFIG_SPL_BUILD
	48	#define CONFIG_CONS_SCIF2
	49	#define CONFIG_SH_SCIF_CLK_FREQ 65000000
	50	#endif
25f9613f	51
cff2f5f0	52	#endif /* __ALT_H */