[J-u-boot.git] / board / freescale / ls2080ardb / ls2080ardb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor
 * Copyright 2017 NXP
 */
#include <common.h>
#include <env.h>
#include <malloc.h>
#include <errno.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
#include <asm/io.h>
#include <hwconfig.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>

#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
#endif
#include "../common/vid.h"

#define PIN_MUX_SEL_SDHC	0x00
#define PIN_MUX_SEL_DSPI	0x0a

#define SET_SDHC_MUX_SEL(reg, value)	((reg & 0xf0) | value)
DECLARE_GLOBAL_DATA_PTR;

enum {
	MUX_TYPE_SDHC,
	MUX_TYPE_DSPI,
};

unsigned long long get_qixis_addr(void)
{
	unsigned long long addr;

	if (gd->flags & GD_FLG_RELOC)
		addr = QIXIS_BASE_PHYS;
	else
		addr = QIXIS_BASE_PHYS_EARLY;

	/*
	 * IFC address under 256MB is mapped to 0x30000000, any address above
	 * is mapped to 0x5_10000000 up to 4GB.
	 */
	addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;

	return addr;
}

int checkboard(void)
{
#ifdef CONFIG_FSL_QIXIS
	u8 sw;
#endif
	char buf[15];

	cpu_name(buf);
	printf("Board: %s-RDB, ", buf);

#ifdef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
	sw = QIXIS_READ(arch);
	printf("Board version: %c, ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
	switch (sw) {
	case 0:
		puts("boot from QSPI DEV#0\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
		break;
	case 1:
		puts("boot from QSPI DEV#1\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
		break;
	case 2:
		puts("boot from QSPI EMU\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
		break;
	case 3:
		puts("boot from QSPI EMU\n");
		puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
		break;
	case 4:
		puts("boot from QSPI DEV#0\n");
		puts("QSPI_CSA_1 mapped to QSPI EMU\n");
		break;
	default:
		printf("invalid setting of SW%u\n", sw);
		break;
	}
	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
	puts("SERDES1 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 161.13MHz");
#else
#ifdef CONFIG_FSL_QIXIS
	sw = QIXIS_READ(arch);
	printf("Board Arch: V%d, ", sw >> 4);
	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank: %d\n", sw);
	else if (sw == 0x9)
		puts("NAND\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);

	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
#endif
	puts("SERDES1 Reference : ");
	printf("Clock1 = 156.25MHz ");
	printf("Clock2 = 156.25MHz");
#endif

	puts("\nSERDES2 Reference : ");
	printf("Clock1 = 100MHz ");
	printf("Clock2 = 100MHz\n");

	return 0;
}

unsigned long get_board_sys_clk(void)
{
#ifdef CONFIG_FSL_QIXIS
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
#endif
	return 100000000;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

#ifndef CONFIG_DM_I2C
	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#else
	struct udevice *dev;

	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
	if (!ret)
		ret = dm_i2c_write(dev, 0, &ch, 1);
#endif

	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

int config_board_mux(int ctrl_type)
{
#ifdef CONFIG_FSL_QIXIS
	u8 reg5;

	reg5 = QIXIS_READ(brdcfg[5]);

	switch (ctrl_type) {
	case MUX_TYPE_SDHC:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
		break;
	case MUX_TYPE_DSPI:
		reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
		break;
	default:
		printf("Wrong mux interface type\n");
		return -1;
	}

	QIXIS_WRITE(brdcfg[5], reg5);
#endif
	return 0;
}

int board_init(void)
{
#ifdef CONFIG_FSL_MC_ENET
	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif

	init_final_memctl_regs();

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

#ifdef CONFIG_FSL_QIXIS
	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif

#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif
#ifdef CONFIG_FSL_LS_PPA
	ppa_init();
#endif

#ifdef CONFIG_FSL_MC_ENET
	/* invert AQR405 IRQ pins polarity */
	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
#ifdef CONFIG_FSL_CAAM
	sec_init();
#endif

#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
	pci_init();
#endif

	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_SYS_I2C_EARLY_INIT
	i2c_early_init_f();
#endif
	fsl_lsch3_early_init_f();
	return 0;
}

int misc_init_r(void)
{
	char *env_hwconfig;
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;
	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
	u32 svr = gur_in32(&gur->svr);

	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

	env_hwconfig = env_get("hwconfig");

	if (hwconfig_f("dspi", env_hwconfig) &&
	    DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
		config_board_mux(MUX_TYPE_DSPI);
	else
		config_board_mux(MUX_TYPE_SDHC);

	/*
	 * LS2081ARDB RevF board has smart voltage translator
	 * which needs to be programmed to enable high speed SD interface
	 * by setting GPIO4_10 output to zero
	 */
#ifdef CONFIG_TARGET_LS2081ARDB
		out_le32(GPIO4_GPDIR_ADDR, (1 << 21 |
					    in_le32(GPIO4_GPDIR_ADDR)));
		out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
					    in_le32(GPIO4_GPDAT_ADDR)));
#endif
	if (hwconfig("sdhc"))
		config_board_mux(MUX_TYPE_SDHC);

	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");
	/*
	 * Default value of board env is based on filename which is
	 * ls2080ardb. Modify board env for other supported SoCs
	 */
	if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2048A))
		env_set("board", "ls2088ardb");
	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
	    (SVR_SOC_VER(svr) == SVR_LS2041A))
		env_set("board", "ls2081ardb");

	return 0;
}

void detail_board_ddr_info(void)
{
	puts("\nDDR    ");
	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
		puts("\nDP-DDR ");
		print_size(gd->bd->bi_dram[2].size, "");
		print_ddr_info(CONFIG_DP_DDR_CTRL);
	}
#endif
}

#ifdef CONFIG_FSL_MC_ENET
void fdt_fixup_board_enet(void *fdt)
{
	int offset;

	offset = fdt_path_offset(fdt, "/soc/fsl-mc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/fsl-mc");

	if (offset < 0) {
		printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
		       __func__, offset);
		return;
	}

	if (get_mc_boot_status() == 0 &&
	    (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
		fdt_status_okay(fdt, offset);
	else
		fdt_status_fail(fdt, offset);
}

void board_quiesce_devices(void)
{
	fsl_mc_ldpaa_exit(gd->bd);
}
#endif

#ifdef CONFIG_OF_BOARD_SETUP
void fsl_fdt_fixup_flash(void *fdt)
{
	int offset;
#ifdef CONFIG_TFABOOT
	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
	u32 val;
#endif

/*
 * IFC and QSPI are muxed on board.
 * So disable IFC node in dts if QSPI is enabled or
 * disable QSPI node in dts in case QSPI is not enabled.
 */
#ifdef CONFIG_TFABOOT
	enum boot_src src = get_boot_src();
	bool disable_ifc = false;

	switch (src) {
	case BOOT_SOURCE_IFC_NOR:
		disable_ifc = false;
		break;
	case BOOT_SOURCE_QSPI_NOR:
		disable_ifc = true;
		break;
	default:
		val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
		if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
			disable_ifc = true;
		break;
	}

	if (disable_ifc) {
		offset = fdt_path_offset(fdt, "/soc/ifc");

		if (offset < 0)
			offset = fdt_path_offset(fdt, "/ifc");
	} else {
		offset = fdt_path_offset(fdt, "/soc/quadspi");

		if (offset < 0)
			offset = fdt_path_offset(fdt, "/quadspi");
	}

#else
#ifdef CONFIG_FSL_QSPI
	offset = fdt_path_offset(fdt, "/soc/ifc");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/ifc");
#else
	offset = fdt_path_offset(fdt, "/soc/quadspi");

	if (offset < 0)
		offset = fdt_path_offset(fdt, "/quadspi");
#endif
#endif

	if (offset < 0)
		return;

	fdt_status_disabled(fdt, offset);
}

int ft_board_setup(void *blob, bd_t *bd)
{
	int i;
	u16 mc_memory_bank = 0;

	u64 *base;
	u64 *size;
	u64 mc_memory_base = 0;
	u64 mc_memory_size = 0;
	u16 total_memory_banks;

	ft_cpu_setup(blob, bd);

	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);

	if (mc_memory_base != 0)
		mc_memory_bank++;

	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;

	base = calloc(total_memory_banks, sizeof(u64));
	size = calloc(total_memory_banks, sizeof(u64));

	/* fixup DT for the two GPP DDR banks */
	base[0] = gd->bd->bi_dram[0].start;
	size[0] = gd->bd->bi_dram[0].size;
	base[1] = gd->bd->bi_dram[1].start;
	size[1] = gd->bd->bi_dram[1].size;

#ifdef CONFIG_RESV_RAM
	/* reduce size if reserved memory is within this bank */
	if (gd->arch.resv_ram >= base[0] &&
	    gd->arch.resv_ram < base[0] + size[0])
		size[0] = gd->arch.resv_ram - base[0];
	else if (gd->arch.resv_ram >= base[1] &&
		 gd->arch.resv_ram < base[1] + size[1])
		size[1] = gd->arch.resv_ram - base[1];
#endif

	if (mc_memory_base != 0) {
		for (i = 0; i <= total_memory_banks; i++) {
			if (base[i] == 0 && size[i] == 0) {
				base[i] = mc_memory_base;
				size[i] = mc_memory_size;
				break;
			}
		}
	}

	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);

	fdt_fsl_mc_fixup_iommu_map_entry(blob);

	fsl_fdt_fixup_dr_usb(blob, bd);

	fsl_fdt_fixup_flash(blob);

#ifdef CONFIG_FSL_MC_ENET
	fdt_fixup_board_enet(blob);
#endif

	fdt_fixup_icid(blob);

	return 0;
}
#endif

void qixis_dump_switch(void)
{
#ifdef CONFIG_FSL_QIXIS
	int i, nr_of_cfgsw;

	QIXIS_WRITE(cms[0], 0x00);
	nr_of_cfgsw = QIXIS_READ(cms[1]);

	puts("DIP switch settings dump:\n");
	for (i = 1; i <= nr_of_cfgsw; i++) {
		QIXIS_WRITE(cms[0], i);
		printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	}
#endif
}

/*
 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
 * Both slots has 0x54, resulting 2nd slot unusable.
 */
void update_spd_address(unsigned int ctrl_num,
			unsigned int slot,
			unsigned int *addr)
{
#ifndef CONFIG_TARGET_LS2081ARDB
#ifdef CONFIG_FSL_QIXIS
	u8 sw;

	sw = QIXIS_READ(arch);
	if ((sw & 0xf) < 0x3) {
		if (ctrl_num == 1 && slot == 0)
			*addr = SPD_EEPROM_ADDRESS4;
		else if (ctrl_num == 1 && slot == 1)
			*addr = SPD_EEPROM_ADDRESS3;
	}
#endif
#endif
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e2b65ea9 YS	2	/*
e2b65ea9 YS	3	* Copyright 2015 Freescale Semiconductor
a7943fd4	4	* Copyright 2017 NXP
e2b65ea9 YS	5	*/
e2b65ea9 YS	6	#include <common.h>
9fb625ce	7	#include <env.h>
e2b65ea9 YS	8	#include <malloc.h>
	9	#include <errno.h>
	10	#include <netdev.h>
	11	#include <fsl_ifc.h>
	12	#include <fsl_ddr.h>
	13	#include <asm/io.h>
5a4d744c	14	#include <hwconfig.h>
e2b65ea9	15	#include <fdt_support.h>
b08c8c48	16	#include <linux/libfdt.h>
e2b65ea9	17	#include <fsl-mc/fsl_mc.h>
f3998fdc	18	#include <env_internal.h>
215b1fb9	19	#include <efi_loader.h>
e2b65ea9	20	#include <i2c.h>
4961eafc	21	#include <asm/arch/mmu.h>
9f3183d2	22	#include <asm/arch/soc.h>
54ad7b5a	23	#include <asm/arch/ppa.h>
fcfdb6d5	24	#include <fsl_sec.h>
e33938ac	25	#include <asm/arch-fsl-layerscape/fsl_icid.h>
e2b65ea9	26
d1418c15	27	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	28	#include "../common/qixis.h"
44937214	29	#include "ls2080ardb_qixis.h"
d1418c15	30	#endif
ed2530d0	31	#include "../common/vid.h"
e2b65ea9	32
5a4d744c	33	#define PIN_MUX_SEL_SDHC 0x00
5989df7e	34	#define PIN_MUX_SEL_DSPI 0x0a
5a4d744c YL	35
5a4d744c YL	36	#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) \| value)
e2b65ea9 YS	37	DECLARE_GLOBAL_DATA_PTR;
e2b65ea9 YS	38
5a4d744c YL	39	enum {
5a4d744c YL	40	MUX_TYPE_SDHC,
5989df7e	41	MUX_TYPE_DSPI,
5a4d744c YL	42	};
5a4d744c YL	43
e2b65ea9 YS	44	unsigned long long get_qixis_addr(void)
	45	{
	46	unsigned long long addr;
	47
	48	if (gd->flags & GD_FLG_RELOC)
	49	addr = QIXIS_BASE_PHYS;
	50	else
	51	addr = QIXIS_BASE_PHYS_EARLY;
	52
	53	/*
	54	* IFC address under 256MB is mapped to 0x30000000, any address above
	55	* is mapped to 0x5_10000000 up to 4GB.
	56	*/
	57	addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
	58
	59	return addr;
	60	}
	61
	62	int checkboard(void)
	63	{
d1418c15	64	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	65	u8 sw;
d1418c15	66	#endif
ff1b8e3f PK	67	char buf[15];
	68
	69	cpu_name(buf);
	70	printf("Board: %s-RDB, ", buf);
e2b65ea9	71
3049a583 PJ	72	#ifdef CONFIG_TARGET_LS2081ARDB
	73	#ifdef CONFIG_FSL_QIXIS
	74	sw = QIXIS_READ(arch);
3049a583 PJ	75	printf("Board version: %c, ", (sw & 0xf) + 'A');
	76
	77	sw = QIXIS_READ(brdcfg[0]);
da28a03e	78	sw = (sw >> QIXIS_QMAP_SHIFT) & QIXIS_QMAP_MASK;
3049a583 PJ	79	switch (sw) {
	80	case 0:
	81	puts("boot from QSPI DEV#0\n");
	82	puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
	83	break;
	84	case 1:
	85	puts("boot from QSPI DEV#1\n");
	86	puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
	87	break;
	88	case 2:
	89	puts("boot from QSPI EMU\n");
	90	puts("QSPI_CSA_1 mapped to QSPI DEV#0\n");
	91	break;
	92	case 3:
	93	puts("boot from QSPI EMU\n");
	94	puts("QSPI_CSA_1 mapped to QSPI DEV#1\n");
	95	break;
	96	case 4:
	97	puts("boot from QSPI DEV#0\n");
	98	puts("QSPI_CSA_1 mapped to QSPI EMU\n");
	99	break;
	100	default:
	101	printf("invalid setting of SW%u\n", sw);
	102	break;
	103	}
f436fbfe	104	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
3049a583 PJ	105	#endif
	106	puts("SERDES1 Reference : ");
	107	printf("Clock1 = 100MHz ");
	108	printf("Clock2 = 161.13MHz");
	109	#else
d1418c15	110	#ifdef CONFIG_FSL_QIXIS
e2b65ea9	111	sw = QIXIS_READ(arch);
e2b65ea9	112	printf("Board Arch: V%d, ", sw >> 4);
27df54b1	113	printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
e2b65ea9 YS	114
	115	sw = QIXIS_READ(brdcfg[0]);
	116	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	117
	118	if (sw < 0x8)
	119	printf("vBank: %d\n", sw);
	120	else if (sw == 0x9)
	121	puts("NAND\n");
	122	else
	123	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
	124
	125	printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
d1418c15	126	#endif
e2b65ea9 YS	127	puts("SERDES1 Reference : ");
	128	printf("Clock1 = 156.25MHz ");
	129	printf("Clock2 = 156.25MHz");
3049a583	130	#endif
e2b65ea9 YS	131
	132	puts("\nSERDES2 Reference : ");
	133	printf("Clock1 = 100MHz ");
	134	printf("Clock2 = 100MHz\n");
	135
	136	return 0;
	137	}
	138
	139	unsigned long get_board_sys_clk(void)
	140	{
d1418c15	141	#ifdef CONFIG_FSL_QIXIS
e2b65ea9 YS	142	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	143
	144	switch (sysclk_conf & 0x0F) {
	145	case QIXIS_SYSCLK_83:
	146	return 83333333;
	147	case QIXIS_SYSCLK_100:
	148	return 100000000;
	149	case QIXIS_SYSCLK_125:
	150	return 125000000;
	151	case QIXIS_SYSCLK_133:
	152	return 133333333;
	153	case QIXIS_SYSCLK_150:
	154	return 150000000;
	155	case QIXIS_SYSCLK_160:
	156	return 160000000;
	157	case QIXIS_SYSCLK_166:
	158	return 166666666;
	159	}
d1418c15 PJ	160	#endif
d1418c15 PJ	161	return 100000000;
e2b65ea9 YS	162	}
	163
	164	int select_i2c_ch_pca9547(u8 ch)
	165	{
	166	int ret;
	167
654e4e70	168	#ifndef CONFIG_DM_I2C
e2b65ea9	169	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
654e4e70 CH	170	#else
	171	struct udevice *dev;
	172
	173	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
	174	if (!ret)
	175	ret = dm_i2c_write(dev, 0, &ch, 1);
	176	#endif
	177
e2b65ea9 YS	178	if (ret) {
	179	puts("PCA: failed to select proper channel\n");
	180	return ret;
	181	}
	182
	183	return 0;
	184	}
	185
ed2530d0 RH	186	int i2c_multiplexer_select_vid_channel(u8 channel)
	187	{
	188	return select_i2c_ch_pca9547(channel);
	189	}
	190
5a4d744c YL	191	int config_board_mux(int ctrl_type)
5a4d744c YL	192	{
d1418c15	193	#ifdef CONFIG_FSL_QIXIS
5a4d744c YL	194	u8 reg5;
	195
	196	reg5 = QIXIS_READ(brdcfg[5]);
	197
	198	switch (ctrl_type) {
	199	case MUX_TYPE_SDHC:
	200	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
	201	break;
5989df7e HW	202	case MUX_TYPE_DSPI:
	203	reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
	204	break;
5a4d744c YL	205	default:
	206	printf("Wrong mux interface type\n");
	207	return -1;
	208	}
	209
	210	QIXIS_WRITE(brdcfg[5], reg5);
d1418c15	211	#endif
5a4d744c YL	212	return 0;
	213	}
	214
5989df7e HW	215	int board_init(void)
5989df7e HW	216	{
931e8751	217	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7	218	u32 __iomem irq_ccsr = (u32 __iomem )ISC_BASE;
931e8751	219	#endif
5989df7e HW	220
	221	init_final_memctl_regs();
	222
5989df7e HW	223	#ifdef CONFIG_ENV_IS_NOWHERE
	224	gd->env_addr = (ulong)&default_environment[0];
	225	#endif
	226	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	227
d1418c15	228	#ifdef CONFIG_FSL_QIXIS
5989df7e	229	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
d1418c15	230	#endif
15e7c681 UA	231
	232	#ifdef CONFIG_FSL_CAAM
	233	sec_init();
	234	#endif
54ad7b5a SK	235	#ifdef CONFIG_FSL_LS_PPA
	236	ppa_init();
	237	#endif
	238
931e8751	239	#ifdef CONFIG_FSL_MC_ENET
abc7d0f7 SX	240	/* invert AQR405 IRQ pins polarity */
abc7d0f7 SX	241	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
931e8751	242	#endif
a8c6fd4e UA	243	#ifdef CONFIG_FSL_CAAM
	244	sec_init();
	245	#endif
abc7d0f7	246
8da1058b IC	247	#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
	248	pci_init();
	249	#endif
	250
5989df7e HW	251	return 0;
	252	}
	253
	254	int board_early_init_f(void)
	255	{
3049a583 PJ	256	#ifdef CONFIG_SYS_I2C_EARLY_INIT
	257	i2c_early_init_f();
	258	#endif
5989df7e HW	259	fsl_lsch3_early_init_f();
	260	return 0;
	261	}
	262
5a4d744c YL	263	int misc_init_r(void)
5a4d744c YL	264	{
263536a6 SK	265	char *env_hwconfig;
	266	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	267	u32 val;
b5dfd475 PJ	268	struct ccsr_gur __iomem gur = (void )(CONFIG_SYS_FSL_GUTS_ADDR);
b5dfd475 PJ	269	u32 svr = gur_in32(&gur->svr);
263536a6 SK	270
	271	val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
	272
00caae6d	273	env_hwconfig = env_get("hwconfig");
263536a6 SK	274
	275	if (hwconfig_f("dspi", env_hwconfig) &&
	276	DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
	277	config_board_mux(MUX_TYPE_DSPI);
	278	else
	279	config_board_mux(MUX_TYPE_SDHC);
	280
5193405a	281	/*
6cc914ef	282	* LS2081ARDB RevF board has smart voltage translator
5193405a PJ	283	* which needs to be programmed to enable high speed SD interface
	284	* by setting GPIO4_10 output to zero
	285	*/
6cc914ef	286	#ifdef CONFIG_TARGET_LS2081ARDB
5193405a PJ	287	out_le32(GPIO4_GPDIR_ADDR, (1 << 21 \|
	288	in_le32(GPIO4_GPDIR_ADDR)));
	289	out_le32(GPIO4_GPDAT_ADDR, (~(1 << 21) &
	290	in_le32(GPIO4_GPDAT_ADDR)));
3049a583	291	#endif
5a4d744c YL	292	if (hwconfig("sdhc"))
	293	config_board_mux(MUX_TYPE_SDHC);
	294
ed2530d0 RH	295	if (adjust_vdd(0))
ed2530d0 RH	296	printf("Warning: Adjusting core voltage failed.\n");
b5dfd475 PJ	297	/*
	298	* Default value of board env is based on filename which is
	299	* ls2080ardb. Modify board env for other supported SoCs
	300	*/
	301	if ((SVR_SOC_VER(svr) == SVR_LS2088A) \|\|
	302	(SVR_SOC_VER(svr) == SVR_LS2048A))
	303	env_set("board", "ls2088ardb");
	304	else if ((SVR_SOC_VER(svr) == SVR_LS2081A) \|\|
	305	(SVR_SOC_VER(svr) == SVR_LS2041A))
	306	env_set("board", "ls2081ardb");
ed2530d0	307
5a4d744c YL	308	return 0;
	309	}
	310
e2b65ea9 YS	311	void detail_board_ddr_info(void)
	312	{
	313	puts("\nDDR ");
	314	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
	315	print_ddr_info(0);
44937214	316	#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
3c1d218a	317	if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
e2b65ea9 YS	318	puts("\nDP-DDR ");
	319	print_size(gd->bd->bi_dram[2].size, "");
	320	print_ddr_info(CONFIG_DP_DDR_CTRL);
	321	}
44937214	322	#endif
e2b65ea9 YS	323	}
e2b65ea9 YS	324
e2b65ea9 YS	325	#ifdef CONFIG_FSL_MC_ENET
	326	void fdt_fixup_board_enet(void *fdt)
	327	{
	328	int offset;
	329
e91f1dec	330	offset = fdt_path_offset(fdt, "/soc/fsl-mc");
e2b65ea9 YS	331
e2b65ea9 YS	332	if (offset < 0)
e91f1dec	333	offset = fdt_path_offset(fdt, "/fsl-mc");
e2b65ea9 YS	334
	335	if (offset < 0) {
	336	printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
	337	__func__, offset);
	338	return;
	339	}
	340
7e968049 MYK	341	if (get_mc_boot_status() == 0 &&
7e968049 MYK	342	(is_lazy_dpl_addr_valid() \|\| get_dpl_apply_status() == 0))
e2b65ea9 YS	343	fdt_status_okay(fdt, offset);
	344	else
	345	fdt_status_fail(fdt, offset);
	346	}
b7b8410a AG	347
	348	void board_quiesce_devices(void)
	349	{
	350	fsl_mc_ldpaa_exit(gd->bd);
	351	}
e2b65ea9 YS	352	#endif
	353
	354	#ifdef CONFIG_OF_BOARD_SETUP
7794d9ab SK	355	void fsl_fdt_fixup_flash(void *fdt)
	356	{
	357	int offset;
9570df03 RB	358	#ifdef CONFIG_TFABOOT
	359	u32 __iomem dcfg_ccsr = (u32 __iomem )DCFG_BASE;
	360	u32 val;
	361	#endif
7794d9ab SK	362
	363	/*
	364	* IFC and QSPI are muxed on board.
	365	* So disable IFC node in dts if QSPI is enabled or
	366	* disable QSPI node in dts in case QSPI is not enabled.
	367	*/
9570df03 RB	368	#ifdef CONFIG_TFABOOT
	369	enum boot_src src = get_boot_src();
	370	bool disable_ifc = false;
	371
	372	switch (src) {
	373	case BOOT_SOURCE_IFC_NOR:
	374	disable_ifc = false;
	375	break;
	376	case BOOT_SOURCE_QSPI_NOR:
	377	disable_ifc = true;
	378	break;
	379	default:
	380	val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
	381	if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
	382	disable_ifc = true;
	383	break;
	384	}
	385
	386	if (disable_ifc) {
	387	offset = fdt_path_offset(fdt, "/soc/ifc");
	388
	389	if (offset < 0)
	390	offset = fdt_path_offset(fdt, "/ifc");
	391	} else {
	392	offset = fdt_path_offset(fdt, "/soc/quadspi");
	393
	394	if (offset < 0)
	395	offset = fdt_path_offset(fdt, "/quadspi");
	396	}
	397
	398	#else
7794d9ab SK	399	#ifdef CONFIG_FSL_QSPI
	400	offset = fdt_path_offset(fdt, "/soc/ifc");
	401
	402	if (offset < 0)
	403	offset = fdt_path_offset(fdt, "/ifc");
	404	#else
	405	offset = fdt_path_offset(fdt, "/soc/quadspi");
	406
	407	if (offset < 0)
	408	offset = fdt_path_offset(fdt, "/quadspi");
	409	#endif
9570df03 RB	410	#endif
9570df03 RB	411
7794d9ab SK	412	if (offset < 0)
	413	return;
	414
	415	fdt_status_disabled(fdt, offset);
	416	}
	417
e2b65ea9 YS	418	int ft_board_setup(void blob, bd_t bd)
e2b65ea9 YS	419	{
cf0bbbd1 MA	420	int i;
	421	u16 mc_memory_bank = 0;
	422
	423	u64 *base;
	424	u64 *size;
	425	u64 mc_memory_base = 0;
	426	u64 mc_memory_size = 0;
	427	u16 total_memory_banks;
e2b65ea9 YS	428
	429	ft_cpu_setup(blob, bd);
	430
cf0bbbd1 MA	431	fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
	432
	433	if (mc_memory_base != 0)
	434	mc_memory_bank++;
	435
	436	total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
	437
	438	base = calloc(total_memory_banks, sizeof(u64));
	439	size = calloc(total_memory_banks, sizeof(u64));
	440
a2dc818f BS	441	/* fixup DT for the two GPP DDR banks */
	442	base[0] = gd->bd->bi_dram[0].start;
	443	size[0] = gd->bd->bi_dram[0].size;
	444	base[1] = gd->bd->bi_dram[1].start;
	445	size[1] = gd->bd->bi_dram[1].size;
	446
36cc0de0 YS	447	#ifdef CONFIG_RESV_RAM
	448	/* reduce size if reserved memory is within this bank */
	449	if (gd->arch.resv_ram >= base[0] &&
	450	gd->arch.resv_ram < base[0] + size[0])
	451	size[0] = gd->arch.resv_ram - base[0];
	452	else if (gd->arch.resv_ram >= base[1] &&
	453	gd->arch.resv_ram < base[1] + size[1])
	454	size[1] = gd->arch.resv_ram - base[1];
	455	#endif
	456
cf0bbbd1 MA	457	if (mc_memory_base != 0) {
	458	for (i = 0; i <= total_memory_banks; i++) {
	459	if (base[i] == 0 && size[i] == 0) {
	460	base[i] = mc_memory_base;
	461	size[i] = mc_memory_size;
	462	break;
	463	}
	464	}
	465	}
	466
	467	fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
e2b65ea9	468
a78df40c NG	469	fdt_fsl_mc_fixup_iommu_map_entry(blob);
a78df40c NG	470
a5c289b9	471	fsl_fdt_fixup_dr_usb(blob, bd);
ef53b8c4	472
7794d9ab SK	473	fsl_fdt_fixup_flash(blob);
7794d9ab SK	474
e2b65ea9 YS	475	#ifdef CONFIG_FSL_MC_ENET
e2b65ea9 YS	476	fdt_fixup_board_enet(blob);
e2b65ea9 YS	477	#endif
e2b65ea9 YS	478
e33938ac LT	479	fdt_fixup_icid(blob);
e33938ac LT	480
e2b65ea9 YS	481	return 0;
	482	}
	483	#endif
	484
	485	void qixis_dump_switch(void)
	486	{
d1418c15	487	#ifdef CONFIG_FSL_QIXIS
e2b65ea9 YS	488	int i, nr_of_cfgsw;
	489
	490	QIXIS_WRITE(cms[0], 0x00);
	491	nr_of_cfgsw = QIXIS_READ(cms[1]);
	492
	493	puts("DIP switch settings dump:\n");
	494	for (i = 1; i <= nr_of_cfgsw; i++) {
	495	QIXIS_WRITE(cms[0], i);
	496	printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
	497	}
d1418c15	498	#endif
e2b65ea9	499	}
fc7b3855 YS	500
	501	/*
	502	* Board rev C and earlier has duplicated I2C addresses for 2nd controller.
	503	* Both slots has 0x54, resulting 2nd slot unusable.
	504	*/
	505	void update_spd_address(unsigned int ctrl_num,
	506	unsigned int slot,
	507	unsigned int *addr)
	508	{
3049a583	509	#ifndef CONFIG_TARGET_LS2081ARDB
d1418c15	510	#ifdef CONFIG_FSL_QIXIS
fc7b3855 YS	511	u8 sw;
	512
	513	sw = QIXIS_READ(arch);
	514	if ((sw & 0xf) < 0x3) {
	515	if (ctrl_num == 1 && slot == 0)
	516	*addr = SPD_EEPROM_ADDRESS4;
	517	else if (ctrl_num == 1 && slot == 1)
	518	*addr = SPD_EEPROM_ADDRESS3;
	519	}
d1418c15	520	#endif
3049a583	521	#endif
fc7b3855	522	}