[J-u-boot.git] / arch / x86 / cpu / i386 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2008-2011
 * Graeme Russ, <[email protected]>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <[email protected]>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[email protected]>
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Alex Zuepke <[email protected]>
 *
 * Part of this file is adapted from coreboot
 * src/arch/x86/lib/cpu.c
 */

#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <malloc.h>
#include <spl.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/processor-flags.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Constructor for a conventional segment GDT (or LDT) entry
 * This is a macro so it can be used in initialisers
 */
#define GDT_ENTRY(flags, base, limit)			\
	((((base)  & 0xff000000ULL) << (56-24)) |	\
	 (((flags) & 0x0000f0ffULL) << 40) |		\
	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
	 (((base)  & 0x00ffffffULL) << 16) |		\
	 (((limit) & 0x0000ffffULL)))

struct gdt_ptr {
	u16 len;
	u32 ptr;
} __packed;

struct cpu_device_id {
	unsigned vendor;
	unsigned device;
};

struct cpuinfo_x86 {
	uint8_t x86;            /* CPU family */
	uint8_t x86_vendor;     /* CPU vendor */
	uint8_t x86_model;
	uint8_t x86_mask;
};

/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
/*
 * List of cpu vendor strings along with their normalized
 * id values.
 */
static const struct {
	int vendor;
	const char *name;
} x86_vendors[] = {
	{ X86_VENDOR_INTEL,     "GenuineIntel", },
	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
	{ X86_VENDOR_AMD,       "AuthenticAMD", },
	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
	{ X86_VENDOR_RISE,      "RiseRiseRise", },
	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
	{ X86_VENDOR_NSC,       "Geode by NSC", },
	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
};
#endif

static void load_ds(u32 segment)
{
	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
}

static void load_es(u32 segment)
{
	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
}

static void load_fs(u32 segment)
{
	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
}

static void load_gs(u32 segment)
{
	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
}

static void load_ss(u32 segment)
{
	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
}

static void load_gdt(const u64 *boot_gdt, u16 num_entries)
{
	struct gdt_ptr gdt;

	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
	gdt.ptr = (ulong)boot_gdt;

	asm volatile("lgdtl %0\n" : : "m" (gdt));
}

void arch_setup_gd(gd_t *new_gd)
{
	u64 *gdt_addr;

	gdt_addr = new_gd->arch.gdt;

	/*
	 * CS: code, read/execute, 4 GB, base 0
	 *
	 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
	 */
	gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);

	/* DS: data, read/write, 4 GB, base 0 */
	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);

	/*
	 * FS: data, read/write, sizeof (Global Data Pointer),
	 * base (Global Data Pointer)
	 */
	new_gd->arch.gd_addr = new_gd;
	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
					(ulong)&new_gd->arch.gd_addr,
					sizeof(new_gd->arch.gd_addr) - 1);

	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);

	/* 16-bit DS: data, read/write, 64 kB, base 0 */
	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);

	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);

	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
	load_ds(X86_GDT_ENTRY_32BIT_DS);
	load_es(X86_GDT_ENTRY_32BIT_DS);
	load_gs(X86_GDT_ENTRY_32BIT_DS);
	load_ss(X86_GDT_ENTRY_32BIT_DS);
	load_fs(X86_GDT_ENTRY_32BIT_FS);
}

#ifdef CONFIG_HAVE_FSP
/*
 * Setup FSP execution environment GDT
 *
 * Per Intel FSP external architecture specification, before calling any FSP
 * APIs, we need make sure the system is in flat 32-bit mode and both the code
 * and data selectors should have full 4GB access range. Here we reuse the one
 * we used in arch/x86/cpu/start16.S, and reload the segement registers.
 */
void setup_fsp_gdt(void)
{
	load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
	load_ds(X86_GDT_ENTRY_32BIT_DS);
	load_ss(X86_GDT_ENTRY_32BIT_DS);
	load_es(X86_GDT_ENTRY_32BIT_DS);
	load_fs(X86_GDT_ENTRY_32BIT_DS);
	load_gs(X86_GDT_ENTRY_32BIT_DS);
}
#endif

/*
 * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 * by the fact that they preserve the flags across the division of 5/2.
 * PII and PPro exhibit this behavior too, but they have cpuid available.
 */

/*
 * Perform the Cyrix 5/2 test. A Cyrix won't change
 * the flags, while other 486 chips will.
 */
static inline int test_cyrix_52div(void)
{
	unsigned int test;

	__asm__ __volatile__(
	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
	     "div %b2\n\t"	/* divide 5 by 2 */
	     "lahf"		/* store flags into %ah */
	     : "=a" (test)
	     : "0" (5), "q" (2)
	     : "cc");

	/* AH is 0x02 on Cyrix after the divide.. */
	return (unsigned char) (test >> 8) == 0x02;
}

#ifndef CONFIG_TPL_BUILD
/*
 *	Detect a NexGen CPU running without BIOS hypercode new enough
 *	to have CPUID. (Thanks to Herbert Oppmann)
 */
static int deep_magic_nexgen_probe(void)
{
	int ret;

	__asm__ __volatile__ (
		"	movw	$0x5555, %%ax\n"
		"	xorw	%%dx,%%dx\n"
		"	movw	$2, %%cx\n"
		"	divw	%%cx\n"
		"	movl	$0, %%eax\n"
		"	jnz	1f\n"
		"	movl	$1, %%eax\n"
		"1:\n"
		: "=a" (ret) : : "cx", "dx");
	return  ret;
}
#endif

static bool has_cpuid(void)
{
	return flag_is_changeable_p(X86_EFLAGS_ID);
}

static bool has_mtrr(void)
{
	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
}

#ifndef CONFIG_TPL_BUILD
static int build_vendor_name(char *vendor_name)
{
	struct cpuid_result result;
	result = cpuid(0x00000000);
	unsigned int *name_as_ints = (unsigned int *)vendor_name;

	name_as_ints[0] = result.ebx;
	name_as_ints[1] = result.edx;
	name_as_ints[2] = result.ecx;

	return result.eax;
}
#endif

static void identify_cpu(struct cpu_device_id *cpu)
{
	cpu->device = 0; /* fix gcc 4.4.4 warning */

	/*
	 * Do a quick and dirty check to save space - Intel and AMD only and
	 * just the vendor. This is enough for most TPL code.
	 */
	if (spl_phase() == PHASE_TPL) {
		struct cpuid_result result;

		result = cpuid(0x00000000);
		switch (result.ecx >> 24) {
		case 'l': /* GenuineIntel */
			cpu->vendor = X86_VENDOR_INTEL;
			break;
		case 'D': /* AuthenticAMD */
			cpu->vendor = X86_VENDOR_AMD;
			break;
		default:
			cpu->vendor = X86_VENDOR_ANY;
			break;
		}
		return;
	}

/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
	char vendor_name[16];
	int i;

	vendor_name[0] = '\0'; /* Unset */

	/* Find the id and vendor_name */
	if (!has_cpuid()) {
		/* Its a 486 if we can modify the AC flag */
		if (flag_is_changeable_p(X86_EFLAGS_AC))
			cpu->device = 0x00000400; /* 486 */
		else
			cpu->device = 0x00000300; /* 386 */
		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
			memcpy(vendor_name, "CyrixInstead", 13);
			/* If we ever care we can enable cpuid here */
		}
		/* Detect NexGen with old hypercode */
		else if (deep_magic_nexgen_probe())
			memcpy(vendor_name, "NexGenDriven", 13);
	} else {
		int cpuid_level;

		cpuid_level = build_vendor_name(vendor_name);
		vendor_name[12] = '\0';

		/* Intel-defined flags: level 0x00000001 */
		if (cpuid_level >= 0x00000001) {
			cpu->device = cpuid_eax(0x00000001);
		} else {
			/* Have CPUID level 0 only unheard of */
			cpu->device = 0x00000400;
		}
	}
	cpu->vendor = X86_VENDOR_UNKNOWN;
	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
			cpu->vendor = x86_vendors[i].vendor;
			break;
		}
	}
#endif
}

static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
{
	c->x86 = (tfms >> 8) & 0xf;
	c->x86_model = (tfms >> 4) & 0xf;
	c->x86_mask = tfms & 0xf;
	if (c->x86 == 0xf)
		c->x86 += (tfms >> 20) & 0xff;
	if (c->x86 >= 0x6)
		c->x86_model += ((tfms >> 16) & 0xF) << 4;
}

u32 cpu_get_family_model(void)
{
	return gd->arch.x86_device & 0x0fff0ff0;
}

u32 cpu_get_stepping(void)
{
	return gd->arch.x86_mask;
}

/* initialise FPU, reset EM, set MP and NE */
static void setup_cpu_features(void)
{
	const u32 em_rst = ~X86_CR0_EM;
	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;

	asm ("fninit\n" \
	"movl %%cr0, %%eax\n" \
	"andl %0, %%eax\n" \
	"orl  %1, %%eax\n" \
	"movl %%eax, %%cr0\n" \
	: : "i" (em_rst), "i" (mp_ne_set) : "eax");
}

static void setup_identity(void)
{
	/* identify CPU via cpuid and store the decoded info into gd->arch */
	if (has_cpuid()) {
		struct cpu_device_id cpu;
		struct cpuinfo_x86 c;

		identify_cpu(&cpu);
		get_fms(&c, cpu.device);
		gd->arch.x86 = c.x86;
		gd->arch.x86_vendor = cpu.vendor;
		gd->arch.x86_model = c.x86_model;
		gd->arch.x86_mask = c.x86_mask;
		gd->arch.x86_device = cpu.device;

		gd->arch.has_mtrr = has_mtrr();
	}
}

/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
static void setup_pci_ram_top(void)
{
	gd->pci_ram_top = 0x80000000U;
}

static void setup_mtrr(void)
{
	u64 mtrr_cap;

	/* Configure fixed range MTRRs for some legacy regions */
	if (!gd->arch.has_mtrr)
		return;

	mtrr_cap = native_read_msr(MTRR_CAP_MSR);
	if (mtrr_cap & MTRR_CAP_FIX) {
		/* Mark the VGA RAM area as uncacheable */
		native_write_msr(MTRR_FIX_16K_A0000_MSR,
				 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
				 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));

		/*
		 * Mark the PCI ROM area as cacheable to improve ROM
		 * execution performance.
		 */
		native_write_msr(MTRR_FIX_4K_C0000_MSR,
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
		native_write_msr(MTRR_FIX_4K_C8000_MSR,
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
		native_write_msr(MTRR_FIX_4K_D0000_MSR,
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
		native_write_msr(MTRR_FIX_4K_D8000_MSR,
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
				 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));

		/* Enable the fixed range MTRRs */
		msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
	}
}

int x86_cpu_init_tpl(void)
{
	setup_cpu_features();
	setup_identity();

	return 0;
}

int x86_cpu_init_f(void)
{
	if (ll_boot_init())
		setup_cpu_features();
	setup_identity();
	setup_mtrr();
	setup_pci_ram_top();

	/* Set up the i8254 timer if required */
	if (IS_ENABLED(CONFIG_I8254_TIMER))
		i8254_init();

	return 0;
}

long detect_coreboot_table_at(ulong start, ulong size)
{
	u32 *ptr, *end;

	size /= 4;
	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
		if (*ptr == 0x4f49424c) /* "LBIO" */
			return (long)ptr;
	}

	return -ENOENT;
}

long locate_coreboot_table(void)
{
	long addr;

	/* We look for LBIO in the first 4K of RAM and again at 960KB */
	addr = detect_coreboot_table_at(0x0, 0x1000);
	if (addr < 0)
		addr = detect_coreboot_table_at(0xf0000, 0x1000);

	return addr;
}

int x86_cpu_reinit_f(void)
{
	setup_identity();
	setup_pci_ram_top();
	if (locate_coreboot_table() >= 0)
		gd->flags |= GD_FLG_SKIP_LL_INIT;

	return 0;
}

void x86_enable_caches(void)
{
	unsigned long cr0;

	cr0 = read_cr0();
	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
	write_cr0(cr0);
	wbinvd();
}
void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));

void x86_disable_caches(void)
{
	unsigned long cr0;

	cr0 = read_cr0();
	cr0 |= X86_CR0_NW | X86_CR0_CD;
	wbinvd();
	write_cr0(cr0);
	wbinvd();
}
void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));

int dcache_status(void)
{
	return !(read_cr0() & X86_CR0_CD);
}

void cpu_enable_paging_pae(ulong cr3)
{
	__asm__ __volatile__(
		/* Load the page table address */
		"movl	%0, %%cr3\n"
		/* Enable pae */
		"movl	%%cr4, %%eax\n"
		"orl	$0x00000020, %%eax\n"
		"movl	%%eax, %%cr4\n"
		/* Enable paging */
		"movl	%%cr0, %%eax\n"
		"orl	$0x80000000, %%eax\n"
		"movl	%%eax, %%cr0\n"
		:
		: "r" (cr3)
		: "eax");
}

void cpu_disable_paging_pae(void)
{
	/* Turn off paging */
	__asm__ __volatile__ (
		/* Disable paging */
		"movl	%%cr0, %%eax\n"
		"andl	$0x7fffffff, %%eax\n"
		"movl	%%eax, %%cr0\n"
		/* Disable pae */
		"movl	%%cr4, %%eax\n"
		"andl	$0xffffffdf, %%eax\n"
		"movl	%%eax, %%cr4\n"
		:
		:
		: "eax");
}

static bool can_detect_long_mode(void)
{
	return cpuid_eax(0x80000000) > 0x80000000UL;
}

static bool has_long_mode(void)
{
	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
}

int cpu_has_64bit(void)
{
	return has_cpuid() && can_detect_long_mode() &&
		has_long_mode();
}

#define PAGETABLE_BASE		0x80000
#define PAGETABLE_SIZE		(6 * 4096)

/**
 * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
 *
 * @pgtable: Pointer to a 24iKB block of memory
 */
static void build_pagetable(uint32_t *pgtable)
{
	uint i;

	memset(pgtable, '\0', PAGETABLE_SIZE);

	/* Level 4 needs a single entry */
	pgtable[0] = (ulong)&pgtable[1024] + 7;

	/* Level 3 has one 64-bit entry for each GiB of memory */
	for (i = 0; i < 4; i++)
		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;

	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
	for (i = 0; i < 2048; i++)
		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
}

int cpu_jump_to_64bit(ulong setup_base, ulong target)
{
	uint32_t *pgtable;

	pgtable = memalign(4096, PAGETABLE_SIZE);
	if (!pgtable)
		return -ENOMEM;

	build_pagetable(pgtable);
	cpu_call64((ulong)pgtable, setup_base, target);
	free(pgtable);

	return -EFAULT;
}

/*
 * Jump from SPL to U-Boot
 *
 * This function is work-in-progress with many issues to resolve.
 *
 * It works by setting up several regions:
 *   ptr      - a place to put the code that jumps into 64-bit mode
 *   gdt      - a place to put the global descriptor table
 *   pgtable  - a place to put the page tables
 *
 * The cpu_call64() code is copied from ROM and then manually patched so that
 * it has the correct GDT address in RAM. U-Boot is copied from ROM into
 * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
 * which changes to 64-bit mode and starts U-Boot.
 */
int cpu_jump_to_64bit_uboot(ulong target)
{
	typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
	uint32_t *pgtable;
	func_t func;
	char *ptr;

	pgtable = (uint32_t *)PAGETABLE_BASE;

	build_pagetable(pgtable);

	extern long call64_stub_size;
	ptr = malloc(call64_stub_size);
	if (!ptr) {
		printf("Failed to allocate the cpu_call64 stub\n");
		return -ENOMEM;
	}
	memcpy(ptr, cpu_call64, call64_stub_size);

	func = (func_t)ptr;

	/*
	 * Copy U-Boot from ROM
	 * TODO([email protected]): Figure out a way to get the text base
	 * correctly here, and in the device-tree binman definition.
	 *
	 * Also consider using FIT so we get the correct image length and
	 * parameters.
	 */
	memcpy((char *)target, (char *)0xfff00000, 0x100000);

	/* Jump to U-Boot */
	func((ulong)pgtable, 0, (ulong)target);

	return -EFAULT;
}

#ifdef CONFIG_SMP
static int enable_smis(struct udevice *cpu, void *unused)
{
	return 0;
}

static struct mp_flight_record mp_steps[] = {
	MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
	/* Wait for APs to finish initialization before proceeding */
	MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
};

int x86_mp_init(void)
{
	struct mp_params mp_params;

	mp_params.parallel_microcode_load = 0,
	mp_params.flight_plan = &mp_steps[0];
	mp_params.num_records = ARRAY_SIZE(mp_steps);
	mp_params.microcode_pointer = 0;

	if (mp_init(&mp_params)) {
		printf("Warning: MP init failure\n");
		return -EIO;
	}

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
be059e88 SG	2	/*
	3	* (C) Copyright 2008-2011
	4	* Graeme Russ, <[email protected]>
	5	*
	6	* (C) Copyright 2002
	7	* Daniel Engström, Omicron Ceti AB, <[email protected]>
	8	*
	9	* (C) Copyright 2002
	10	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	11	* Marius Groeger <[email protected]>
	12	*
	13	* (C) Copyright 2002
	14	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	15	* Alex Zuepke <[email protected]>
	16	*
	17	* Part of this file is adapted from coreboot
	18	* src/arch/x86/lib/cpu.c
be059e88 SG	19	*/
	20
	21	#include <common.h>
9edefc27	22	#include <cpu_func.h>
35a3f871	23	#include <init.h>
be059e88	24	#include <malloc.h>
caca13f6	25	#include <spl.h>
be059e88 SG	26	#include <asm/control_regs.h>
	27	#include <asm/cpu.h>
	28	#include <asm/mp.h>
	29	#include <asm/msr.h>
	30	#include <asm/mtrr.h>
	31	#include <asm/processor-flags.h>
	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
	35	/*
	36	* Constructor for a conventional segment GDT (or LDT) entry
	37	* This is a macro so it can be used in initialisers
	38	*/
	39	#define GDT_ENTRY(flags, base, limit) \
	40	((((base) & 0xff000000ULL) << (56-24)) \| \
	41	(((flags) & 0x0000f0ffULL) << 40) \| \
	42	(((limit) & 0x000f0000ULL) << (48-16)) \| \
	43	(((base) & 0x00ffffffULL) << 16) \| \
	44	(((limit) & 0x0000ffffULL)))
	45
	46	struct gdt_ptr {
	47	u16 len;
	48	u32 ptr;
	49	} __packed;
	50
	51	struct cpu_device_id {
	52	unsigned vendor;
	53	unsigned device;
	54	};
	55
	56	struct cpuinfo_x86 {
	57	uint8_t x86; /* CPU family */
	58	uint8_t x86_vendor; /* CPU vendor */
	59	uint8_t x86_model;
	60	uint8_t x86_mask;
	61	};
	62
caca13f6 SG	63	/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
caca13f6 SG	64	#ifndef CONFIG_TPL_BUILD
be059e88 SG	65	/*
	66	* List of cpu vendor strings along with their normalized
	67	* id values.
	68	*/
	69	static const struct {
	70	int vendor;
	71	const char *name;
	72	} x86_vendors[] = {
	73	{ X86_VENDOR_INTEL, "GenuineIntel", },
	74	{ X86_VENDOR_CYRIX, "CyrixInstead", },
	75	{ X86_VENDOR_AMD, "AuthenticAMD", },
	76	{ X86_VENDOR_UMC, "UMC UMC UMC ", },
	77	{ X86_VENDOR_NEXGEN, "NexGenDriven", },
	78	{ X86_VENDOR_CENTAUR, "CentaurHauls", },
	79	{ X86_VENDOR_RISE, "RiseRiseRise", },
	80	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
	81	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
	82	{ X86_VENDOR_NSC, "Geode by NSC", },
	83	{ X86_VENDOR_SIS, "SiS SiS SiS ", },
	84	};
caca13f6	85	#endif
be059e88 SG	86
	87	static void load_ds(u32 segment)
	88	{
	89	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
	90	}
	91
	92	static void load_es(u32 segment)
	93	{
	94	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
	95	}
	96
	97	static void load_fs(u32 segment)
	98	{
	99	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
	100	}
	101
	102	static void load_gs(u32 segment)
	103	{
	104	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
	105	}
	106
	107	static void load_ss(u32 segment)
	108	{
	109	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
	110	}
	111
	112	static void load_gdt(const u64 *boot_gdt, u16 num_entries)
	113	{
	114	struct gdt_ptr gdt;
	115
	116	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
	117	gdt.ptr = (ulong)boot_gdt;
	118
	119	asm volatile("lgdtl %0\n" : : "m" (gdt));
	120	}
	121
	122	void arch_setup_gd(gd_t *new_gd)
	123	{
	124	u64 *gdt_addr;
	125
	126	gdt_addr = new_gd->arch.gdt;
	127
	128	/*
	129	* CS: code, read/execute, 4 GB, base 0
	130	*
	131	* Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
	132	*/
	133	gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
	134	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
	135
	136	/* DS: data, read/write, 4 GB, base 0 */
	137	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
	138
2fa863e9 MY	139	/*
	140	* FS: data, read/write, sizeof (Global Data Pointer),
	141	* base (Global Data Pointer)
	142	*/
be059e88	143	new_gd->arch.gd_addr = new_gd;
2fa863e9 MY	144	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0x8093,
	145	(ulong)&new_gd->arch.gd_addr,
	146	sizeof(new_gd->arch.gd_addr) - 1);
be059e88 SG	147
	148	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
	149	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
	150
	151	/* 16-bit DS: data, read/write, 64 kB, base 0 */
	152	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
	153
	154	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
	155	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
	156
	157	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
	158	load_ds(X86_GDT_ENTRY_32BIT_DS);
	159	load_es(X86_GDT_ENTRY_32BIT_DS);
	160	load_gs(X86_GDT_ENTRY_32BIT_DS);
	161	load_ss(X86_GDT_ENTRY_32BIT_DS);
	162	load_fs(X86_GDT_ENTRY_32BIT_FS);
	163	}
	164
	165	#ifdef CONFIG_HAVE_FSP
	166	/*
	167	* Setup FSP execution environment GDT
	168	*
	169	* Per Intel FSP external architecture specification, before calling any FSP
	170	* APIs, we need make sure the system is in flat 32-bit mode and both the code
	171	* and data selectors should have full 4GB access range. Here we reuse the one
	172	* we used in arch/x86/cpu/start16.S, and reload the segement registers.
	173	*/
	174	void setup_fsp_gdt(void)
	175	{
	176	load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
	177	load_ds(X86_GDT_ENTRY_32BIT_DS);
	178	load_ss(X86_GDT_ENTRY_32BIT_DS);
	179	load_es(X86_GDT_ENTRY_32BIT_DS);
	180	load_fs(X86_GDT_ENTRY_32BIT_DS);
	181	load_gs(X86_GDT_ENTRY_32BIT_DS);
	182	}
	183	#endif
	184
	185	/*
	186	* Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
	187	* by the fact that they preserve the flags across the division of 5/2.
	188	* PII and PPro exhibit this behavior too, but they have cpuid available.
	189	*/
	190
	191	/*
	192	* Perform the Cyrix 5/2 test. A Cyrix won't change
	193	* the flags, while other 486 chips will.
	194	*/
	195	static inline int test_cyrix_52div(void)
	196	{
	197	unsigned int test;
	198
	199	__asm__ __volatile__(
	200	"sahf\n\t" /* clear flags (%eax = 0x0005) */
	201	"div %b2\n\t" /* divide 5 by 2 */
	202	"lahf" /* store flags into %ah */
	203	: "=a" (test)
	204	: "0" (5), "q" (2)
	205	: "cc");
	206
	207	/* AH is 0x02 on Cyrix after the divide.. */
	208	return (unsigned char) (test >> 8) == 0x02;
	209	}
	210
caca13f6	211	#ifndef CONFIG_TPL_BUILD
be059e88 SG	212	/*
	213	* Detect a NexGen CPU running without BIOS hypercode new enough
	214	* to have CPUID. (Thanks to Herbert Oppmann)
	215	*/
	216	static int deep_magic_nexgen_probe(void)
	217	{
	218	int ret;
	219
	220	__asm__ __volatile__ (
	221	" movw $0x5555, %%ax\n"
	222	" xorw %%dx,%%dx\n"
	223	" movw $2, %%cx\n"
	224	" divw %%cx\n"
	225	" movl $0, %%eax\n"
	226	" jnz 1f\n"
	227	" movl $1, %%eax\n"
	228	"1:\n"
	229	: "=a" (ret) : : "cx", "dx");
	230	return ret;
	231	}
caca13f6	232	#endif
be059e88 SG	233
	234	static bool has_cpuid(void)
	235	{
	236	return flag_is_changeable_p(X86_EFLAGS_ID);
	237	}
	238
	239	static bool has_mtrr(void)
	240	{
	241	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
	242	}
	243
caca13f6	244	#ifndef CONFIG_TPL_BUILD
be059e88 SG	245	static int build_vendor_name(char *vendor_name)
	246	{
	247	struct cpuid_result result;
	248	result = cpuid(0x00000000);
	249	unsigned int name_as_ints = (unsigned int )vendor_name;
	250
	251	name_as_ints[0] = result.ebx;
	252	name_as_ints[1] = result.edx;
	253	name_as_ints[2] = result.ecx;
	254
	255	return result.eax;
	256	}
caca13f6	257	#endif
be059e88 SG	258
	259	static void identify_cpu(struct cpu_device_id *cpu)
	260	{
caca13f6 SG	261	cpu->device = 0; /* fix gcc 4.4.4 warning */
	262
	263	/*
	264	* Do a quick and dirty check to save space - Intel and AMD only and
	265	* just the vendor. This is enough for most TPL code.
	266	*/
	267	if (spl_phase() == PHASE_TPL) {
	268	struct cpuid_result result;
	269
	270	result = cpuid(0x00000000);
	271	switch (result.ecx >> 24) {
	272	case 'l': /* GenuineIntel */
	273	cpu->vendor = X86_VENDOR_INTEL;
	274	break;
	275	case 'D': /* AuthenticAMD */
	276	cpu->vendor = X86_VENDOR_AMD;
	277	break;
	278	default:
	279	cpu->vendor = X86_VENDOR_ANY;
	280	break;
	281	}
	282	return;
	283	}
	284
	285	/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
	286	#ifndef CONFIG_TPL_BUILD
be059e88 SG	287	char vendor_name[16];
	288	int i;
	289
	290	vendor_name[0] = '\0'; /* Unset */
be059e88 SG	291
	292	/* Find the id and vendor_name */
	293	if (!has_cpuid()) {
	294	/* Its a 486 if we can modify the AC flag */
	295	if (flag_is_changeable_p(X86_EFLAGS_AC))
	296	cpu->device = 0x00000400; /* 486 */
	297	else
	298	cpu->device = 0x00000300; /* 386 */
	299	if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
	300	memcpy(vendor_name, "CyrixInstead", 13);
	301	/* If we ever care we can enable cpuid here */
	302	}
	303	/* Detect NexGen with old hypercode */
	304	else if (deep_magic_nexgen_probe())
	305	memcpy(vendor_name, "NexGenDriven", 13);
caca13f6 SG	306	} else {
caca13f6 SG	307	int cpuid_level;
be059e88 SG	308
	309	cpuid_level = build_vendor_name(vendor_name);
	310	vendor_name[12] = '\0';
	311
	312	/* Intel-defined flags: level 0x00000001 */
	313	if (cpuid_level >= 0x00000001) {
	314	cpu->device = cpuid_eax(0x00000001);
	315	} else {
	316	/* Have CPUID level 0 only unheard of */
	317	cpu->device = 0x00000400;
	318	}
	319	}
	320	cpu->vendor = X86_VENDOR_UNKNOWN;
	321	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
	322	if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
	323	cpu->vendor = x86_vendors[i].vendor;
	324	break;
	325	}
	326	}
caca13f6	327	#endif
be059e88 SG	328	}
	329
	330	static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
	331	{
	332	c->x86 = (tfms >> 8) & 0xf;
	333	c->x86_model = (tfms >> 4) & 0xf;
	334	c->x86_mask = tfms & 0xf;
	335	if (c->x86 == 0xf)
	336	c->x86 += (tfms >> 20) & 0xff;
	337	if (c->x86 >= 0x6)
	338	c->x86_model += ((tfms >> 16) & 0xF) << 4;
	339	}
	340
	341	u32 cpu_get_family_model(void)
	342	{
	343	return gd->arch.x86_device & 0x0fff0ff0;
	344	}
	345
	346	u32 cpu_get_stepping(void)
	347	{
	348	return gd->arch.x86_mask;
	349	}
	350
c0069e9a SG	351	/* initialise FPU, reset EM, set MP and NE */
c0069e9a SG	352	static void setup_cpu_features(void)
be059e88 SG	353	{
	354	const u32 em_rst = ~X86_CR0_EM;
	355	const u32 mp_ne_set = X86_CR0_MP \| X86_CR0_NE;
	356
c0069e9a SG	357	asm ("fninit\n" \
	358	"movl %%cr0, %%eax\n" \
	359	"andl %0, %%eax\n" \
	360	"orl %1, %%eax\n" \
	361	"movl %%eax, %%cr0\n" \
	362	: : "i" (em_rst), "i" (mp_ne_set) : "eax");
	363	}
be059e88	364
c0069e9a SG	365	static void setup_identity(void)
c0069e9a SG	366	{
be059e88 SG	367	/* identify CPU via cpuid and store the decoded info into gd->arch */
	368	if (has_cpuid()) {
	369	struct cpu_device_id cpu;
	370	struct cpuinfo_x86 c;
	371
	372	identify_cpu(&cpu);
	373	get_fms(&c, cpu.device);
	374	gd->arch.x86 = c.x86;
	375	gd->arch.x86_vendor = cpu.vendor;
	376	gd->arch.x86_model = c.x86_model;
	377	gd->arch.x86_mask = c.x86_mask;
	378	gd->arch.x86_device = cpu.device;
	379
	380	gd->arch.has_mtrr = has_mtrr();
	381	}
c0069e9a SG	382	}
	383
	384	/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
	385	static void setup_pci_ram_top(void)
	386	{
be059e88	387	gd->pci_ram_top = 0x80000000U;
c0069e9a SG	388	}
	389
	390	static void setup_mtrr(void)
	391	{
	392	u64 mtrr_cap;
be059e88 SG	393
be059e88 SG	394	/* Configure fixed range MTRRs for some legacy regions */
c0069e9a SG	395	if (!gd->arch.has_mtrr)
	396	return;
	397
	398	mtrr_cap = native_read_msr(MTRR_CAP_MSR);
	399	if (mtrr_cap & MTRR_CAP_FIX) {
	400	/* Mark the VGA RAM area as uncacheable */
	401	native_write_msr(MTRR_FIX_16K_A0000_MSR,
	402	MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
	403	MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
	404
	405	/*
	406	* Mark the PCI ROM area as cacheable to improve ROM
	407	* execution performance.
	408	*/
	409	native_write_msr(MTRR_FIX_4K_C0000_MSR,
	410	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
	411	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
	412	native_write_msr(MTRR_FIX_4K_C8000_MSR,
	413	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
	414	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
	415	native_write_msr(MTRR_FIX_4K_D0000_MSR,
	416	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
	417	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
	418	native_write_msr(MTRR_FIX_4K_D8000_MSR,
	419	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
	420	MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
	421
	422	/* Enable the fixed range MTRRs */
	423	msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
be059e88	424	}
c0069e9a SG	425	}
c0069e9a SG	426
ece3a460 SG	427	int x86_cpu_init_tpl(void)
	428	{
	429	setup_cpu_features();
	430	setup_identity();
	431
	432	return 0;
	433	}
	434
c0069e9a SG	435	int x86_cpu_init_f(void)
	436	{
	437	if (ll_boot_init())
	438	setup_cpu_features();
	439	setup_identity();
	440	setup_mtrr();
	441	setup_pci_ram_top();
be059e88	442
be059e88	443	/* Set up the i8254 timer if required */
c0069e9a SG	444	if (IS_ENABLED(CONFIG_I8254_TIMER))
	445	i8254_init();
	446
	447	return 0;
	448	}
	449
33139a0b SG	450	long detect_coreboot_table_at(ulong start, ulong size)
	451	{
	452	u32 ptr, end;
	453
	454	size /= 4;
	455	for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
	456	if (ptr == 0x4f49424c) / "LBIO" */
	457	return (long)ptr;
	458	}
	459
	460	return -ENOENT;
	461	}
	462
	463	long locate_coreboot_table(void)
	464	{
	465	long addr;
	466
	467	/* We look for LBIO in the first 4K of RAM and again at 960KB */
	468	addr = detect_coreboot_table_at(0x0, 0x1000);
	469	if (addr < 0)
	470	addr = detect_coreboot_table_at(0xf0000, 0x1000);
	471
	472	return addr;
	473	}
	474
c0069e9a SG	475	int x86_cpu_reinit_f(void)
	476	{
	477	setup_identity();
	478	setup_pci_ram_top();
cfe7a106 SG	479	if (locate_coreboot_table() >= 0)
cfe7a106 SG	480	gd->flags \|= GD_FLG_SKIP_LL_INIT;
be059e88 SG	481
	482	return 0;
	483	}
	484
	485	void x86_enable_caches(void)
	486	{
	487	unsigned long cr0;
	488
	489	cr0 = read_cr0();
	490	cr0 &= ~(X86_CR0_NW \| X86_CR0_CD);
	491	write_cr0(cr0);
	492	wbinvd();
	493	}
	494	void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
	495
	496	void x86_disable_caches(void)
	497	{
	498	unsigned long cr0;
	499
	500	cr0 = read_cr0();
	501	cr0 \|= X86_CR0_NW \| X86_CR0_CD;
	502	wbinvd();
	503	write_cr0(cr0);
	504	wbinvd();
	505	}
	506	void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
	507
	508	int dcache_status(void)
	509	{
	510	return !(read_cr0() & X86_CR0_CD);
	511	}
	512
	513	void cpu_enable_paging_pae(ulong cr3)
	514	{
	515	__asm__ __volatile__(
	516	/* Load the page table address */
	517	"movl %0, %%cr3\n"
	518	/* Enable pae */
	519	"movl %%cr4, %%eax\n"
	520	"orl $0x00000020, %%eax\n"
	521	"movl %%eax, %%cr4\n"
	522	/* Enable paging */
	523	"movl %%cr0, %%eax\n"
	524	"orl $0x80000000, %%eax\n"
	525	"movl %%eax, %%cr0\n"
	526	:
	527	: "r" (cr3)
	528	: "eax");
	529	}
	530
	531	void cpu_disable_paging_pae(void)
	532	{
	533	/* Turn off paging */
	534	__asm__ __volatile__ (
	535	/* Disable paging */
	536	"movl %%cr0, %%eax\n"
	537	"andl $0x7fffffff, %%eax\n"
	538	"movl %%eax, %%cr0\n"
	539	/* Disable pae */
	540	"movl %%cr4, %%eax\n"
	541	"andl $0xffffffdf, %%eax\n"
	542	"movl %%eax, %%cr4\n"
	543	:
	544	:
545	: "eax");
546	}
547
548	static bool can_detect_long_mode(void)
549	{
550	return cpuid_eax(0x80000000) > 0x80000000UL;
551	}
552
553	static bool has_long_mode(void)
554	{
555	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
556	}
557
558	int cpu_has_64bit(void)
559	{
560	return has_cpuid() && can_detect_long_mode() &&
561	has_long_mode();
562	}
563
dbb0696b	564	#define PAGETABLE_BASE 0x80000
be059e88 SG	565	#define PAGETABLE_SIZE (6 * 4096)
	566
	567	/**
	568	* build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
	569	*
	570	* @pgtable: Pointer to a 24iKB block of memory
	571	*/
	572	static void build_pagetable(uint32_t *pgtable)
	573	{
	574	uint i;
	575
	576	memset(pgtable, '\0', PAGETABLE_SIZE);
	577
	578	/* Level 4 needs a single entry */
	579	pgtable[0] = (ulong)&pgtable[1024] + 7;
	580
	581	/* Level 3 has one 64-bit entry for each GiB of memory */
	582	for (i = 0; i < 4; i++)
	583	pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
	584
	585	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
	586	for (i = 0; i < 2048; i++)
	587	pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
	588	}
	589
	590	int cpu_jump_to_64bit(ulong setup_base, ulong target)
	591	{
	592	uint32_t *pgtable;
	593
	594	pgtable = memalign(4096, PAGETABLE_SIZE);
	595	if (!pgtable)
	596	return -ENOMEM;
	597
	598	build_pagetable(pgtable);
	599	cpu_call64((ulong)pgtable, setup_base, target);
	600	free(pgtable);
	601
	602	return -EFAULT;
	603	}
	604
fa5fcb3b SG	605	/*
	606	* Jump from SPL to U-Boot
	607	*
	608	* This function is work-in-progress with many issues to resolve.
	609	*
	610	* It works by setting up several regions:
	611	* ptr - a place to put the code that jumps into 64-bit mode
	612	* gdt - a place to put the global descriptor table
	613	* pgtable - a place to put the page tables
	614	*
	615	* The cpu_call64() code is copied from ROM and then manually patched so that
	616	* it has the correct GDT address in RAM. U-Boot is copied from ROM into
	617	* its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
	618	* which changes to 64-bit mode and starts U-Boot.
	619	*/
	620	int cpu_jump_to_64bit_uboot(ulong target)
	621	{
	622	typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
	623	uint32_t *pgtable;
	624	func_t func;
91683260	625	char *ptr;
fa5fcb3b	626
dbb0696b	627	pgtable = (uint32_t *)PAGETABLE_BASE;
fa5fcb3b SG	628
	629	build_pagetable(pgtable);
	630
91683260 BM	631	extern long call64_stub_size;
	632	ptr = malloc(call64_stub_size);
	633	if (!ptr) {
	634	printf("Failed to allocate the cpu_call64 stub\n");
	635	return -ENOMEM;
	636	}
91683260	637	memcpy(ptr, cpu_call64, call64_stub_size);
fa5fcb3b	638
fa5fcb3b	639	func = (func_t)ptr;
fa5fcb3b SG	640
	641	/*
	642	* Copy U-Boot from ROM
	643	* TODO([email protected]): Figure out a way to get the text base
	644	* correctly here, and in the device-tree binman definition.
	645	*
	646	* Also consider using FIT so we get the correct image length and
	647	* parameters.
	648	*/
	649	memcpy((char )target, (char )0xfff00000, 0x100000);
	650
	651	/* Jump to U-Boot */
	652	func((ulong)pgtable, 0, (ulong)target);
	653
	654	return -EFAULT;
	655	}
	656
be059e88 SG	657	#ifdef CONFIG_SMP
	658	static int enable_smis(struct udevice cpu, void unused)
	659	{
	660	return 0;
	661	}
	662
	663	static struct mp_flight_record mp_steps[] = {
	664	MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
	665	/* Wait for APs to finish initialization before proceeding */
	666	MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
	667	};
	668
	669	int x86_mp_init(void)
	670	{
	671	struct mp_params mp_params;
	672
	673	mp_params.parallel_microcode_load = 0,
	674	mp_params.flight_plan = &mp_steps[0];
	675	mp_params.num_records = ARRAY_SIZE(mp_steps);
	676	mp_params.microcode_pointer = 0;
	677
	678	if (mp_init(&mp_params)) {
	679	printf("Warning: MP init failure\n");
	680	return -EIO;
	681	}
	682
	683	return 0;
	684	}
	685	#endif