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c67bee14 SB |
1 | /* |
2 | * (C) Copyright 2000-2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, [email protected]. | |
4 | * | |
5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
6 | * TsiChung Liew ([email protected]) | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/arch/imx-regs.h> | |
e4d34492 | 29 | #include <asm/arch/clock.h> |
c67bee14 | 30 | |
29565326 JR |
31 | #ifdef CONFIG_FSL_ESDHC |
32 | DECLARE_GLOBAL_DATA_PTR; | |
33 | #endif | |
34 | ||
c67bee14 SB |
35 | int get_clocks(void) |
36 | { | |
c67bee14 | 37 | #ifdef CONFIG_FSL_ESDHC |
5c23712d | 38 | #ifdef CONFIG_FSL_USDHC |
32384656 | 39 | #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR |
e9adeca3 | 40 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
32384656 | 41 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR |
e9adeca3 | 42 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
32384656 | 43 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR |
e9adeca3 | 44 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
32384656 | 45 | #else |
e9adeca3 | 46 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
32384656 BT |
47 | #endif |
48 | #else | |
49 | #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR | |
e9adeca3 | 50 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
32384656 | 51 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR |
e9adeca3 | 52 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
32384656 | 53 | #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR |
e9adeca3 | 54 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
5c23712d | 55 | #else |
e9adeca3 | 56 | gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
32384656 | 57 | #endif |
5c23712d | 58 | #endif |
c67bee14 SB |
59 | #endif |
60 | return 0; | |
61 | } |