[J-u-boot.git] / drivers / spi / tegra210_qspi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * NVIDIA Tegra210 QSPI controller driver
 *
 * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
 *
 */

#include <dm.h>
#include <log.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#include <spi.h>
#include <fdtdec.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include "tegra_spi.h"

DECLARE_GLOBAL_DATA_PTR;

/* COMMAND1 */
#define QSPI_CMD1_GO			BIT(31)
#define QSPI_CMD1_M_S			BIT(30)
#define QSPI_CMD1_MODE_MASK		GENMASK(1,0)
#define QSPI_CMD1_MODE_SHIFT		28
#define QSPI_CMD1_CS_SEL_MASK		GENMASK(1,0)
#define QSPI_CMD1_CS_SEL_SHIFT		26
#define QSPI_CMD1_CS_POL_INACTIVE0	BIT(22)
#define QSPI_CMD1_CS_SW_HW		BIT(21)
#define QSPI_CMD1_CS_SW_VAL		BIT(20)
#define QSPI_CMD1_IDLE_SDA_MASK		GENMASK(1,0)
#define QSPI_CMD1_IDLE_SDA_SHIFT	18
#define QSPI_CMD1_BIDIR			BIT(17)
#define QSPI_CMD1_LSBI_FE		BIT(16)
#define QSPI_CMD1_LSBY_FE		BIT(15)
#define QSPI_CMD1_BOTH_EN_BIT		BIT(14)
#define QSPI_CMD1_BOTH_EN_BYTE		BIT(13)
#define QSPI_CMD1_RX_EN			BIT(12)
#define QSPI_CMD1_TX_EN			BIT(11)
#define QSPI_CMD1_PACKED		BIT(5)
#define QSPI_CMD1_BITLEN_MASK		GENMASK(4,0)
#define QSPI_CMD1_BITLEN_SHIFT		0

/* COMMAND2 */
#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT	10
#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK	GENMASK(14,10)
#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT	0
#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK	GENMASK(7,0)

/* TRANSFER STATUS */
#define QSPI_XFER_STS_RDY		BIT(30)

/* FIFO STATUS */
#define QSPI_FIFO_STS_CS_INACTIVE	BIT(31)
#define QSPI_FIFO_STS_FRAME_END		BIT(30)
#define QSPI_FIFO_STS_RX_FIFO_FLUSH	BIT(15)
#define QSPI_FIFO_STS_TX_FIFO_FLUSH	BIT(14)
#define QSPI_FIFO_STS_ERR		BIT(8)
#define QSPI_FIFO_STS_TX_FIFO_OVF	BIT(7)
#define QSPI_FIFO_STS_TX_FIFO_UNR	BIT(6)
#define QSPI_FIFO_STS_RX_FIFO_OVF	BIT(5)
#define QSPI_FIFO_STS_RX_FIFO_UNR	BIT(4)
#define QSPI_FIFO_STS_TX_FIFO_FULL	BIT(3)
#define QSPI_FIFO_STS_TX_FIFO_EMPTY	BIT(2)
#define QSPI_FIFO_STS_RX_FIFO_FULL	BIT(1)
#define QSPI_FIFO_STS_RX_FIFO_EMPTY	BIT(0)

#define QSPI_TIMEOUT		1000

struct qspi_regs {
	u32 command1;	/* 000:QSPI_COMMAND1 register */
	u32 command2;	/* 004:QSPI_COMMAND2 register */
	u32 timing1;	/* 008:QSPI_CS_TIM1 register */
	u32 timing2;	/* 00c:QSPI_CS_TIM2 register */
	u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
	u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
	u32 tx_data;	/* 018:QSPI_TX_DATA register */
	u32 rx_data;	/* 01c:QSPI_RX_DATA register */
	u32 dma_ctl;	/* 020:QSPI_DMA_CTL register */
	u32 dma_blk;	/* 024:QSPI_DMA_BLK register */
	u32 rsvd[56];	/* 028-107 reserved */
	u32 tx_fifo;	/* 108:QSPI_FIFO1 register */
	u32 rsvd2[31];	/* 10c-187 reserved */
	u32 rx_fifo;	/* 188:QSPI_FIFO2 register */
	u32 spare_ctl;	/* 18c:QSPI_SPARE_CTRL register */
};

struct tegra210_qspi_priv {
	struct qspi_regs *regs;
	unsigned int freq;
	unsigned int mode;
	int periph_id;
	int valid;
	int last_transaction_us;
};

static int tegra210_qspi_of_to_plat(struct udevice *bus)
{
	struct tegra_spi_plat *plat = dev_get_plat(bus);

	plat->base = dev_read_addr(bus);
	plat->periph_id = clock_decode_periph_id(bus);

	if (plat->periph_id == PERIPH_ID_NONE) {
		debug("%s: could not decode periph id %d\n", __func__,
		      plat->periph_id);
		return -FDT_ERR_NOTFOUND;
	}

	/* Use 500KHz as a suitable default */
	plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
					       500000);
	plat->deactivate_delay_us = dev_read_u32_default(bus,
							 "spi-deactivate-delay",
							 0);
	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	      __func__, plat->base, plat->periph_id, plat->frequency,
	      plat->deactivate_delay_us);

	return 0;
}

static int tegra210_qspi_probe(struct udevice *bus)
{
	struct tegra_spi_plat *plat = dev_get_plat(bus);
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);

	priv->regs = (struct qspi_regs *)plat->base;
	struct qspi_regs *regs = priv->regs;

	priv->last_transaction_us = timer_get_us();
	priv->freq = plat->frequency;
	priv->periph_id = plat->periph_id;

	debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
	      priv->periph_id);
	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);

	/* Set tap delays here, clock change above resets QSPI controller */
	u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) |
		   (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
	writel(reg, &regs->command2);
	debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));

	return 0;
}

static int tegra210_qspi_claim_bus(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	struct qspi_regs *regs = priv->regs;

	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));

	/* Set master mode and sw controlled CS */
	setbits_le32(&regs->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW |
		     (priv->mode << QSPI_CMD1_MODE_SHIFT));
	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));

	return 0;
}

/**
 * Activate the CS by driving it LOW
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_activate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct tegra_spi_plat *pdata = dev_get_plat(bus);
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);

	/* If it's too soon to do another transaction, wait */
	if (pdata->deactivate_delay_us &&
	    priv->last_transaction_us) {
		ulong delay_us;		/* The delay completed so far */
		delay_us = timer_get_us() - priv->last_transaction_us;
		if (delay_us < pdata->deactivate_delay_us)
			udelay(pdata->deactivate_delay_us - delay_us);
	}

	clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
}

/**
 * Deactivate the CS by driving it HIGH
 *
 * @param slave	Pointer to spi_slave to which controller has to
 *		communicate with
 */
static void spi_cs_deactivate(struct udevice *dev)
{
	struct udevice *bus = dev->parent;
	struct tegra_spi_plat *pdata = dev_get_plat(bus);
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);

	setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);

	/* Remember time of this transaction so we can honour the bus delay */
	if (pdata->deactivate_delay_us)
		priv->last_transaction_us = timer_get_us();

	debug("Deactivate CS, bus '%s'\n", bus->name);
}

static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
			     const void *data_out, void *data_in,
			     unsigned long flags)
{
	struct udevice *bus = dev->parent;
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	struct qspi_regs *regs = priv->regs;
	u32 reg, tmpdout, tmpdin = 0;
	const u8 *dout = data_out;
	u8 *din = data_in;
	int num_bytes, tm, ret;

	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
	      __func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
	if (bitlen % 8)
		return -1;
	num_bytes = bitlen / 8;

	ret = 0;

	/* clear all error status bits */
	reg = readl(&regs->fifo_status);
	writel(reg, &regs->fifo_status);

	/* flush RX/TX FIFOs */
	setbits_le32(&regs->fifo_status,
		     (QSPI_FIFO_STS_RX_FIFO_FLUSH |
		      QSPI_FIFO_STS_TX_FIFO_FLUSH));

	tm = QSPI_TIMEOUT;
	while ((tm && readl(&regs->fifo_status) &
		      (QSPI_FIFO_STS_RX_FIFO_FLUSH |
		       QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
		tm--;
		udelay(1);
	}

	if (!tm) {
		printf("%s: timeout during QSPI FIFO flush!\n",
		       __func__);
		return -1;
	}

	/*
	 * Notes:
	 *   1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
	 *   2. don't set RX_EN and TX_EN yet.
	 *      (SW needs to make sure that while programming the blk_size,
	 *       tx_en and rx_en bits must be zero)
	 *      [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
	 *	       i.e., both dout and din are not NULL.
	 */
	clrsetbits_le32(&regs->command1,
			(QSPI_CMD1_LSBI_FE | QSPI_CMD1_LSBY_FE |
			 QSPI_CMD1_RX_EN | QSPI_CMD1_TX_EN),
			(spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));

	/* set xfer size to 1 block (32 bits) */
	writel(0, &regs->dma_blk);

	if (flags & SPI_XFER_BEGIN)
		spi_cs_activate(dev);

	/* handle data in 32-bit chunks */
	while (num_bytes > 0) {
		int bytes;

		tmpdout = 0;
		bytes = (num_bytes > 4) ?  4 : num_bytes;

		if (dout != NULL) {
			memcpy((void *)&tmpdout, (void *)dout, bytes);
			dout += bytes;
			num_bytes -= bytes;
			writel(tmpdout, &regs->tx_fifo);
			setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
		}

		if (din != NULL)
			setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);

		/* clear ready bit */
		setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);

		clrsetbits_le32(&regs->command1,
				QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
				(bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);

		/* Need to stabilize other reg bits before GO bit set.
		 * As per the TRM:
		 * "For successful operation at various freq combinations,
		 * a minimum of 4-5 spi_clk cycle delay might be required
		 * before enabling the PIO or DMA bits. The worst case delay
		 * calculation can be done considering slowest qspi_clk as
		 * 1MHz. Based on that 1us delay should be enough before
		 * enabling PIO or DMA." Padded another 1us for safety.
		 */
		udelay(2);
		setbits_le32(&regs->command1, QSPI_CMD1_GO);
		udelay(1);

		/*
		 * Wait for SPI transmit FIFO to empty, or to time out.
		 * The RX FIFO status will be read and cleared last
		 */
		for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
			u32 fifo_status, xfer_status;

			xfer_status = readl(&regs->xfer_status);
			if (!(xfer_status & QSPI_XFER_STS_RDY))
				continue;

			fifo_status = readl(&regs->fifo_status);
			if (fifo_status & QSPI_FIFO_STS_ERR) {
				debug("%s: got a fifo error: ", __func__);
				if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
					debug("tx FIFO overflow ");
				if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
					debug("tx FIFO underrun ");
				if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
					debug("rx FIFO overflow ");
				if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
					debug("rx FIFO underrun ");
				if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
					debug("tx FIFO full ");
				if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
					debug("tx FIFO empty ");
				if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
					debug("rx FIFO full ");
				if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
					debug("rx FIFO empty ");
				debug("\n");
				break;
			}

			if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
				tmpdin = readl(&regs->rx_fifo);
				if (din != NULL) {
					memcpy(din, &tmpdin, bytes);
					din += bytes;
					num_bytes -= bytes;
				}
			}
			break;
		}

		if (tm >= QSPI_TIMEOUT)
			ret = tm;

		/* clear ACK RDY, etc. bits */
		writel(readl(&regs->fifo_status), &regs->fifo_status);
	}

	if (flags & SPI_XFER_END)
		spi_cs_deactivate(dev);

	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
	      __func__, tmpdin, readl(&regs->fifo_status));

	if (ret) {
		printf("%s: timeout during SPI transfer, tm %d\n",
		       __func__, ret);
		return -1;
	}

	return ret;
}

static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
{
	struct tegra_spi_plat *plat = dev_get_plat(bus);
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);

	if (speed > plat->frequency)
		speed = plat->frequency;
	priv->freq = speed;
	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);

	return 0;
}

static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
{
	struct tegra210_qspi_priv *priv = dev_get_priv(bus);

	priv->mode = mode;
	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);

	return 0;
}

static const struct dm_spi_ops tegra210_qspi_ops = {
	.claim_bus	= tegra210_qspi_claim_bus,
	.xfer		= tegra210_qspi_xfer,
	.set_speed	= tegra210_qspi_set_speed,
	.set_mode	= tegra210_qspi_set_mode,
	/*
	 * cs_info is not needed, since we require all chip selects to be
	 * in the device tree explicitly
	 */
};

static const struct udevice_id tegra210_qspi_ids[] = {
	{ .compatible = "nvidia,tegra210-qspi" },
	{ }
};

U_BOOT_DRIVER(tegra210_qspi) = {
	.name = "tegra210-qspi",
	.id = UCLASS_SPI,
	.of_match = tegra210_qspi_ids,
	.ops = &tegra210_qspi_ops,
	.of_to_plat = tegra210_qspi_of_to_plat,
	.plat_auto	= sizeof(struct tegra_spi_plat),
	.priv_auto	= sizeof(struct tegra210_qspi_priv),
	.per_child_auto	= sizeof(struct spi_slave),
	.probe = tegra210_qspi_probe,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4e675ff2 TW	2	/*
	3	* NVIDIA Tegra210 QSPI controller driver
	4	*
b1747fdb	5	* (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com>
3c8cf240	6	*
4e675ff2 TW	7	*/
4e675ff2 TW	8
4e675ff2	9	#include <dm.h>
f7ae49fc	10	#include <log.h>
1045315d	11	#include <time.h>
401d1c4f	12	#include <asm/global_data.h>
4e675ff2 TW	13	#include <asm/io.h>
	14	#include <asm/arch/clock.h>
	15	#include <asm/arch-tegra/clk_rst.h>
	16	#include <spi.h>
	17	#include <fdtdec.h>
cd93d625	18	#include <linux/bitops.h>
c05ed00a	19	#include <linux/delay.h>
4e675ff2 TW	20	#include "tegra_spi.h"
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
	24	/* COMMAND1 */
	25	#define QSPI_CMD1_GO BIT(31)
	26	#define QSPI_CMD1_M_S BIT(30)
	27	#define QSPI_CMD1_MODE_MASK GENMASK(1,0)
	28	#define QSPI_CMD1_MODE_SHIFT 28
	29	#define QSPI_CMD1_CS_SEL_MASK GENMASK(1,0)
	30	#define QSPI_CMD1_CS_SEL_SHIFT 26
	31	#define QSPI_CMD1_CS_POL_INACTIVE0 BIT(22)
	32	#define QSPI_CMD1_CS_SW_HW BIT(21)
	33	#define QSPI_CMD1_CS_SW_VAL BIT(20)
	34	#define QSPI_CMD1_IDLE_SDA_MASK GENMASK(1,0)
	35	#define QSPI_CMD1_IDLE_SDA_SHIFT 18
	36	#define QSPI_CMD1_BIDIR BIT(17)
	37	#define QSPI_CMD1_LSBI_FE BIT(16)
	38	#define QSPI_CMD1_LSBY_FE BIT(15)
	39	#define QSPI_CMD1_BOTH_EN_BIT BIT(14)
	40	#define QSPI_CMD1_BOTH_EN_BYTE BIT(13)
	41	#define QSPI_CMD1_RX_EN BIT(12)
	42	#define QSPI_CMD1_TX_EN BIT(11)
	43	#define QSPI_CMD1_PACKED BIT(5)
	44	#define QSPI_CMD1_BITLEN_MASK GENMASK(4,0)
	45	#define QSPI_CMD1_BITLEN_SHIFT 0
	46
	47	/* COMMAND2 */
2fcc3ba1 TW	48	#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10
	49	#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10)
	50	#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0
	51	#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0)
4e675ff2 TW	52
	53	/* TRANSFER STATUS */
	54	#define QSPI_XFER_STS_RDY BIT(30)
	55
	56	/* FIFO STATUS */
	57	#define QSPI_FIFO_STS_CS_INACTIVE BIT(31)
	58	#define QSPI_FIFO_STS_FRAME_END BIT(30)
	59	#define QSPI_FIFO_STS_RX_FIFO_FLUSH BIT(15)
	60	#define QSPI_FIFO_STS_TX_FIFO_FLUSH BIT(14)
	61	#define QSPI_FIFO_STS_ERR BIT(8)
	62	#define QSPI_FIFO_STS_TX_FIFO_OVF BIT(7)
	63	#define QSPI_FIFO_STS_TX_FIFO_UNR BIT(6)
	64	#define QSPI_FIFO_STS_RX_FIFO_OVF BIT(5)
	65	#define QSPI_FIFO_STS_RX_FIFO_UNR BIT(4)
	66	#define QSPI_FIFO_STS_TX_FIFO_FULL BIT(3)
	67	#define QSPI_FIFO_STS_TX_FIFO_EMPTY BIT(2)
	68	#define QSPI_FIFO_STS_RX_FIFO_FULL BIT(1)
	69	#define QSPI_FIFO_STS_RX_FIFO_EMPTY BIT(0)
	70
	71	#define QSPI_TIMEOUT 1000
	72
	73	struct qspi_regs {
	74	u32 command1; /* 000:QSPI_COMMAND1 register */
	75	u32 command2; /* 004:QSPI_COMMAND2 register */
	76	u32 timing1; /* 008:QSPI_CS_TIM1 register */
	77	u32 timing2; /* 00c:QSPI_CS_TIM2 register */
	78	u32 xfer_status;/* 010:QSPI_TRANS_STATUS register */
	79	u32 fifo_status;/* 014:QSPI_FIFO_STATUS register */
	80	u32 tx_data; /* 018:QSPI_TX_DATA register */
	81	u32 rx_data; /* 01c:QSPI_RX_DATA register */
	82	u32 dma_ctl; /* 020:QSPI_DMA_CTL register */
	83	u32 dma_blk; /* 024:QSPI_DMA_BLK register */
	84	u32 rsvd[56]; /* 028-107 reserved */
	85	u32 tx_fifo; /* 108:QSPI_FIFO1 register */
	86	u32 rsvd2[31]; /* 10c-187 reserved */
	87	u32 rx_fifo; /* 188:QSPI_FIFO2 register */
	88	u32 spare_ctl; /* 18c:QSPI_SPARE_CTRL register */
	89	};
	90
	91	struct tegra210_qspi_priv {
	92	struct qspi_regs *regs;
	93	unsigned int freq;
	94	unsigned int mode;
	95	int periph_id;
	96	int valid;
	97	int last_transaction_us;
	98	};
	99
d1998a9f	100	static int tegra210_qspi_of_to_plat(struct udevice *bus)
4e675ff2	101	{
0fd3d911	102	struct tegra_spi_plat *plat = dev_get_plat(bus);
4e675ff2	103
b1747fdb	104	plat->base = dev_read_addr(bus);
000f15fa	105	plat->periph_id = clock_decode_periph_id(bus);
4e675ff2 TW	106
	107	if (plat->periph_id == PERIPH_ID_NONE) {
	108	debug("%s: could not decode periph id %d\n", __func__,
	109	plat->periph_id);
	110	return -FDT_ERR_NOTFOUND;
	111	}
	112
	113	/* Use 500KHz as a suitable default */
b1747fdb TW	114	plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
	115	500000);
	116	plat->deactivate_delay_us = dev_read_u32_default(bus,
	117	"spi-deactivate-delay",
	118	0);
4e675ff2 TW	119	debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
	120	__func__, plat->base, plat->periph_id, plat->frequency,
	121	plat->deactivate_delay_us);
	122
	123	return 0;
	124	}
	125
	126	static int tegra210_qspi_probe(struct udevice *bus)
	127	{
8a8d24bd	128	struct tegra_spi_plat *plat = dev_get_plat(bus);
4e675ff2 TW	129	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	130
	131	priv->regs = (struct qspi_regs *)plat->base;
2fcc3ba1	132	struct qspi_regs *regs = priv->regs;
4e675ff2 TW	133
	134	priv->last_transaction_us = timer_get_us();
	135	priv->freq = plat->frequency;
	136	priv->periph_id = plat->periph_id;
	137
2fcc3ba1 TW	138	debug("%s: Freq = %u, id = %d\n", __func__, priv->freq,
2fcc3ba1 TW	139	priv->periph_id);
4832c7f5 SW	140	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
	141	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
	142
2fcc3ba1 TW	143	/* Set tap delays here, clock change above resets QSPI controller */
	144	u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) \|
	145	(0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT);
	146	writel(reg, &regs->command2);
	147	debug("%s: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
	148
4e675ff2 TW	149	return 0;
	150	}
	151
3c8cf240	152	static int tegra210_qspi_claim_bus(struct udevice *dev)
4e675ff2	153	{
3c8cf240	154	struct udevice *bus = dev->parent;
4e675ff2 TW	155	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	156	struct qspi_regs *regs = priv->regs;
	157
4e675ff2 TW	158	debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
	159
	160	/* Set master mode and sw controlled CS */
	161	setbits_le32(&regs->command1, QSPI_CMD1_M_S \| QSPI_CMD1_CS_SW_HW \|
	162	(priv->mode << QSPI_CMD1_MODE_SHIFT));
	163	debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
	164
	165	return 0;
	166	}
	167
	168	/**
	169	* Activate the CS by driving it LOW
	170	*
	171	* @param slave Pointer to spi_slave to which controller has to
	172	* communicate with
	173	*/
	174	static void spi_cs_activate(struct udevice *dev)
	175	{
	176	struct udevice *bus = dev->parent;
8a8d24bd	177	struct tegra_spi_plat *pdata = dev_get_plat(bus);
4e675ff2 TW	178	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	179
	180	/* If it's too soon to do another transaction, wait */
	181	if (pdata->deactivate_delay_us &&
	182	priv->last_transaction_us) {
	183	ulong delay_us; /* The delay completed so far */
	184	delay_us = timer_get_us() - priv->last_transaction_us;
	185	if (delay_us < pdata->deactivate_delay_us)
	186	udelay(pdata->deactivate_delay_us - delay_us);
	187	}
	188
	189	clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
	190	}
	191
	192	/**
	193	* Deactivate the CS by driving it HIGH
	194	*
	195	* @param slave Pointer to spi_slave to which controller has to
	196	* communicate with
	197	*/
	198	static void spi_cs_deactivate(struct udevice *dev)
	199	{
	200	struct udevice *bus = dev->parent;
8a8d24bd	201	struct tegra_spi_plat *pdata = dev_get_plat(bus);
4e675ff2 TW	202	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	203
	204	setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL);
	205
	206	/* Remember time of this transaction so we can honour the bus delay */
	207	if (pdata->deactivate_delay_us)
	208	priv->last_transaction_us = timer_get_us();
	209
	210	debug("Deactivate CS, bus '%s'\n", bus->name);
	211	}
	212
	213	static int tegra210_qspi_xfer(struct udevice *dev, unsigned int bitlen,
	214	const void data_out, void data_in,
	215	unsigned long flags)
	216	{
	217	struct udevice *bus = dev->parent;
	218	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	219	struct qspi_regs *regs = priv->regs;
	220	u32 reg, tmpdout, tmpdin = 0;
	221	const u8 *dout = data_out;
	222	u8 *din = data_in;
	223	int num_bytes, tm, ret;
	224
	225	debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
8b85dfc6	226	__func__, dev_seq(bus), spi_chip_select(dev), dout, din, bitlen);
4e675ff2 TW	227	if (bitlen % 8)
	228	return -1;
	229	num_bytes = bitlen / 8;
	230
	231	ret = 0;
	232
	233	/* clear all error status bits */
	234	reg = readl(&regs->fifo_status);
	235	writel(reg, &regs->fifo_status);
	236
	237	/* flush RX/TX FIFOs */
	238	setbits_le32(&regs->fifo_status,
	239	(QSPI_FIFO_STS_RX_FIFO_FLUSH \|
	240	QSPI_FIFO_STS_TX_FIFO_FLUSH));
	241
	242	tm = QSPI_TIMEOUT;
	243	while ((tm && readl(&regs->fifo_status) &
	244	(QSPI_FIFO_STS_RX_FIFO_FLUSH \|
	245	QSPI_FIFO_STS_TX_FIFO_FLUSH))) {
	246	tm--;
	247	udelay(1);
	248	}
	249
	250	if (!tm) {
	251	printf("%s: timeout during QSPI FIFO flush!\n",
	252	__func__);
	253	return -1;
	254	}
	255
	256	/*
	257	* Notes:
	258	* 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs;
	259	* 2. don't set RX_EN and TX_EN yet.
	260	* (SW needs to make sure that while programming the blk_size,
	261	* tx_en and rx_en bits must be zero)
	262	* [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set
	263	* i.e., both dout and din are not NULL.
	264	*/
	265	clrsetbits_le32(&regs->command1,
	266	(QSPI_CMD1_LSBI_FE \| QSPI_CMD1_LSBY_FE \|
	267	QSPI_CMD1_RX_EN \| QSPI_CMD1_TX_EN),
	268	(spi_chip_select(dev) << QSPI_CMD1_CS_SEL_SHIFT));
	269
	270	/* set xfer size to 1 block (32 bits) */
	271	writel(0, &regs->dma_blk);
	272
	273	if (flags & SPI_XFER_BEGIN)
	274	spi_cs_activate(dev);
	275
	276	/* handle data in 32-bit chunks */
	277	while (num_bytes > 0) {
	278	int bytes;
	279
	280	tmpdout = 0;
	281	bytes = (num_bytes > 4) ? 4 : num_bytes;
	282
	283	if (dout != NULL) {
	284	memcpy((void )&tmpdout, (void )dout, bytes);
	285	dout += bytes;
	286	num_bytes -= bytes;
	287	writel(tmpdout, &regs->tx_fifo);
	288	setbits_le32(&regs->command1, QSPI_CMD1_TX_EN);
	289	}
	290
291	if (din != NULL)
292	setbits_le32(&regs->command1, QSPI_CMD1_RX_EN);
293
294	/* clear ready bit */
295	setbits_le32(&regs->xfer_status, QSPI_XFER_STS_RDY);
296
297	clrsetbits_le32(&regs->command1,
298	QSPI_CMD1_BITLEN_MASK << QSPI_CMD1_BITLEN_SHIFT,
299	(bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT);
300
301	/* Need to stabilize other reg bits before GO bit set.
302	* As per the TRM:
303	* "For successful operation at various freq combinations,
304	* a minimum of 4-5 spi_clk cycle delay might be required
305	* before enabling the PIO or DMA bits. The worst case delay
306	* calculation can be done considering slowest qspi_clk as
307	* 1MHz. Based on that 1us delay should be enough before
308	* enabling PIO or DMA." Padded another 1us for safety.
309	*/
310	udelay(2);
311	setbits_le32(&regs->command1, QSPI_CMD1_GO);
312	udelay(1);
313
314	/*
315	* Wait for SPI transmit FIFO to empty, or to time out.
316	* The RX FIFO status will be read and cleared last
317	*/
318	for (tm = 0; tm < QSPI_TIMEOUT; ++tm) {
319	u32 fifo_status, xfer_status;
320
321	xfer_status = readl(&regs->xfer_status);
322	if (!(xfer_status & QSPI_XFER_STS_RDY))
323	continue;
324
325	fifo_status = readl(&regs->fifo_status);
326	if (fifo_status & QSPI_FIFO_STS_ERR) {
327	debug("%s: got a fifo error: ", __func__);
328	if (fifo_status & QSPI_FIFO_STS_TX_FIFO_OVF)
329	debug("tx FIFO overflow ");
330	if (fifo_status & QSPI_FIFO_STS_TX_FIFO_UNR)
331	debug("tx FIFO underrun ");
332	if (fifo_status & QSPI_FIFO_STS_RX_FIFO_OVF)
333	debug("rx FIFO overflow ");
334	if (fifo_status & QSPI_FIFO_STS_RX_FIFO_UNR)
335	debug("rx FIFO underrun ");
336	if (fifo_status & QSPI_FIFO_STS_TX_FIFO_FULL)
337	debug("tx FIFO full ");
338	if (fifo_status & QSPI_FIFO_STS_TX_FIFO_EMPTY)
339	debug("tx FIFO empty ");
340	if (fifo_status & QSPI_FIFO_STS_RX_FIFO_FULL)
341	debug("rx FIFO full ");
342	if (fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)
343	debug("rx FIFO empty ");
344	debug("\n");
345	break;
346	}
347
348	if (!(fifo_status & QSPI_FIFO_STS_RX_FIFO_EMPTY)) {
349	tmpdin = readl(&regs->rx_fifo);
350	if (din != NULL) {
351	memcpy(din, &tmpdin, bytes);
352	din += bytes;
353	num_bytes -= bytes;
354	}
355	}
356	break;
357	}
358
359	if (tm >= QSPI_TIMEOUT)
360	ret = tm;
361
362	/* clear ACK RDY, etc. bits */
363	writel(readl(&regs->fifo_status), &regs->fifo_status);
364	}
365
366	if (flags & SPI_XFER_END)
367	spi_cs_deactivate(dev);
368
369	debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
370	__func__, tmpdin, readl(&regs->fifo_status));
371
372	if (ret) {
373	printf("%s: timeout during SPI transfer, tm %d\n",
374	__func__, ret);
375	return -1;
376	}
377
378	return ret;
379	}
380
381	static int tegra210_qspi_set_speed(struct udevice *bus, uint speed)
382	{
0fd3d911	383	struct tegra_spi_plat *plat = dev_get_plat(bus);
4e675ff2 TW	384	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	385
	386	if (speed > plat->frequency)
	387	speed = plat->frequency;
	388	priv->freq = speed;
	389	debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
	390
	391	return 0;
	392	}
	393
	394	static int tegra210_qspi_set_mode(struct udevice *bus, uint mode)
	395	{
	396	struct tegra210_qspi_priv *priv = dev_get_priv(bus);
	397
	398	priv->mode = mode;
	399	debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
	400
	401	return 0;
	402	}
	403
	404	static const struct dm_spi_ops tegra210_qspi_ops = {
	405	.claim_bus = tegra210_qspi_claim_bus,
	406	.xfer = tegra210_qspi_xfer,
	407	.set_speed = tegra210_qspi_set_speed,
	408	.set_mode = tegra210_qspi_set_mode,
	409	/*
	410	* cs_info is not needed, since we require all chip selects to be
	411	* in the device tree explicitly
	412	*/
	413	};
	414
	415	static const struct udevice_id tegra210_qspi_ids[] = {
	416	{ .compatible = "nvidia,tegra210-qspi" },
	417	{ }
	418	};
	419
	420	U_BOOT_DRIVER(tegra210_qspi) = {
	421	.name = "tegra210-qspi",
	422	.id = UCLASS_SPI,
	423	.of_match = tegra210_qspi_ids,
	424	.ops = &tegra210_qspi_ops,
d1998a9f	425	.of_to_plat = tegra210_qspi_of_to_plat,
8a8d24bd	426	.plat_auto = sizeof(struct tegra_spi_plat),
41575d8e SG	427	.priv_auto = sizeof(struct tegra210_qspi_priv),
41575d8e SG	428	.per_child_auto = sizeof(struct spi_slave),
4e675ff2 TW	429	.probe = tegra210_qspi_probe,
4e675ff2 TW	430	};