[J-u-boot.git] / drivers / pwm / pwm-cadence-ttc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * (C) Copyright 2021 Xilinx, Inc. Michal Simek
 */

#define LOG_CATEGORY UCLASS_PWM

#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <log.h>
#include <pwm.h>
#include <asm/io.h>
#include <log.h>
#include <div64.h>
#include <linux/bitfield.h>
#include <linux/math64.h>
#include <linux/log2.h>
#include <linux/time.h>
#include <dm/device_compat.h>

#define CLOCK_CONTROL		0
#define COUNTER_CONTROL		0xc
#define INTERVAL_COUNTER	0x24
#define MATCH_1_COUNTER		0x30

#define CLK_FALLING_EDGE	BIT(6)
#define CLK_SRC_EXTERNAL	BIT(5)
#define CLK_PRESCALE_MASK	GENMASK(4, 1)
#define CLK_PRESCALE_ENABLE	BIT(0)

#define COUNTER_WAVE_POL		BIT(6)
#define COUNTER_WAVE_DISABLE		BIT(5)
#define COUNTER_RESET			BIT(4)
#define COUNTER_MATCH_ENABLE		BIT(3)
#define COUNTER_DECREMENT_ENABLE	BIT(2)
#define COUNTER_INTERVAL_ENABLE		BIT(1)
#define COUNTER_COUNTING_DISABLE	BIT(0)

#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
#define TTC_CLOCK_CONTROL(reg, channel) \
	TTC_REG((reg) + CLOCK_CONTROL, (channel))
#define TTC_COUNTER_CONTROL(reg, channel) \
	TTC_REG((reg) + COUNTER_CONTROL, (channel))
#define TTC_INTERVAL_COUNTER(reg, channel) \
	TTC_REG((reg) + INTERVAL_COUNTER, (channel))
#define TTC_MATCH_1_COUNTER(reg, channel) \
	TTC_REG((reg) + MATCH_1_COUNTER, (channel))

struct cadence_ttc_pwm_plat {
	u8 *regs;
	u32 timer_width;
};

struct cadence_ttc_pwm_priv {
	u8 *regs;
	u32 timer_width;
	u32 timer_mask;
	unsigned long frequency;
	bool invert[2];
};

static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
				      bool polarity)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	priv->invert[channel] = polarity;

	dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);

	return 0;
}

static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
				      uint period_ns, uint duty_ns)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	u32 counter_ctrl, clock_ctrl;
	int period_clocks, duty_clocks, prescaler;

	dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
		duty_ns, period_ns);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	/* Make sure counter is stopped */
	counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
		     COUNTER_COUNTING_DISABLE | COUNTER_WAVE_DISABLE);

	/* Calculate period, prescaler and set clock control register */
	period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
				  NSEC_PER_SEC);

	prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
	if (prescaler < 0)
		prescaler = 0;

	clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));

	if (!prescaler) {
		clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK);
	} else {
		clock_ctrl &= ~CLK_PRESCALE_MASK;
		clock_ctrl |= CLK_PRESCALE_ENABLE;
		clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
	};

	/* External source is not handled by this driver now */
	clock_ctrl &= ~CLK_SRC_EXTERNAL;

	writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));

	/* Calculate interval and set counter control value */
	duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
				NSEC_PER_SEC);

	writel((period_clocks >> prescaler) & priv->timer_mask,
	       TTC_INTERVAL_COUNTER(priv->regs, channel));
	writel((duty_clocks >> prescaler) & priv->timer_mask,
	       TTC_MATCH_1_COUNTER(priv->regs, channel));

	/* Restore/reset counter */
	counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
	counter_ctrl |= COUNTER_INTERVAL_ENABLE |
			COUNTER_RESET |
			COUNTER_MATCH_ENABLE;

	if (priv->invert[channel])
		counter_ctrl |= COUNTER_WAVE_POL;
	else
		counter_ctrl &= ~COUNTER_WAVE_POL;

	writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));

	dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
		period_clocks, prescaler);

	return 0;
};

static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
				      bool enable)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);

	if (channel > 2) {
		dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
		return -EINVAL;
	}

	dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);

	if (enable) {
		clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_COUNTING_DISABLE |
			     COUNTER_WAVE_DISABLE);
		setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_RESET);
	} else {
		setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
			     COUNTER_COUNTING_DISABLE |
			     COUNTER_WAVE_DISABLE);
	}

	return 0;
};

static int cadence_ttc_pwm_probe(struct udevice *dev)
{
	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
	struct clk clk;
	int ret;

	priv->regs = plat->regs;
	priv->timer_width = plat->timer_width;
	priv->timer_mask = GENMASK(priv->timer_width - 1, 0);

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0) {
		dev_err(dev, "failed to get clock\n");
		return ret;
	}

	priv->frequency = clk_get_rate(&clk);
	if (IS_ERR_VALUE(priv->frequency)) {
		dev_err(dev, "failed to get rate\n");
		return priv->frequency;
	}
	dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);

	ret = clk_enable(&clk);
	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}

	return 0;
}

static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
{
	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
	const char *cells;

	cells = dev_read_prop(dev, "#pwm-cells", NULL);
	if (!cells)
		return -EINVAL;

	plat->regs = dev_read_addr_ptr(dev);

	plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);

	return 0;
}

static int cadence_ttc_pwm_bind(struct udevice *dev)
{
	const char *cells;

	cells = dev_read_prop(dev, "#pwm-cells", NULL);
	if (!cells)
		return -ENODEV;

	return 0;
}

static const struct pwm_ops cadence_ttc_pwm_ops = {
	.set_invert = cadence_ttc_pwm_set_invert,
	.set_config = cadence_ttc_pwm_set_config,
	.set_enable = cadence_ttc_pwm_set_enable,
};

static const struct udevice_id cadence_ttc_pwm_ids[] = {
	{ .compatible = "cdns,ttc" },
	{ }
};

U_BOOT_DRIVER(cadence_ttc_pwm) = {
	.name = "cadence_ttc_pwm",
	.id = UCLASS_PWM,
	.of_match = cadence_ttc_pwm_ids,
	.ops = &cadence_ttc_pwm_ops,
	.bind = cadence_ttc_pwm_bind,
	.of_to_plat = cadence_ttc_pwm_of_to_plat,
	.probe = cadence_ttc_pwm_probe,
	.priv_auto = sizeof(struct cadence_ttc_pwm_priv),
	.plat_auto = sizeof(struct cadence_ttc_pwm_plat),
};
Commit	Line	Data
fb92cc2c MS	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* (C) Copyright 2021 Xilinx, Inc. Michal Simek
	4	*/
	5
	6	#define LOG_CATEGORY UCLASS_PWM
	7
	8	#include <clk.h>
fb92cc2c MS	9	#include <div64.h>
	10	#include <dm.h>
	11	#include <log.h>
	12	#include <pwm.h>
	13	#include <asm/io.h>
	14	#include <log.h>
	15	#include <div64.h>
	16	#include <linux/bitfield.h>
	17	#include <linux/math64.h>
	18	#include <linux/log2.h>
13248d66	19	#include <linux/time.h>
fb92cc2c MS	20	#include <dm/device_compat.h>
	21
	22	#define CLOCK_CONTROL 0
	23	#define COUNTER_CONTROL 0xc
	24	#define INTERVAL_COUNTER 0x24
	25	#define MATCH_1_COUNTER 0x30
	26
	27	#define CLK_FALLING_EDGE BIT(6)
	28	#define CLK_SRC_EXTERNAL BIT(5)
	29	#define CLK_PRESCALE_MASK GENMASK(4, 1)
	30	#define CLK_PRESCALE_ENABLE BIT(0)
	31
	32	#define COUNTER_WAVE_POL BIT(6)
	33	#define COUNTER_WAVE_DISABLE BIT(5)
	34	#define COUNTER_RESET BIT(4)
	35	#define COUNTER_MATCH_ENABLE BIT(3)
	36	#define COUNTER_DECREMENT_ENABLE BIT(2)
	37	#define COUNTER_INTERVAL_ENABLE BIT(1)
	38	#define COUNTER_COUNTING_DISABLE BIT(0)
	39
fb92cc2c MS	40	#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
	41	#define TTC_CLOCK_CONTROL(reg, channel) \
	42	TTC_REG((reg) + CLOCK_CONTROL, (channel))
	43	#define TTC_COUNTER_CONTROL(reg, channel) \
	44	TTC_REG((reg) + COUNTER_CONTROL, (channel))
	45	#define TTC_INTERVAL_COUNTER(reg, channel) \
	46	TTC_REG((reg) + INTERVAL_COUNTER, (channel))
	47	#define TTC_MATCH_1_COUNTER(reg, channel) \
	48	TTC_REG((reg) + MATCH_1_COUNTER, (channel))
	49
	50	struct cadence_ttc_pwm_plat {
	51	u8 *regs;
	52	u32 timer_width;
	53	};
	54
	55	struct cadence_ttc_pwm_priv {
	56	u8 *regs;
	57	u32 timer_width;
	58	u32 timer_mask;
	59	unsigned long frequency;
	60	bool invert[2];
	61	};
	62
	63	static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
	64	bool polarity)
	65	{
	66	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	67
	68	if (channel > 2) {
	69	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
	70	return -EINVAL;
	71	}
	72
	73	priv->invert[channel] = polarity;
	74
	75	dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
	76
	77	return 0;
	78	}
	79
	80	static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
	81	uint period_ns, uint duty_ns)
	82	{
	83	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
	84	u32 counter_ctrl, clock_ctrl;
	85	int period_clocks, duty_clocks, prescaler;
	86
	87	dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
	88	duty_ns, period_ns);
	89
	90	if (channel > 2) {
	91	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
	92	return -EINVAL;
	93	}
	94
	95	/* Make sure counter is stopped */
	96	counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
	97	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
	98	COUNTER_COUNTING_DISABLE \| COUNTER_WAVE_DISABLE);
	99
	100	/* Calculate period, prescaler and set clock control register */
	101	period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
	102	NSEC_PER_SEC);
	103
104	prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
105	if (prescaler < 0)
106	prescaler = 0;
107
108	clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));
109
110	if (!prescaler) {
111	clock_ctrl &= ~(CLK_PRESCALE_ENABLE \| CLK_PRESCALE_MASK);
112	} else {
113	clock_ctrl &= ~CLK_PRESCALE_MASK;
114	clock_ctrl \|= CLK_PRESCALE_ENABLE;
115	clock_ctrl \|= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
116	};
117
118	/* External source is not handled by this driver now */
119	clock_ctrl &= ~CLK_SRC_EXTERNAL;
120
121	writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));
122
123	/* Calculate interval and set counter control value */
124	duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
125	NSEC_PER_SEC);
126
127	writel((period_clocks >> prescaler) & priv->timer_mask,
128	TTC_INTERVAL_COUNTER(priv->regs, channel));
129	writel((duty_clocks >> prescaler) & priv->timer_mask,
130	TTC_MATCH_1_COUNTER(priv->regs, channel));
131
132	/* Restore/reset counter */
133	counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
134	counter_ctrl \|= COUNTER_INTERVAL_ENABLE \|
135	COUNTER_RESET \|
136	COUNTER_MATCH_ENABLE;
137
138	if (priv->invert[channel])
139	counter_ctrl \|= COUNTER_WAVE_POL;
140	else
141	counter_ctrl &= ~COUNTER_WAVE_POL;
142
143	writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));
144
145	dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
146	period_clocks, prescaler);
147
148	return 0;
149	};
150
151	static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
152	bool enable)
153	{
154	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
155
156	if (channel > 2) {
157	dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
158	return -EINVAL;
159	}
160
161	dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
162
163	if (enable) {
164	clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
165	COUNTER_COUNTING_DISABLE \|
166	COUNTER_WAVE_DISABLE);
167	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
168	COUNTER_RESET);
169	} else {
170	setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
171	COUNTER_COUNTING_DISABLE \|
172	COUNTER_WAVE_DISABLE);
173	}
174
175	return 0;
176	};
177
178	static int cadence_ttc_pwm_probe(struct udevice *dev)
179	{
180	struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
181	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
182	struct clk clk;
183	int ret;
184
185	priv->regs = plat->regs;
186	priv->timer_width = plat->timer_width;
187	priv->timer_mask = GENMASK(priv->timer_width - 1, 0);
188
189	ret = clk_get_by_index(dev, 0, &clk);
190	if (ret < 0) {
191	dev_err(dev, "failed to get clock\n");
192	return ret;
193	}
194
195	priv->frequency = clk_get_rate(&clk);
196	if (IS_ERR_VALUE(priv->frequency)) {
197	dev_err(dev, "failed to get rate\n");
198	return priv->frequency;
199	}
200	dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
201
202	ret = clk_enable(&clk);
203	if (ret) {
204	dev_err(dev, "failed to enable clock\n");
205	return ret;
206	}
207
208	return 0;
209	}
210
211	static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
212	{
213	struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
214	const char *cells;
215
216	cells = dev_read_prop(dev, "#pwm-cells", NULL);
217	if (!cells)
218	return -EINVAL;
219
220	plat->regs = dev_read_addr_ptr(dev);
221
222	plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);
223
224	return 0;
225	}
226
227	static int cadence_ttc_pwm_bind(struct udevice *dev)
228	{
229	const char *cells;
230
231	cells = dev_read_prop(dev, "#pwm-cells", NULL);
232	if (!cells)
233	return -ENODEV;
234
235	return 0;
236	}
237
238	static const struct pwm_ops cadence_ttc_pwm_ops = {
239	.set_invert = cadence_ttc_pwm_set_invert,
240	.set_config = cadence_ttc_pwm_set_config,
241	.set_enable = cadence_ttc_pwm_set_enable,
242	};
243
244	static const struct udevice_id cadence_ttc_pwm_ids[] = {
245	{ .compatible = "cdns,ttc" },
246	{ }
247	};
248
249	U_BOOT_DRIVER(cadence_ttc_pwm) = {
250	.name = "cadence_ttc_pwm",
251	.id = UCLASS_PWM,
252	.of_match = cadence_ttc_pwm_ids,
253	.ops = &cadence_ttc_pwm_ops,
254	.bind = cadence_ttc_pwm_bind,
255	.of_to_plat = cadence_ttc_pwm_of_to_plat,
256	.probe = cadence_ttc_pwm_probe,
257	.priv_auto = sizeof(struct cadence_ttc_pwm_priv),
258	.plat_auto = sizeof(struct cadence_ttc_pwm_plat),
259	};