[J-u-boot.git] / drivers / net / phy / natsemi.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * National Semiconductor PHY drivers
 *
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * author Andy Fleming
 */
#include <phy.h>

/* NatSemi DP83630 */

#define DP83630_PHY_PAGESEL_REG		0x13
#define DP83630_PHY_PTP_COC_REG		0x14
#define DP83630_PHY_PTP_CLKOUT_EN	(1<<15)
#define DP83630_PHY_RBR_REG		0x17

static int dp83630_config(struct phy_device *phydev)
{
	int ptp_coc_reg;

	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
	ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
			       DP83630_PHY_PTP_COC_REG);
	ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
		  ptp_coc_reg);
	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);

	genphy_config_aneg(phydev);

	return 0;
}

U_BOOT_PHY_DRIVER(dp83630) = {
	.name = "NatSemi DP83630",
	.uid = 0x20005ce1,
	.mask = 0xfffffff0,
	.features = PHY_BASIC_FEATURES,
	.config = &dp83630_config,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};


/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR      0x11
#define MIIM_DP83865_SPD_MASK  0x0018
#define MIIM_DP83865_SPD_1000  0x0010
#define MIIM_DP83865_SPD_100   0x0008
#define MIIM_DP83865_DPX_FULL  0x0002


/* NatSemi DP83865 */
static int dp838xx_config(struct phy_device *phydev)
{
	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	genphy_config_aneg(phydev);

	return 0;
}

static int dp83865_parse_status(struct phy_device *phydev)
{
	int mii_reg;

	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);

	switch (mii_reg & MIIM_DP83865_SPD_MASK) {

	case MIIM_DP83865_SPD_1000:
		phydev->speed = SPEED_1000;
		break;

	case MIIM_DP83865_SPD_100:
		phydev->speed = SPEED_100;
		break;

	default:
		phydev->speed = SPEED_10;
		break;

	}

	if (mii_reg & MIIM_DP83865_DPX_FULL)
		phydev->duplex = DUPLEX_FULL;
	else
		phydev->duplex = DUPLEX_HALF;

	return 0;
}

static int dp83865_startup(struct phy_device *phydev)
{
	int ret;

	ret = genphy_update_link(phydev);
	if (ret)
		return ret;

	return dp83865_parse_status(phydev);
}


U_BOOT_PHY_DRIVER(dp83865) = {
	.name = "NatSemi DP83865",
	.uid = 0x20005c70,
	.mask = 0xfffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &dp838xx_config,
	.startup = &dp83865_startup,
	.shutdown = &genphy_shutdown,
};

/* NatSemi DP83848 */
static int dp83848_parse_status(struct phy_device *phydev)
{
	int mii_reg;

	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);

	if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
		phydev->speed = SPEED_100;
	} else {
		phydev->speed = SPEED_10;
	}

	if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
		phydev->duplex = DUPLEX_FULL;
	} else {
		phydev->duplex = DUPLEX_HALF;
	}

	return 0;
}

static int dp83848_startup(struct phy_device *phydev)
{
	int ret;

	ret = genphy_update_link(phydev);
	if (ret)
		return ret;

	return dp83848_parse_status(phydev);
}

U_BOOT_PHY_DRIVER(dp83848) = {
	.name = "NatSemi DP83848",
	.uid = 0x20005c90,
	.mask = 0x2000ff90,
	.features = PHY_BASIC_FEATURES,
	.config = &dp838xx_config,
	.startup = &dp83848_startup,
	.shutdown = &genphy_shutdown,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9082eeac AF	2	/*
	3	* National Semiconductor PHY drivers
	4	*
9082eeac AF	5	* Copyright 2010-2011 Freescale Semiconductor, Inc.
9082eeac AF	6	* author Andy Fleming
9082eeac AF	7	*/
	8	#include <phy.h>
	9
96d0b9e1 HS	10	/* NatSemi DP83630 */
	11
	12	#define DP83630_PHY_PAGESEL_REG 0x13
	13	#define DP83630_PHY_PTP_COC_REG 0x14
	14	#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
	15	#define DP83630_PHY_RBR_REG 0x17
	16
	17	static int dp83630_config(struct phy_device *phydev)
	18	{
	19	int ptp_coc_reg;
	20
	21	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	22	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
	23	ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
	24	DP83630_PHY_PTP_COC_REG);
	25	ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
	26	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
	27	ptp_coc_reg);
	28	phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
	29
	30	genphy_config_aneg(phydev);
	31
	32	return 0;
	33	}
	34
390e3fcd	35	U_BOOT_PHY_DRIVER(dp83630) = {
96d0b9e1 HS	36	.name = "NatSemi DP83630",
	37	.uid = 0x20005ce1,
	38	.mask = 0xfffffff0,
	39	.features = PHY_BASIC_FEATURES,
	40	.config = &dp83630_config,
	41	.startup = &genphy_startup,
	42	.shutdown = &genphy_shutdown,
	43	};
	44
	45
9082eeac AF	46	/* DP83865 Link and Auto-Neg Status Register */
	47	#define MIIM_DP83865_LANR 0x11
	48	#define MIIM_DP83865_SPD_MASK 0x0018
	49	#define MIIM_DP83865_SPD_1000 0x0010
	50	#define MIIM_DP83865_SPD_100 0x0008
	51	#define MIIM_DP83865_DPX_FULL 0x0002
	52
	53
	54	/* NatSemi DP83865 */
5ea667ea	55	static int dp838xx_config(struct phy_device *phydev)
9082eeac AF	56	{
	57	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	58	genphy_config_aneg(phydev);
	59
	60	return 0;
	61	}
	62
	63	static int dp83865_parse_status(struct phy_device *phydev)
	64	{
	65	int mii_reg;
	66
	67	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
	68
	69	switch (mii_reg & MIIM_DP83865_SPD_MASK) {
	70
	71	case MIIM_DP83865_SPD_1000:
	72	phydev->speed = SPEED_1000;
	73	break;
	74
	75	case MIIM_DP83865_SPD_100:
	76	phydev->speed = SPEED_100;
	77	break;
	78
	79	default:
	80	phydev->speed = SPEED_10;
	81	break;
	82
	83	}
	84
	85	if (mii_reg & MIIM_DP83865_DPX_FULL)
	86	phydev->duplex = DUPLEX_FULL;
	87	else
	88	phydev->duplex = DUPLEX_HALF;
	89
	90	return 0;
	91	}
	92
	93	static int dp83865_startup(struct phy_device *phydev)
	94	{
b733c278	95	int ret;
9082eeac	96
b733c278 MS	97	ret = genphy_update_link(phydev);
	98	if (ret)
	99	return ret;
	100
	101	return dp83865_parse_status(phydev);
9082eeac AF	102	}
	103
	104
390e3fcd	105	U_BOOT_PHY_DRIVER(dp83865) = {
9082eeac AF	106	.name = "NatSemi DP83865",
	107	.uid = 0x20005c70,
	108	.mask = 0xfffffff0,
	109	.features = PHY_GBIT_FEATURES,
5ea667ea	110	.config = &dp838xx_config,
9082eeac AF	111	.startup = &dp83865_startup,
	112	.shutdown = &genphy_shutdown,
	113	};
	114
5ea667ea VB	115	/* NatSemi DP83848 */
	116	static int dp83848_parse_status(struct phy_device *phydev)
	117	{
	118	int mii_reg;
	119
	120	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
	121
	122	if(mii_reg & (BMSR_100FULL \| BMSR_100HALF)) {
	123	phydev->speed = SPEED_100;
	124	} else {
	125	phydev->speed = SPEED_10;
	126	}
	127
	128	if (mii_reg & (BMSR_10FULL \| BMSR_100FULL)) {
	129	phydev->duplex = DUPLEX_FULL;
	130	} else {
	131	phydev->duplex = DUPLEX_HALF;
	132	}
	133
	134	return 0;
	135	}
	136
	137	static int dp83848_startup(struct phy_device *phydev)
	138	{
b733c278	139	int ret;
5ea667ea	140
b733c278 MS	141	ret = genphy_update_link(phydev);
	142	if (ret)
	143	return ret;
	144
	145	return dp83848_parse_status(phydev);
5ea667ea VB	146	}
5ea667ea VB	147
390e3fcd	148	U_BOOT_PHY_DRIVER(dp83848) = {
5ea667ea VB	149	.name = "NatSemi DP83848",
	150	.uid = 0x20005c90,
	151	.mask = 0x2000ff90,
	152	.features = PHY_BASIC_FEATURES,
	153	.config = &dp838xx_config,
	154	.startup = &dp83848_startup,
	155	.shutdown = &genphy_shutdown,
	156	};