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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c037c93b AM |
2 | /* |
3 | * (C) Copyright 2012 | |
4 | * NVIDIA Inc, <www.nvidia.com> | |
5 | * | |
6 | * Allen Martin <[email protected]> | |
c037c93b | 7 | */ |
9b6b3c1b | 8 | #include <debug_uart.h> |
f7ae49fc | 9 | #include <log.h> |
b2f98938 | 10 | #include <spl.h> |
c037c93b AM |
11 | |
12 | #include <asm/io.h> | |
c037c93b | 13 | #include <asm/arch/clock.h> |
c037c93b | 14 | #include <asm/arch/pinmux.h> |
150c2493 | 15 | #include <asm/arch/tegra.h> |
19ed7b4e | 16 | #include <asm/arch-tegra/apb_misc.h> |
516f00b3 | 17 | #include <asm/arch-tegra/board.h> |
9f2ec3f5 | 18 | #include <asm/spl.h> |
1b245fee | 19 | #include "cpu.h" |
c037c93b | 20 | |
b2f98938 | 21 | void spl_board_init(void) |
c037c93b | 22 | { |
19ed7b4e SW |
23 | struct apb_misc_pp_ctlr *apb_misc = |
24 | (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; | |
b2f98938 AM |
25 | |
26 | /* enable JTAG */ | |
19ed7b4e | 27 | writel(0xC0, &apb_misc->cfg_ctl); |
c037c93b | 28 | |
c037c93b AM |
29 | board_init_uart_f(); |
30 | ||
31 | /* Initialize periph GPIOs */ | |
c037c93b | 32 | gpio_early_init_uart(); |
c037c93b | 33 | |
b2f98938 | 34 | clock_early_init(); |
9b6b3c1b SG |
35 | #ifdef CONFIG_DEBUG_UART |
36 | debug_uart_init(); | |
37 | #endif | |
b2f98938 | 38 | preloader_console_init(); |
c037c93b AM |
39 | } |
40 | ||
b2f98938 | 41 | u32 spl_boot_device(void) |
c037c93b | 42 | { |
b2f98938 | 43 | return BOOT_DEVICE_RAM; |
c037c93b AM |
44 | } |
45 | ||
b2f98938 | 46 | void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) |
c037c93b | 47 | { |
11e1479b | 48 | debug("image entry point: 0x%lX\n", spl_image->entry_point); |
c037c93b | 49 | |
b2f98938 | 50 | start_cpu((u32)spl_image->entry_point); |
c037c93b | 51 | halt_avp(); |
c037c93b | 52 | } |