[J-u-boot.git] / include / configs / alt.h

/*
 * include/configs/alt.h
 *     This file is alt board configuration.
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __ALT_H
#define __ALT_H

#undef DEBUG
#define CONFIG_R8A7794
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_TEXT_BASE	0x70000000
#else
#define CONFIG_SYS_TEXT_BASE	0xE6304000
#endif

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SH_QSPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK        20000000u
#define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)

#define CONFIG_SYS_TMU_CLK_DIV  4

/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH		4
#define CONFIG_SH_I2C_DATA_LOW		5
#define CONFIG_SH_I2C_CLOCK		10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* MMCIF */
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR		0xee200000
#define CONFIG_SH_MMCIF_CLK		48000000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF2 */
#define CONFIG_SMSTP7_ENA	0x00080000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ		97500000

#endif /* __ALT_H */
Commit	Line	Data
cff2f5f0 NI	1	/*
	2	* include/configs/alt.h
	3	* This file is alt board configuration.
	4	*
	5	* Copyright (C) 2014 Renesas Electronics Corporation
	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#ifndef __ALT_H
	11	#define __ALT_H
	12
	13	#undef DEBUG
cff2f5f0	14	#define CONFIG_R8A7794
1cc95f6e	15	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
cff2f5f0	16
5ca6dfe6	17	#include "rcar-gen2-common.h"
cff2f5f0	18
1cc95f6e	19	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
c9b59bf7 NI	20	#define CONFIG_SYS_TEXT_BASE 0x70000000
c9b59bf7 NI	21	#else
cff2f5f0	22	#define CONFIG_SYS_TEXT_BASE 0xE6304000
c9b59bf7	23	#endif
cff2f5f0	24
1cc95f6e	25	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
c9b59bf7 NI	26	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
c9b59bf7 NI	27	#else
cff2f5f0	28	#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
c9b59bf7	29	#endif
cff2f5f0 NI	30	#define STACK_AREA_SIZE 0xC000
	31	#define LOW_LEVEL_MERAM_STACK \
	32	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	33
	34	/* MEMORY */
5ca6dfe6 NI	35	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	36	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	37	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
cff2f5f0 NI	38
cff2f5f0 NI	39	/* SCIF */
cff2f5f0 NI	40
	41	/* FLASH */
	42	#define CONFIG_SPI
cff2f5f0	43	#define CONFIG_SH_QSPI
cff2f5f0	44	#define CONFIG_SPI_FLASH_QUAD
cff2f5f0	45
cff2f5f0	46	/* SH Ether */
cff2f5f0 NI	47	#define CONFIG_SH_ETHER
	48	#define CONFIG_SH_ETHER_USE_PORT 0
	49	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	50	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	51	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	52	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	53	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
	54	#define CONFIG_PHYLIB
	55	#define CONFIG_PHY_MICREL
	56	#define CONFIG_BITBANGMII
	57	#define CONFIG_BITBANGMII_MULTI
	58
	59	/* Board Clock */
	60	#define RMOBILE_XTAL_CLK 20000000u
	61	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	62	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	63	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	64	#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
cff2f5f0 NI	65
	66	#define CONFIG_SYS_TMU_CLK_DIV 4
	67
	68	/* i2c */
cff2f5f0 NI	69	#define CONFIG_SYS_I2C
	70	#define CONFIG_SYS_I2C_SH
	71	#define CONFIG_SYS_I2C_SLAVE 0x7F
	72	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
cff2f5f0	73	#define CONFIG_SYS_I2C_SH_SPEED0 400000
cff2f5f0	74	#define CONFIG_SYS_I2C_SH_SPEED1 400000
cff2f5f0 NI	75	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	76	#define CONFIG_SH_I2C_DATA_HIGH 4
	77	#define CONFIG_SH_I2C_DATA_LOW 5
	78	#define CONFIG_SH_I2C_CLOCK 10000000
	79
	80	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	81
7ffc8dfb	82	/* USB */
7ffc8dfb NI	83	#define CONFIG_USB_EHCI_RMOBILE
	84	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	85
2b8c0814	86	/* MMCIF */
2b8c0814 NI	87	#define CONFIG_SH_MMCIF
	88	#define CONFIG_SH_MMCIF_ADDR 0xee200000
	89	#define CONFIG_SH_MMCIF_CLK 48000000
	90
8e2e5886 NI	91	/* Module stop status bits */
	92	/* INTC-RT */
	93	#define CONFIG_SMSTP0_ENA 0x00400000
	94	/* MSIF */
	95	#define CONFIG_SMSTP2_ENA 0x00002000
	96	/* INTC-SYS, IRQC */
	97	#define CONFIG_SMSTP4_ENA 0x00000180
	98	/* SCIF2 */
	99	#define CONFIG_SMSTP7_ENA 0x00080000
	100
25f9613f NI	101	/* SDHI */
	102	#define CONFIG_SH_SDHI_FREQ 97500000
	103
cff2f5f0	104	#endif /* __ALT_H */