[J-u-boot.git] / drivers / i2c / fsl_i2c.c

/*
 * Copyright 2006,2009 Freescale Semiconductor, Inc.
 *
 * 2012, Heiko Schocher, DENX Software Engineering, [email protected].
 * Changes for multibus/multiadapter I2C support.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <command.h>
#include <i2c.h>		/* Functional interface */
#include <asm/io.h>
#include <asm/fsl_i2c.h>	/* HW definitions */

/* The maximum number of microseconds we will wait until another master has
 * released the bus.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_MBB_TIMEOUT
#define CONFIG_I2C_MBB_TIMEOUT	100000
#endif

/* The maximum number of microseconds we will wait for a read or write
 * operation to complete.  If not defined in the board header file, then use a
 * generic value.
 */
#ifndef CONFIG_I2C_TIMEOUT
#define CONFIG_I2C_TIMEOUT	100000
#endif

#define I2C_READ_BIT  1
#define I2C_WRITE_BIT 0

DECLARE_GLOBAL_DATA_PTR;

static const struct fsl_i2c_base *i2c_base[4] = {
	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
#endif
};

/* I2C speed map for a DFSR value of 1 */

/*
 * Map I2C frequency dividers to FDR and DFSR values
 *
 * This structure is used to define the elements of a table that maps I2C
 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
 * Sampling Rate (DFSR) registers.
 *
 * The actual table should be defined in the board file, and it must be called
 * fsl_i2c_speed_map[].
 *
 * The last entry of the table must have a value of {-1, X}, where X is same
 * FDR/DFSR values as the second-to-last entry.  This guarantees that any
 * search through the array will always find a match.
 *
 * The values of the divider must be in increasing numerical order, i.e.
 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
 *
 * For this table, the values are based on a value of 1 for the DFSR
 * register.  See the application note AN2919 "Determining the I2C Frequency
 * Divider Ratio for SCL"
 *
 * ColdFire I2C frequency dividers for FDR values are different from
 * PowerPC. The protocol to use the I2C module is still the same.
 * A different table is defined and are based on MCF5xxx user manual.
 *
 */
static const struct {
	unsigned short divider;
	u8 fdr;
} fsl_i2c_speed_map[] = {
#ifdef __M68K__
	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	{-1, 31}
#endif
};

/**
 * Set the I2C bus speed for a given I2C device
 *
 * @param base: the I2C device registers
 * @i2c_clk: I2C bus clock frequency
 * @speed: the desired speed of the bus
 *
 * The I2C device must be stopped before calling this function.
 *
 * The return value is the actual bus speed that is set.
 */
static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
	unsigned int i2c_clk, unsigned int speed)
{
	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);

	/*
	 * We want to choose an FDR/DFSR that generates an I2C bus speed that
	 * is equal to or lower than the requested speed.  That means that we
	 * want the first divider that is equal to or greater than the
	 * calculated divider.
	 */
#ifdef __PPC__
	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	unsigned short a, b, ga, gb;
	unsigned long c_div, est_div;

#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
#else
	/* Condition 1: dfsr <= 50/T */
	dfsr = (5 * (i2c_clk / 1000)) / 100000;
#endif
#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	speed = i2c_clk / divider; /* Fake something */
#else
	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	if (!dfsr)
		dfsr = 1;

	est_div = ~0;
	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
		for (gb = 0; gb < 8; gb++) {
			b = 16 << gb;
			c_div = b * (a + ((3*dfsr)/b)*2);
			if ((c_div > divider) && (c_div < est_div)) {
				unsigned short bin_gb, bin_ga;

				est_div = c_div;
				bin_gb = gb << 2;
				bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
				fdr = bin_gb | bin_ga;
				speed = i2c_clk / est_div;
				debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
				      "a:%d, b:%d, speed:%d\n",
				      fdr, est_div, ga, gb, a, b, speed);
				/* Condition 2 not accounted for */
				debug("Tr <= %d ns\n",
				      (b - 3 * dfsr) * 1000000 /
				      (i2c_clk / 1000));
			}
		}
		if (a == 20)
			a += 2;
		if (a == 24)
			a += 4;
	}
	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
#endif
	writeb(dfsr, &base->dfsrr);	/* set default filter */
	writeb(fdr, &base->fdr);	/* set bus speed */
#else
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
		if (fsl_i2c_speed_map[i].divider >= divider) {
			u8 fdr;

			fdr = fsl_i2c_speed_map[i].fdr;
			speed = i2c_clk / fsl_i2c_speed_map[i].divider;
			writeb(fdr, &base->fdr);	/* set bus speed */

			break;
		}
#endif
	return speed;
}

static unsigned int get_i2c_clock(int bus)
{
	if (bus)
		return gd->arch.i2c2_clk;	/* I2C2 clock */
	else
		return gd->arch.i2c1_clk;	/* I2C1 clock */
}

static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
{
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
	unsigned long long timeval = 0;
	int ret = -1;
	unsigned int flags = 0;

#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	unsigned int svr = get_svr();
	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
		flags = I2C_CR_BIT6;
#endif

	writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);

	timeval = get_ticks();
	while (!(readb(&base->sr) & I2C_SR_MBB)) {
		if ((get_ticks() - timeval) > timeout)
			goto err;
	}

	if (readb(&base->sr) & I2C_SR_MAL) {
		/* SDA is stuck low */
		writeb(0, &base->cr);
		udelay(100);
		writeb(I2C_CR_MSTA | flags, &base->cr);
		writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
	}

	readb(&base->dr);

	timeval = get_ticks();
	while (!(readb(&base->sr) & I2C_SR_MIF)) {
		if ((get_ticks() - timeval) > timeout)
			goto err;
	}
	ret = 0;

err:
	writeb(I2C_CR_MEN | flags, &base->cr);
	writeb(0, &base->sr);
	udelay(100);

	return ret;
}

static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
	const struct fsl_i2c_base *base;
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
	unsigned long long timeval;

#ifdef CONFIG_SYS_I2C_INIT_BOARD
	/* Call board specific i2c bus reset routine before accessing the
	 * environment, which might be in a chip on that bus. For details
	 * about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_init_board();
#endif
	base = (struct fsl_i2c_base *)i2c_base[adap->hwadapnr];

	writeb(0, &base->cr);		/* stop I2C controller */
	udelay(5);			/* let it shutdown in peace */
	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
	writeb(slaveadd << 1, &base->adr);/* write slave address */
	writeb(0x0, &base->sr);		/* clear status register */
	writeb(I2C_CR_MEN, &base->cr);	/* start I2C controller */

	timeval = get_ticks();
	while (readb(&base->sr) & I2C_SR_MBB) {
		if ((get_ticks() - timeval) < timeout)
			continue;

		if (fsl_i2c_fixup(base))
			debug("i2c_init: BUS#%d failed to init\n",
			      adap->hwadapnr);

		break;
	}

#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	/* Call board specific i2c bus reset routine AFTER the bus has been
	 * initialized. Use either this callpoint or i2c_init_board;
	 * which is called before i2c_init operations.
	 * For details about this problem see doc/I2C_Edge_Conditions.
	*/
	i2c_board_late_init();
#endif
}

static int
i2c_wait4bus(struct i2c_adapter *adap)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);

	while (readb(&base->sr) & I2C_SR_MBB) {
		if ((get_ticks() - timeval) > timeout)
			return -1;
	}

	return 0;
}

static __inline__ int
i2c_wait(struct i2c_adapter *adap, int write)
{
	u32 csr;
	unsigned long long timeval = get_ticks();
	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];

	do {
		csr = readb(&base->sr);
		if (!(csr & I2C_SR_MIF))
			continue;
		/* Read again to allow register to stabilise */
		csr = readb(&base->sr);

		writeb(0x0, &base->sr);

		if (csr & I2C_SR_MAL) {
			debug("i2c_wait: MAL\n");
			return -1;
		}

		if (!(csr & I2C_SR_MCF))	{
			debug("i2c_wait: unfinished\n");
			return -1;
		}

		if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
			debug("i2c_wait: No RXACK\n");
			return -1;
		}

		return 0;
	} while ((get_ticks() - timeval) < timeout);

	debug("i2c_wait: timed out\n");
	return -1;
}

static __inline__ int
i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];

	writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
	       | (rsta ? I2C_CR_RSTA : 0),
	       &base->cr);

	writeb((dev << 1) | dir, &base->dr);

	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
		return 0;

	return 1;
}

static __inline__ int
__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	int i;

	for (i = 0; i < length; i++) {
		writeb(data[i], &base->dr);

		if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
			break;
	}

	return i;
}

static __inline__ int
__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	int i;

	writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
	       &base->cr);

	/* dummy read */
	readb(&base->dr);

	for (i = 0; i < length; i++) {
		if (i2c_wait(adap, I2C_READ_BIT) < 0)
			break;

		/* Generate ack on last next to last byte */
		if (i == length - 2)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
			       &base->cr);

		/* Do not generate stop on last byte */
		if (i == length - 1)
			writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
			       &base->cr);

		data[i] = readb(&base->dr);
	}

	return i;
}

static int
fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
	     u8 *data, int dlen)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	int ret = -1; /* signal error */
	u8 *o = (u8 *)&offset;

	if (i2c_wait4bus(adap) < 0)
		return -1;

	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
	 * adhere to the following convention:
	 * - the offset length is passed as negative (that is, the absolute
	 *   value of olen is the actual offset length)
	 * - the offset itself is passed in data, which is overwritten by the
	 *   subsequent read operation
	 */
	if (olen < 0) {
		if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
			ret = __i2c_write(adap, data, -olen);

		if (ret != -olen)
			return -1;

		if (dlen && i2c_write_addr(adap, chip_addr,
					   I2C_READ_BIT, 1) != 0)
			ret = __i2c_read(adap, data, dlen);
	} else {
		if ((!dlen || olen > 0) &&
		    i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
		    __i2c_write(adap, &o[4 - olen], olen) == olen)
			ret = 0; /* No error so far */

		if (dlen && i2c_write_addr(adap, chip_addr, I2C_READ_BIT,
					   olen ? 1 : 0) != 0)
			ret = __i2c_read(adap, data, dlen);
	}

	writeb(I2C_CR_MEN, &base->cr);

	if (i2c_wait4bus(adap)) /* Wait until STOP */
		debug("i2c_read: wait4bus timed out\n");

	if (ret == dlen)
		return 0;

	return -1;
}

static int
fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
	      u8 *data, int dlen)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	int ret = -1; /* signal error */
	u8 *o = (u8 *)&offset;

	if (i2c_wait4bus(adap) < 0)
		return -1;

	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
	    __i2c_write(adap, &o[4 - olen], olen) == olen) {
		ret = __i2c_write(adap, data, dlen);
	}

	writeb(I2C_CR_MEN, &base->cr);
	if (i2c_wait4bus(adap)) /* Wait until STOP */
		debug("i2c_write: wait4bus timed out\n");

	if (ret == dlen)
		return 0;

	return -1;
}

static int
fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
	/* For unknow reason the controller will ACK when
	 * probing for a slave with the same address, so skip
	 * it.
	 */
	if (chip == (readb(&base->adr) >> 1))
		return -1;

	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
}

static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
			unsigned int speed)
{
	struct fsl_i2c_base *base =
		(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];

	writeb(0, &base->cr);		/* stop controller */
	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
	writeb(I2C_CR_MEN, &base->cr);	/* start controller */

	return 0;
}

/*
 * Register fsl i2c adapters
 */
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
			 0)
#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
			 1)
#endif
#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
			 2)
#endif
#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
			 fsl_i2c_write, fsl_i2c_set_bus_speed,
			 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
			 3)
#endif
Commit	Line	Data
debb7354	1	/*
92477a63	2	* Copyright 2006,2009 Freescale Semiconductor, Inc.
debb7354	3	*
00f792e0 HS	4	* 2012, Heiko Schocher, DENX Software Engineering, [email protected].
	5	* Changes for multibus/multiadapter I2C support.
	6	*
5b8031cc	7	* SPDX-License-Identifier: GPL-2.0
debb7354 JL	8	*/
	9
	10	#include <common.h>
4d45f69e	11	#include <command.h>
20476726	12	#include <i2c.h> /* Functional interface */
7237c033	13	#include <asm/io.h>
20476726	14	#include <asm/fsl_i2c.h> /* HW definitions */
debb7354	15
92477a63 TT	16	/* The maximum number of microseconds we will wait until another master has
	17	* released the bus. If not defined in the board header file, then use a
	18	* generic value.
	19	*/
	20	#ifndef CONFIG_I2C_MBB_TIMEOUT
	21	#define CONFIG_I2C_MBB_TIMEOUT 100000
	22	#endif
	23
	24	/* The maximum number of microseconds we will wait for a read or write
	25	* operation to complete. If not defined in the board header file, then use a
	26	* generic value.
	27	*/
	28	#ifndef CONFIG_I2C_TIMEOUT
6dd38cc3	29	#define CONFIG_I2C_TIMEOUT 100000
92477a63	30	#endif
debb7354	31
1939d969 JT	32	#define I2C_READ_BIT 1
	33	#define I2C_WRITE_BIT 0
	34
d8c82db4 TT	35	DECLARE_GLOBAL_DATA_PTR;
d8c82db4 TT	36
ec2c81c5	37	static const struct fsl_i2c_base *i2c_base[4] = {
ec2c81c5	38	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
00f792e0	39	#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
ec2c81c5	40	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
a17fd10f SL	41	#endif
a17fd10f SL	42	#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
ec2c81c5	43	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
a17fd10f SL	44	#endif
a17fd10f SL	45	#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
ec2c81c5	46	(struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
be5e6181 TT	47	#endif
be5e6181 TT	48	};
debb7354	49
d8c82db4 TT	50	/* I2C speed map for a DFSR value of 1 */
	51
	52	/*
	53	* Map I2C frequency dividers to FDR and DFSR values
	54	*
	55	* This structure is used to define the elements of a table that maps I2C
	56	* frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
	57	* programmed into the Frequency Divider Ratio (FDR) and Digital Filter
	58	* Sampling Rate (DFSR) registers.
	59	*
	60	* The actual table should be defined in the board file, and it must be called
	61	* fsl_i2c_speed_map[].
	62	*
	63	* The last entry of the table must have a value of {-1, X}, where X is same
	64	* FDR/DFSR values as the second-to-last entry. This guarantees that any
	65	* search through the array will always find a match.
	66	*
	67	* The values of the divider must be in increasing numerical order, i.e.
	68	* fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
	69	*
	70	* For this table, the values are based on a value of 1 for the DFSR
	71	* register. See the application note AN2919 "Determining the I2C Frequency
	72	* Divider Ratio for SCL"
5d9a5efa TL	73	*
	74	* ColdFire I2C frequency dividers for FDR values are different from
	75	* PowerPC. The protocol to use the I2C module is still the same.
	76	* A different table is defined and are based on MCF5xxx user manual.
	77	*
d8c82db4 TT	78	*/
	79	static const struct {
	80	unsigned short divider;
d8c82db4 TT	81	u8 fdr;
d8c82db4 TT	82	} fsl_i2c_speed_map[] = {
99404202	83	#ifdef __M68K__
5d9a5efa TL	84	{20, 32}, {22, 33}, {24, 34}, {26, 35},
	85	{28, 0}, {28, 36}, {30, 1}, {32, 37},
	86	{34, 2}, {36, 38}, {40, 3}, {40, 39},
	87	{44, 4}, {48, 5}, {48, 40}, {56, 6},
	88	{56, 41}, {64, 42}, {68, 7}, {72, 43},
	89	{80, 8}, {80, 44}, {88, 9}, {96, 41},
	90	{104, 10}, {112, 42}, {128, 11}, {128, 43},
	91	{144, 12}, {160, 13}, {160, 48}, {192, 14},
	92	{192, 49}, {224, 50}, {240, 15}, {256, 51},
	93	{288, 16}, {320, 17}, {320, 52}, {384, 18},
	94	{384, 53}, {448, 54}, {480, 19}, {512, 55},
	95	{576, 20}, {640, 21}, {640, 56}, {768, 22},
	96	{768, 57}, {960, 23}, {896, 58}, {1024, 59},
	97	{1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
	98	{1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
	99	{2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
	100	{-1, 31}
	101	#endif
d8c82db4 TT	102	};
	103
	104	/**
	105	* Set the I2C bus speed for a given I2C device
	106	*
ec2c81c5	107	* @param base: the I2C device registers
d8c82db4 TT	108	* @i2c_clk: I2C bus clock frequency
	109	* @speed: the desired speed of the bus
	110	*
	111	* The I2C device must be stopped before calling this function.
	112	*
	113	* The return value is the actual bus speed that is set.
	114	*/
ec2c81c5	115	static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base,
d8c82db4 TT	116	unsigned int i2c_clk, unsigned int speed)
d8c82db4 TT	117	{
b4141195	118	unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX);
d8c82db4 TT	119
	120	/*
	121	* We want to choose an FDR/DFSR that generates an I2C bus speed that
	122	* is equal to or lower than the requested speed. That means that we
	123	* want the first divider that is equal to or greater than the
	124	* calculated divider.
	125	*/
5d9a5efa	126	#ifdef __PPC__
99404202 JT	127	u8 dfsr, fdr = 0x31; /* Default if no FDR found */
	128	/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
	129	unsigned short a, b, ga, gb;
	130	unsigned long c_div, est_div;
	131
d01ee4db	132	#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
99404202	133	dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
d01ee4db	134	#else
99404202 JT	135	/* Condition 1: dfsr <= 50/T */
99404202 JT	136	dfsr = (5 * (i2c_clk / 1000)) / 100000;
d01ee4db JT	137	#endif
d01ee4db JT	138	#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
99404202 JT	139	fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
	140	speed = i2c_clk / divider; /* Fake something */
	141	#else
	142	debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
	143	if (!dfsr)
	144	dfsr = 1;
	145
	146	est_div = ~0;
	147	for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
	148	for (gb = 0; gb < 8; gb++) {
	149	b = 16 << gb;
	150	c_div = b * (a + ((3dfsr)/b)2);
	151	if ((c_div > divider) && (c_div < est_div)) {
	152	unsigned short bin_gb, bin_ga;
	153
	154	est_div = c_div;
	155	bin_gb = gb << 2;
	156	bin_ga = (ga & 0x3) \| ((ga & 0x4) << 3);
	157	fdr = bin_gb \| bin_ga;
	158	speed = i2c_clk / est_div;
	159	debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
	160	"a:%d, b:%d, speed:%d\n",
	161	fdr, est_div, ga, gb, a, b, speed);
	162	/* Condition 2 not accounted for */
	163	debug("Tr <= %d ns\n",
	164	(b - 3 * dfsr) * 1000000 /
	165	(i2c_clk / 1000));
	166	}
	167	}
	168	if (a == 20)
	169	a += 2;
	170	if (a == 24)
	171	a += 4;
	172	}
	173	debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
	174	debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
	175	#endif
ec2c81c5	176	writeb(dfsr, &base->dfsrr); /* set default filter */
ec2c81c5	177	writeb(fdr, &base->fdr); /* set bus speed */
d01ee4db	178	#else
99404202 JT	179	unsigned int i;
	180
	181	for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
	182	if (fsl_i2c_speed_map[i].divider >= divider) {
	183	u8 fdr;
	184
d8c82db4 TT	185	fdr = fsl_i2c_speed_map[i].fdr;
d8c82db4 TT	186	speed = i2c_clk / fsl_i2c_speed_map[i].divider;
ec2c81c5	187	writeb(fdr, &base->fdr); /* set bus speed */
d01ee4db	188
d8c82db4 TT	189	break;
d8c82db4 TT	190	}
99404202	191	#endif
d8c82db4 TT	192	return speed;
	193	}
	194
62f730ff	195	static unsigned int get_i2c_clock(int bus)
c9a8b25e JH	196	{
c9a8b25e JH	197	if (bus)
609e6ec3	198	return gd->arch.i2c2_clk; /* I2C2 clock */
c9a8b25e	199	else
609e6ec3	200	return gd->arch.i2c1_clk; /* I2C1 clock */
c9a8b25e JH	201	}
c9a8b25e JH	202
ec2c81c5	203	static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
b8ce3343 CL	204	{
	205	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
	206	unsigned long long timeval = 0;
	207	int ret = -1;
9c3f77eb CL	208	unsigned int flags = 0;
	209
	210	#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
	211	unsigned int svr = get_svr();
	212	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) \|\|
	213	(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
	214	flags = I2C_CR_BIT6;
	215	#endif
b8ce3343	216
ec2c81c5	217	writeb(I2C_CR_MEN \| I2C_CR_MSTA, &base->cr);
b8ce3343 CL	218
b8ce3343 CL	219	timeval = get_ticks();
ec2c81c5	220	while (!(readb(&base->sr) & I2C_SR_MBB)) {
b8ce3343 CL	221	if ((get_ticks() - timeval) > timeout)
	222	goto err;
	223	}
	224
ec2c81c5	225	if (readb(&base->sr) & I2C_SR_MAL) {
b8ce3343	226	/* SDA is stuck low */
ec2c81c5	227	writeb(0, &base->cr);
b8ce3343	228	udelay(100);
ec2c81c5	229	writeb(I2C_CR_MSTA \| flags, &base->cr);
ec2c81c5	230	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| flags, &base->cr);
b8ce3343 CL	231	}
b8ce3343 CL	232
ec2c81c5	233	readb(&base->dr);
b8ce3343 CL	234
b8ce3343 CL	235	timeval = get_ticks();
ec2c81c5	236	while (!(readb(&base->sr) & I2C_SR_MIF)) {
b8ce3343 CL	237	if ((get_ticks() - timeval) > timeout)
	238	goto err;
	239	}
	240	ret = 0;
	241
	242	err:
ec2c81c5	243	writeb(I2C_CR_MEN \| flags, &base->cr);
ec2c81c5	244	writeb(0, &base->sr);
b8ce3343 CL	245	udelay(100);
	246
	247	return ret;
	248	}
	249
00f792e0	250	static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
debb7354	251	{
ec2c81c5	252	const struct fsl_i2c_base *base;
b8ce3343 CL	253	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
b8ce3343 CL	254	unsigned long long timeval;
be5e6181	255
39df00d9	256	#ifdef CONFIG_SYS_I2C_INIT_BOARD
26a33504 RR	257	/* Call board specific i2c bus reset routine before accessing the
	258	* environment, which might be in a chip on that bus. For details
	259	* about this problem see doc/I2C_Edge_Conditions.
	260	*/
39df00d9 HS	261	i2c_init_board();
39df00d9 HS	262	#endif
ec2c81c5	263	base = (struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
00f792e0	264
ec2c81c5	265	writeb(0, &base->cr); /* stop I2C controller */
00f792e0	266	udelay(5); /* let it shutdown in peace */
ec2c81c5	267	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
	268	writeb(slaveadd << 1, &base->adr);/* write slave address */
	269	writeb(0x0, &base->sr); /* clear status register */
	270	writeb(I2C_CR_MEN, &base->cr); /* start I2C controller */
26a33504	271
b8ce3343	272	timeval = get_ticks();
ec2c81c5	273	while (readb(&base->sr) & I2C_SR_MBB) {
b8ce3343 CL	274	if ((get_ticks() - timeval) < timeout)
	275	continue;
	276
ec2c81c5	277	if (fsl_i2c_fixup(base))
b8ce3343 CL	278	debug("i2c_init: BUS#%d failed to init\n",
	279	adap->hwadapnr);
	280
	281	break;
	282	}
	283
26a33504 RR	284	#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
	285	/* Call board specific i2c bus reset routine AFTER the bus has been
	286	* initialized. Use either this callpoint or i2c_init_board;
	287	* which is called before i2c_init operations.
	288	* For details about this problem see doc/I2C_Edge_Conditions.
	289	*/
	290	i2c_board_late_init();
	291	#endif
debb7354 JL	292	}
debb7354 JL	293
21f4cbb7	294	static int
00f792e0	295	i2c_wait4bus(struct i2c_adapter *adap)
debb7354	296	{
ec2c81c5	297	struct fsl_i2c_base *base =
ec2c81c5	298	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
f2302d44	299	unsigned long long timeval = get_ticks();
92477a63	300	const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
debb7354	301
ec2c81c5	302	while (readb(&base->sr) & I2C_SR_MBB) {
92477a63	303	if ((get_ticks() - timeval) > timeout)
debb7354	304	return -1;
debb7354 JL	305	}
debb7354 JL	306
5c9efb36	307	return 0;
debb7354 JL	308	}
	309
	310	static __inline__ int
00f792e0	311	i2c_wait(struct i2c_adapter *adap, int write)
debb7354 JL	312	{
debb7354 JL	313	u32 csr;
f2302d44	314	unsigned long long timeval = get_ticks();
92477a63	315	const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
ec2c81c5	316	struct fsl_i2c_base *base =
ec2c81c5	317	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
debb7354 JL	318
debb7354 JL	319	do {
ec2c81c5	320	csr = readb(&base->sr);
7237c033	321	if (!(csr & I2C_SR_MIF))
debb7354	322	continue;
21f4cbb7	323	/* Read again to allow register to stabilise */
ec2c81c5	324	csr = readb(&base->sr);
debb7354	325
ec2c81c5	326	writeb(0x0, &base->sr);
debb7354	327
7237c033	328	if (csr & I2C_SR_MAL) {
debb7354 JL	329	debug("i2c_wait: MAL\n");
	330	return -1;
	331	}
	332
7237c033	333	if (!(csr & I2C_SR_MCF)) {
debb7354 JL	334	debug("i2c_wait: unfinished\n");
	335	return -1;
	336	}
	337
1939d969	338	if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
debb7354 JL	339	debug("i2c_wait: No RXACK\n");
	340	return -1;
	341	}
	342
	343	return 0;
92477a63	344	} while ((get_ticks() - timeval) < timeout);
debb7354 JL	345
	346	debug("i2c_wait: timed out\n");
	347	return -1;
	348	}
	349
	350	static __inline__ int
00f792e0	351	i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
debb7354	352	{
ec2c81c5	353	struct fsl_i2c_base *base =
ec2c81c5	354	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
00f792e0	355
7237c033 JL	356	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX
7237c033 JL	357	\| (rsta ? I2C_CR_RSTA : 0),
ec2c81c5	358	&base->cr);
debb7354	359
ec2c81c5	360	writeb((dev << 1) \| dir, &base->dr);
debb7354	361
00f792e0	362	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
debb7354 JL	363	return 0;
	364
	365	return 1;
	366	}
	367
	368	static __inline__ int
00f792e0	369	__i2c_write(struct i2c_adapter adap, u8 data, int length)
debb7354	370	{
ec2c81c5	371	struct fsl_i2c_base *base =
ec2c81c5	372	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
debb7354	373	int i;
5c9efb36	374
5c9efb36	375	for (i = 0; i < length; i++) {
ec2c81c5	376	writeb(data[i], &base->dr);
debb7354	377
00f792e0	378	if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
debb7354 JL	379	break;
	380	}
	381
	382	return i;
	383	}
	384
	385	static __inline__ int
00f792e0	386	__i2c_read(struct i2c_adapter adap, u8 data, int length)
debb7354	387	{
ec2c81c5	388	struct fsl_i2c_base *base =
ec2c81c5	389	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
debb7354 JL	390	int i;
debb7354 JL	391
7237c033	392	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| ((length == 1) ? I2C_CR_TXAK : 0),
ec2c81c5	393	&base->cr);
debb7354 JL	394
debb7354 JL	395	/* dummy read */
ec2c81c5	396	readb(&base->dr);
debb7354	397
5c9efb36	398	for (i = 0; i < length; i++) {
00f792e0	399	if (i2c_wait(adap, I2C_READ_BIT) < 0)
debb7354 JL	400	break;
	401
	402	/* Generate ack on last next to last byte */
	403	if (i == length - 2)
7237c033	404	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_TXAK,
ec2c81c5	405	&base->cr);
debb7354	406
d1c9e5b3	407	/* Do not generate stop on last byte */
debb7354	408	if (i == length - 1)
d1c9e5b3	409	writeb(I2C_CR_MEN \| I2C_CR_MSTA \| I2C_CR_MTX,
ec2c81c5	410	&base->cr);
debb7354	411
ec2c81c5	412	data[i] = readb(&base->dr);
debb7354	413	}
5c9efb36	414
debb7354 JL	415	return i;
	416	}
	417
00f792e0	418	static int
2b21e960	419	fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
2b21e960	420	u8 *data, int dlen)
debb7354	421	{
ec2c81c5	422	struct fsl_i2c_base *base =
ec2c81c5	423	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
2b21e960	424	int ret = -1; /* signal error */
2b21e960	425	u8 o = (u8 )&offset;
debb7354	426
00f792e0	427	if (i2c_wait4bus(adap) < 0)
b778c1b5 RP	428	return -1;
b778c1b5 RP	429
386b2769	430	/* Some drivers use offset lengths in excess of 4 bytes. These drivers
	431	* adhere to the following convention:
	432	* - the offset length is passed as negative (that is, the absolute
	433	* value of olen is the actual offset length)
	434	* - the offset itself is passed in data, which is overwritten by the
	435	* subsequent read operation
a405764c	436	*/
2b21e960	437	if (olen < 0) {
2b21e960	438	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0)
03a112aa	439	ret = __i2c_write(adap, data, -olen);
a405764c	440
03a112aa	441	if (ret != -olen)
a405764c	442	return -1;
f6f5f709	443
2b21e960	444	if (dlen && i2c_write_addr(adap, chip_addr,
	445	I2C_READ_BIT, 1) != 0)
	446	ret = __i2c_read(adap, data, dlen);
a405764c	447	} else {
2b21e960	448	if ((!dlen \|\| olen > 0) &&
	449	i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
	450	__i2c_write(adap, &o[4 - olen], olen) == olen)
	451	ret = 0; /* No error so far */
	452
	453	if (dlen && i2c_write_addr(adap, chip_addr, I2C_READ_BIT,
	454	olen ? 1 : 0) != 0)
	455	ret = __i2c_read(adap, data, dlen);
a405764c	456	}
debb7354	457
ec2c81c5	458	writeb(I2C_CR_MEN, &base->cr);
debb7354	459
00f792e0	460	if (i2c_wait4bus(adap)) /* Wait until STOP */
d1c9e5b3 JT	461	debug("i2c_read: wait4bus timed out\n");
d1c9e5b3 JT	462
2b21e960	463	if (ret == dlen)
2b21e960	464	return 0;
4d45f69e JL	465
4d45f69e JL	466	return -1;
debb7354 JL	467	}
debb7354 JL	468
00f792e0	469	static int
2b21e960	470	fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen,
2b21e960	471	u8 *data, int dlen)
debb7354	472	{
ec2c81c5	473	struct fsl_i2c_base *base =
ec2c81c5	474	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
2b21e960	475	int ret = -1; /* signal error */
2b21e960	476	u8 o = (u8 )&offset;
debb7354	477
b8ce3343 CL	478	if (i2c_wait4bus(adap) < 0)
	479	return -1;
	480
2b21e960	481	if (i2c_write_addr(adap, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
	482	__i2c_write(adap, &o[4 - olen], olen) == olen) {
	483	ret = __i2c_write(adap, data, dlen);
4d45f69e	484	}
debb7354	485
ec2c81c5	486	writeb(I2C_CR_MEN, &base->cr);
00f792e0	487	if (i2c_wait4bus(adap)) /* Wait until STOP */
21f4cbb7	488	debug("i2c_write: wait4bus timed out\n");
debb7354	489
2b21e960	490	if (ret == dlen)
2b21e960	491	return 0;
4d45f69e JL	492
4d45f69e JL	493	return -1;
debb7354 JL	494	}
debb7354 JL	495
00f792e0 HS	496	static int
00f792e0 HS	497	fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
debb7354	498	{
ec2c81c5	499	struct fsl_i2c_base *base =
ec2c81c5	500	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
f6f5f709 JT	501	/* For unknow reason the controller will ACK when
	502	* probing for a slave with the same address, so skip
	503	* it.
debb7354	504	*/
ec2c81c5	505	if (chip == (readb(&base->adr) >> 1))
be5e6181	506	return -1;
be5e6181	507
00f792e0	508	return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
be5e6181 TT	509	}
be5e6181 TT	510
00f792e0 HS	511	static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
00f792e0 HS	512	unsigned int speed)
be5e6181	513	{
ec2c81c5	514	struct fsl_i2c_base *base =
ec2c81c5	515	(struct fsl_i2c_base *)i2c_base[adap->hwadapnr];
d8c82db4	516
ec2c81c5	517	writeb(0, &base->cr); /* stop controller */
	518	set_i2c_bus_speed(base, get_i2c_clock(adap->hwadapnr), speed);
	519	writeb(I2C_CR_MEN, &base->cr); /* start controller */
d8c82db4 TT	520
d8c82db4 TT	521	return 0;
be5e6181 TT	522	}
be5e6181 TT	523
00f792e0 HS	524	/*
	525	* Register fsl i2c adapters
	526	*/
	527	U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	528	fsl_i2c_write, fsl_i2c_set_bus_speed,
	529	CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
	530	0)
	531	#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
	532	U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	533	fsl_i2c_write, fsl_i2c_set_bus_speed,
	534	CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
	535	1)
c1bce4ff	536	#endif
a17fd10f SL	537	#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
	538	U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	539	fsl_i2c_write, fsl_i2c_set_bus_speed,
	540	CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
	541	2)
	542	#endif
	543	#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
	544	U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
	545	fsl_i2c_write, fsl_i2c_set_bus_speed,
	546	CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
	547	3)
	548	#endif