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Commit | Line | Data |
---|---|---|
dd84058d | 1 | CONFIG_PPC=y |
278b90ce | 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
a09fea1d TR |
3 | CONFIG_ENV_SIZE=0x2000 |
4 | CONFIG_ENV_SECT_SIZE=0x20000 | |
ff3bb0c4 | 5 | CONFIG_SYS_CLK_FREQ=66000000 |
dd84058d | 6 | CONFIG_MPC83xx=y |
93de2530 | 7 | CONFIG_HIGH_BATS=y |
dd84058d | 8 | CONFIG_TARGET_MPC832XEMDS=y |
21c1502a MS |
9 | CONFIG_CORE_PLL_RATIO_2_1=y |
10 | CONFIG_QUICC_MULT_FACTOR_3=y | |
11 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y | |
30915ab9 MS |
12 | CONFIG_BAT0=y |
13 | CONFIG_BAT0_NAME="SDRAM" | |
14 | CONFIG_BAT0_BASE=0x00000000 | |
15 | CONFIG_BAT0_LENGTH_256_MBYTES=y | |
16 | CONFIG_BAT0_ACCESS_RW=y | |
17 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y | |
18 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y | |
19 | CONFIG_BAT0_USER_MODE_VALID=y | |
20 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y | |
21 | CONFIG_BAT1=y | |
22 | CONFIG_BAT1_NAME="IMMR" | |
23 | CONFIG_BAT1_BASE=0xE0000000 | |
24 | CONFIG_BAT1_LENGTH_4_MBYTES=y | |
25 | CONFIG_BAT1_ACCESS_RW=y | |
26 | CONFIG_BAT1_ICACHE_INHIBITED=y | |
27 | CONFIG_BAT1_ICACHE_GUARDED=y | |
28 | CONFIG_BAT1_DCACHE_INHIBITED=y | |
29 | CONFIG_BAT1_DCACHE_GUARDED=y | |
30 | CONFIG_BAT1_USER_MODE_VALID=y | |
31 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y | |
32 | CONFIG_BAT2=y | |
33 | CONFIG_BAT2_NAME="BCSR" | |
34 | CONFIG_BAT2_BASE=0xF8000000 | |
35 | CONFIG_BAT2_ACCESS_RW=y | |
36 | CONFIG_BAT2_ICACHE_INHIBITED=y | |
37 | CONFIG_BAT2_ICACHE_GUARDED=y | |
38 | CONFIG_BAT2_DCACHE_INHIBITED=y | |
39 | CONFIG_BAT2_DCACHE_GUARDED=y | |
40 | CONFIG_BAT2_USER_MODE_VALID=y | |
41 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y | |
42 | CONFIG_BAT3=y | |
43 | CONFIG_BAT3_NAME="FLASH" | |
44 | CONFIG_BAT3_BASE=0xFE000000 | |
45 | CONFIG_BAT3_LENGTH_32_MBYTES=y | |
46 | CONFIG_BAT3_ACCESS_RW=y | |
47 | CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y | |
48 | CONFIG_BAT3_DCACHE_INHIBITED=y | |
49 | CONFIG_BAT3_DCACHE_GUARDED=y | |
50 | CONFIG_BAT3_USER_MODE_VALID=y | |
51 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y | |
52 | CONFIG_BAT5=y | |
53 | CONFIG_BAT5_NAME="STACK_IN_DCACHE" | |
54 | CONFIG_BAT5_BASE=0xE6000000 | |
55 | CONFIG_BAT5_ACCESS_RW=y | |
56 | CONFIG_BAT5_USER_MODE_VALID=y | |
57 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y | |
58 | CONFIG_BAT6=y | |
59 | CONFIG_BAT6_NAME="PCI_MEM_PHYS" | |
60 | CONFIG_BAT6_BASE=0x80000000 | |
61 | CONFIG_BAT6_LENGTH_256_MBYTES=y | |
62 | CONFIG_BAT6_ACCESS_RW=y | |
63 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y | |
64 | CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y | |
65 | CONFIG_BAT6_USER_MODE_VALID=y | |
66 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y | |
67 | CONFIG_BAT7=y | |
68 | CONFIG_BAT7_NAME="PCI1_MMIO_PHYS" | |
69 | CONFIG_BAT7_BASE=0x90000000 | |
70 | CONFIG_BAT7_LENGTH_256_MBYTES=y | |
71 | CONFIG_BAT7_ACCESS_RW=y | |
72 | CONFIG_BAT7_ICACHE_INHIBITED=y | |
73 | CONFIG_BAT7_ICACHE_GUARDED=y | |
74 | CONFIG_BAT7_DCACHE_INHIBITED=y | |
75 | CONFIG_BAT7_DCACHE_GUARDED=y | |
76 | CONFIG_BAT7_USER_MODE_VALID=y | |
77 | CONFIG_BAT7_SUPERVISOR_MODE_VALID=y | |
9c5df7a2 MS |
78 | CONFIG_LBLAW0=y |
79 | CONFIG_LBLAW0_BASE=0xFE000000 | |
80 | CONFIG_LBLAW0_NAME="FLASH" | |
81 | CONFIG_LBLAW0_LENGTH_32_MBYTES=y | |
82 | CONFIG_LBLAW1=y | |
83 | CONFIG_LBLAW1_BASE=0xF8000000 | |
84 | CONFIG_LBLAW1_NAME="BCSR" | |
85 | CONFIG_LBLAW1_LENGTH_32_KBYTES=y | |
86 | CONFIG_LBLAW3=y | |
87 | CONFIG_LBLAW3_BASE=0xF8008000 | |
88 | CONFIG_LBLAW3_NAME="PIB" | |
89 | CONFIG_LBLAW3_LENGTH_64_KBYTES=y | |
fe7d654d MS |
90 | CONFIG_ELBC_BR0_OR0=y |
91 | CONFIG_BR0_OR0_NAME="FLASH" | |
92 | CONFIG_BR0_OR0_BASE=0xFE000000 | |
fe7d654d MS |
93 | CONFIG_BR0_PORTSIZE_16BIT=y |
94 | CONFIG_OR0_AM_16_MBYTES=y | |
344a0e43 | 95 | CONFIG_OR0_XAM_SET=y |
fe7d654d | 96 | CONFIG_OR0_SCY_15=y |
344a0e43 TR |
97 | CONFIG_OR0_CSNT_EARLIER=y |
98 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y | |
fe7d654d | 99 | CONFIG_OR0_XACS_EXTENDED=y |
fe7d654d MS |
100 | CONFIG_OR0_TRLX_RELAXED=y |
101 | CONFIG_OR0_EHTR_8_CYCLE=y | |
344a0e43 | 102 | CONFIG_OR0_EAD_EXTRA=y |
fe7d654d MS |
103 | CONFIG_ELBC_BR1_OR1=y |
104 | CONFIG_BR1_OR1_NAME="BCSR" | |
105 | CONFIG_BR1_OR1_BASE=0xF8000000 | |
344a0e43 | 106 | CONFIG_OR1_XAM_SET=y |
fe7d654d | 107 | CONFIG_OR1_SCY_15=y |
344a0e43 | 108 | CONFIG_OR1_CSNT_EARLIER=y |
fe7d654d | 109 | CONFIG_OR1_XACS_EXTENDED=y |
fe7d654d MS |
110 | CONFIG_OR1_TRLX_RELAXED=y |
111 | CONFIG_OR1_EHTR_8_CYCLE=y | |
344a0e43 | 112 | CONFIG_OR1_EAD_EXTRA=y |
fe7d654d MS |
113 | CONFIG_ELBC_BR2_OR2=y |
114 | CONFIG_BR2_OR2_NAME="PIB1" | |
115 | CONFIG_BR2_OR2_BASE=0xF8008000 | |
344a0e43 | 116 | CONFIG_OR2_XAM_SET=y |
fe7d654d | 117 | CONFIG_OR2_SCY_15=y |
344a0e43 | 118 | CONFIG_OR2_CSNT_EARLIER=y |
fe7d654d | 119 | CONFIG_OR2_XACS_EXTENDED=y |
fe7d654d MS |
120 | CONFIG_OR2_TRLX_RELAXED=y |
121 | CONFIG_OR2_EHTR_8_CYCLE=y | |
344a0e43 | 122 | CONFIG_OR2_EAD_EXTRA=y |
fe7d654d MS |
123 | CONFIG_ELBC_BR3_OR3=y |
124 | CONFIG_BR3_OR3_NAME="PIB2" | |
125 | CONFIG_BR3_OR3_BASE=0xF8010000 | |
344a0e43 | 126 | CONFIG_OR3_XAM_SET=y |
fe7d654d | 127 | CONFIG_OR3_SCY_15=y |
344a0e43 | 128 | CONFIG_OR3_CSNT_EARLIER=y |
fe7d654d | 129 | CONFIG_OR3_XACS_EXTENDED=y |
fe7d654d MS |
130 | CONFIG_OR3_TRLX_RELAXED=y |
131 | CONFIG_OR3_EHTR_8_CYCLE=y | |
344a0e43 TR |
132 | CONFIG_OR3_EAD_EXTRA=y |
133 | CONFIG_HID0_FINAL_EMCP=y | |
134 | CONFIG_HID0_FINAL_ICE=y | |
135 | CONFIG_HID2_HBE=y | |
7c2e5357 | 136 | CONFIG_LCRR_CLKDIV_2=y |
344a0e43 TR |
137 | CONFIG_OF_BOARD_SETUP=y |
138 | CONFIG_OF_STDOUT_VIA_ALIAS=y | |
139 | CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" | |
140 | CONFIG_BOOTDELAY=6 | |
141 | CONFIG_BOARD_EARLY_INIT_R=y | |
142 | CONFIG_HUSH_PARSER=y | |
143 | CONFIG_CMD_IMLS=y | |
144 | CONFIG_CMD_ASKENV=y | |
145 | CONFIG_CMD_I2C=y | |
146 | CONFIG_CMD_PCI=y | |
147 | # CONFIG_CMD_SETEXPR is not set | |
148 | CONFIG_CMD_PING=y | |
a09fea1d | 149 | CONFIG_ENV_ADDR=0xFE080000 |
344a0e43 TR |
150 | # CONFIG_MMC is not set |
151 | CONFIG_MTD_NOR_FLASH=y | |
152 | CONFIG_FLASH_CFI_DRIVER=y | |
153 | CONFIG_SYS_FLASH_PROTECTION=y | |
154 | CONFIG_SYS_FLASH_CFI=y | |
155 | CONFIG_QE=y | |
156 | CONFIG_SYS_NS16550=y | |
157 | CONFIG_OF_LIBFDT=y |