[J-u-boot.git] / include / configs / maxbcm.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2014 Stefan Roese <[email protected]>
 */

#ifndef _CONFIG_DB_MV7846MP_GP_H
#define _CONFIG_DB_MV7846MP_GP_H

#include <linux/sizes.h>

/*
 * High Level Configuration Options (easy to change)
 */

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */

/* I2C */
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE

/* SPI NOR flash default params, used by sf commands */

/* Environment in SPI NOR flash */

#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000))

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_SYS_SDRAM_SIZE		SZ_1G

#endif /* _CONFIG_DB_MV7846MP_GP_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
a4884831 SR	2	/*
a4884831 SR	3	* Copyright (C) 2014 Stefan Roese <[email protected]>
a4884831 SR	4	*/
	5
	6	#ifndef _CONFIG_DB_MV7846MP_GP_H
	7	#define _CONFIG_DB_MV7846MP_GP_H
	8
94752f5f TR	9	#include <linux/sizes.h>
94752f5f TR	10
a4884831 SR	11	/*
	12	* High Level Configuration Options (easy to change)
	13	*/
a4884831	14
2923c2d2 SR	15	/*
	16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	* for DDR ECC byte filling in the SPL before loading the main
	18	* U-Boot into it.
	19	*/
a4884831	20
a4884831	21	/* I2C */
dd82242b	22	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
a4884831 SR	23
a4884831 SR	24	/* SPI NOR flash default params, used by sf commands */
a4884831 SR	25
a4884831 SR	26	/* Environment in SPI NOR flash */
a4884831	27
a4884831	28	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
a4884831	29
a4884831 SR	30	/*
	31	* mv-common.h should be defined after CMD configs since it used them
	32	* to enable certain macros
	33	*/
	34	#include "mv-common.h"
	35
e7778ec1 SR	36	/*
	37	* Memory layout while starting into the bin_hdr via the
	38	* BootROM:
	39	*
	40	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	41	* 0x4000.4030 bin_hdr start address
	42	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	43	* 0x4007.fffc BootROM stack top
	44	*
	45	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	46	* L2 cache thus cannot be used.
	47	*/
	48
	49	/* SPL */
	50	/* Defines for SPL */
1dcbcc71	51	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000))
e7778ec1 SR	52
	53	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	54	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	55
6451223a SR	56	#ifdef CONFIG_SPL_BUILD
	57	#define CONFIG_SYS_MALLOC_SIMPLE
	58	#endif
e7778ec1 SR	59
	60	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	61	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	62
e7778ec1	63	/* SPL related SPI defines */
e7778ec1 SR	64
e7778ec1 SR	65	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
94752f5f	66	#define CONFIG_SYS_SDRAM_SIZE SZ_1G
e7778ec1	67
a4884831	68	#endif /* _CONFIG_DB_MV7846MP_GP_H */