[J-u-boot.git] / arch / arm / mach-stm32mp / fdt.c

// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY LOGC_ARCH

#include <common.h>
#include <fdtdec.h>
#include <fdt_support.h>
#include <log.h>
#include <tee.h>
#include <asm/arch/sys_proto.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
#include <linux/io.h>

#define ETZPC_DECPROT(n)	(STM32_ETZPC_BASE + 0x10 + 4 * (n))
#define ETZPC_DECPROT_NB	6

#define DECPROT_MASK		0x03
#define NB_PROT_PER_REG		0x10
#define DECPROT_NB_BITS		2

#define DECPROT_SECURED		0x00
#define DECPROT_WRITE_SECURE	0x01
#define DECPROT_MCU_ISOLATION	0x02
#define DECPROT_NON_SECURED	0x03

#define ETZPC_RESERVED		0xffffffff

#define STM32MP13_FDCAN_BASE	0x4400F000
#define STM32MP13_ADC1_BASE	0x48003000
#define STM32MP13_TSC_BASE	0x5000B000
#define STM32MP13_CRYP_BASE	0x54002000
#define STM32MP13_ETH2_BASE	0x5800E000
#define STM32MP13_DCMIPP_BASE	0x5A000000
#define STM32MP13_LTDC_BASE	0x5A010000

#define STM32MP15_FDCAN_BASE	0x4400e000
#define STM32MP15_CRYP2_BASE	0x4c005000
#define STM32MP15_CRYP1_BASE	0x54001000
#define STM32MP15_GPU_BASE	0x59000000
#define STM32MP15_DSI_BASE	0x5a000000

static const u32 stm32mp13_ip_addr[] = {
	0x50025000,		/* 0 VREFBUF APB3 */
	0x50021000,		/* 1 LPTIM2 APB3 */
	0x50022000,		/* 2 LPTIM3 APB3 */
	STM32MP13_LTDC_BASE,	/* 3 LTDC APB4 */
	STM32MP13_DCMIPP_BASE,	/* 4 DCMIPP APB4 */
	0x5A006000,		/* 5 USBPHYCTRL APB4 */
	0x5A003000,		/* 6 DDRCTRLPHY APB4 */
	ETZPC_RESERVED,		/* 7 Reserved*/
	ETZPC_RESERVED,		/* 8 Reserved*/
	ETZPC_RESERVED,		/* 9 Reserved*/
	0x5C006000,		/* 10 TZC APB5 */
	0x58001000,		/* 11 MCE APB5 */
	0x5C000000,		/* 12 IWDG1 APB5 */
	0x5C008000,		/* 13 STGENC APB5 */
	ETZPC_RESERVED,		/* 14 Reserved*/
	ETZPC_RESERVED,		/* 15 Reserved*/
	0x4C000000,		/* 16 USART1 APB6 */
	0x4C001000,		/* 17 USART2 APB6 */
	0x4C002000,		/* 18 SPI4 APB6 */
	0x4C003000,		/* 19 SPI5 APB6 */
	0x4C004000,		/* 20 I2C3 APB6 */
	0x4C005000,		/* 21 I2C4 APB6 */
	0x4C006000,		/* 22 I2C5 APB6 */
	0x4C007000,		/* 23 TIM12 APB6 */
	0x4C008000,		/* 24 TIM13 APB6 */
	0x4C009000,		/* 25 TIM14 APB6 */
	0x4C00A000,		/* 26 TIM15 APB6 */
	0x4C00B000,		/* 27 TIM16 APB6 */
	0x4C00C000,		/* 28 TIM17 APB6 */
	ETZPC_RESERVED,		/* 29 Reserved*/
	ETZPC_RESERVED,		/* 30 Reserved*/
	ETZPC_RESERVED,		/* 31 Reserved*/
	STM32MP13_ADC1_BASE,	/* 32 ADC1 AHB2 */
	0x48004000,		/* 33 ADC2 AHB2 */
	0x49000000,		/* 34 OTG AHB2 */
	ETZPC_RESERVED,		/* 35 Reserved*/
	ETZPC_RESERVED,		/* 36 Reserved*/
	STM32MP13_TSC_BASE,	/* 37 TSC AHB4 */
	ETZPC_RESERVED,		/* 38 Reserved*/
	ETZPC_RESERVED,		/* 39 Reserved*/
	0x54004000,		/* 40 RNG AHB5 */
	0x54003000,		/* 41 HASH AHB5 */
	STM32MP13_CRYP_BASE,	/* 42 CRYPT AHB5 */
	0x54005000,		/* 43 SAES AHB5 */
	0x54006000,		/* 44 PKA AHB5 */
	0x54000000,		/* 45 BKPSRAM AHB5 */
	ETZPC_RESERVED,		/* 46 Reserved*/
	ETZPC_RESERVED,		/* 47 Reserved*/
	0x5800A000,		/* 48 ETH1 AHB6 */
	STM32MP13_ETH2_BASE,	/* 49 ETH2 AHB6 */
	0x58005000,		/* 50 SDMMC1 AHB6 */
	0x58007000,		/* 51 SDMMC2 AHB6 */
	ETZPC_RESERVED,		/* 52 Reserved*/
	ETZPC_RESERVED,		/* 53 Reserved*/
	0x58002000,		/* 54 FMC AHB6 */
	0x58003000,		/* 55 QSPI AHB6 */
	ETZPC_RESERVED,		/* 56 Reserved*/
	ETZPC_RESERVED,		/* 57 Reserved*/
	ETZPC_RESERVED,		/* 58 Reserved*/
	ETZPC_RESERVED,		/* 59 Reserved*/
	0x30000000,		/* 60 SRAM1 MLAHB */
	0x30004000,		/* 61 SRAM2 MLAHB */
	0x30006000,		/* 62 SRAM3 MLAHB */
	ETZPC_RESERVED,		/* 63 Reserved*/
	ETZPC_RESERVED,		/* 64 Reserved*/
	ETZPC_RESERVED,		/* 65 Reserved*/
	ETZPC_RESERVED,		/* 66 Reserved*/
	ETZPC_RESERVED,		/* 67 Reserved*/
	ETZPC_RESERVED,		/* 68 Reserved*/
	ETZPC_RESERVED,		/* 69 Reserved*/
	ETZPC_RESERVED,		/* 70 Reserved*/
	ETZPC_RESERVED,		/* 71 Reserved*/
	ETZPC_RESERVED,		/* 72 Reserved*/
	ETZPC_RESERVED,		/* 73 Reserved*/
	ETZPC_RESERVED,		/* 74 Reserved*/
	ETZPC_RESERVED,		/* 75 Reserved*/
	ETZPC_RESERVED,		/* 76 Reserved*/
	ETZPC_RESERVED,		/* 77 Reserved*/
	ETZPC_RESERVED,		/* 78 Reserved*/
	ETZPC_RESERVED,		/* 79 Reserved*/
	ETZPC_RESERVED,		/* 80 Reserved*/
	ETZPC_RESERVED,		/* 81 Reserved*/
	ETZPC_RESERVED,		/* 82 Reserved*/
	ETZPC_RESERVED,		/* 83 Reserved*/
	ETZPC_RESERVED,		/* 84 Reserved*/
	ETZPC_RESERVED,		/* 85 Reserved*/
	ETZPC_RESERVED,		/* 86 Reserved*/
	ETZPC_RESERVED,		/* 87 Reserved*/
	ETZPC_RESERVED,		/* 88 Reserved*/
	ETZPC_RESERVED,		/* 89 Reserved*/
	ETZPC_RESERVED,		/* 90 Reserved*/
	ETZPC_RESERVED,		/* 91 Reserved*/
	ETZPC_RESERVED,		/* 92 Reserved*/
	ETZPC_RESERVED,		/* 93 Reserved*/
	ETZPC_RESERVED,		/* 94 Reserved*/
	ETZPC_RESERVED,		/* 95 Reserved*/
};

static const u32 stm32mp15_ip_addr[] = {
	0x5c008000,	/* 00 stgenc */
	0x54000000,	/* 01 bkpsram */
	0x5c003000,	/* 02 iwdg1 */
	0x5c000000,	/* 03 usart1 */
	0x5c001000,	/* 04 spi6 */
	0x5c002000,	/* 05 i2c4 */
	ETZPC_RESERVED,	/* 06 reserved */
	0x54003000,	/* 07 rng1 */
	0x54002000,	/* 08 hash1 */
	STM32MP15_CRYP1_BASE,	/* 09 cryp1 */
	0x5a003000,	/* 0A ddrctrl */
	0x5a004000,	/* 0B ddrphyc */
	0x5c009000,	/* 0C i2c6 */
	ETZPC_RESERVED,	/* 0D reserved */
	ETZPC_RESERVED,	/* 0E reserved */
	ETZPC_RESERVED,	/* 0F reserved */
	0x40000000,	/* 10 tim2 */
	0x40001000,	/* 11 tim3 */
	0x40002000,	/* 12 tim4 */
	0x40003000,	/* 13 tim5 */
	0x40004000,	/* 14 tim6 */
	0x40005000,	/* 15 tim7 */
	0x40006000,	/* 16 tim12 */
	0x40007000,	/* 17 tim13 */
	0x40008000,	/* 18 tim14 */
	0x40009000,	/* 19 lptim1 */
	0x4000a000,	/* 1A wwdg1 */
	0x4000b000,	/* 1B spi2 */
	0x4000c000,	/* 1C spi3 */
	0x4000d000,	/* 1D spdifrx */
	0x4000e000,	/* 1E usart2 */
	0x4000f000,	/* 1F usart3 */
	0x40010000,	/* 20 uart4 */
	0x40011000,	/* 21 uart5 */
	0x40012000,	/* 22 i2c1 */
	0x40013000,	/* 23 i2c2 */
	0x40014000,	/* 24 i2c3 */
	0x40015000,	/* 25 i2c5 */
	0x40016000,	/* 26 cec */
	0x40017000,	/* 27 dac */
	0x40018000,	/* 28 uart7 */
	0x40019000,	/* 29 uart8 */
	ETZPC_RESERVED,	/* 2A reserved */
	ETZPC_RESERVED,	/* 2B reserved */
	0x4001c000,	/* 2C mdios */
	ETZPC_RESERVED,	/* 2D reserved */
	ETZPC_RESERVED,	/* 2E reserved */
	ETZPC_RESERVED,	/* 2F reserved */
	0x44000000,	/* 30 tim1 */
	0x44001000,	/* 31 tim8 */
	ETZPC_RESERVED,	/* 32 reserved */
	0x44003000,	/* 33 usart6 */
	0x44004000,	/* 34 spi1 */
	0x44005000,	/* 35 spi4 */
	0x44006000,	/* 36 tim15 */
	0x44007000,	/* 37 tim16 */
	0x44008000,	/* 38 tim17 */
	0x44009000,	/* 39 spi5 */
	0x4400a000,	/* 3A sai1 */
	0x4400b000,	/* 3B sai2 */
	0x4400c000,	/* 3C sai3 */
	0x4400d000,	/* 3D dfsdm */
	STM32MP15_FDCAN_BASE,	/* 3E tt_fdcan */
	ETZPC_RESERVED,	/* 3F reserved */
	0x50021000,	/* 40 lptim2 */
	0x50022000,	/* 41 lptim3 */
	0x50023000,	/* 42 lptim4 */
	0x50024000,	/* 43 lptim5 */
	0x50027000,	/* 44 sai4 */
	0x50025000,	/* 45 vrefbuf */
	0x4c006000,	/* 46 dcmi */
	0x4c004000,	/* 47 crc2 */
	0x48003000,	/* 48 adc */
	0x4c002000,	/* 49 hash2 */
	0x4c003000,	/* 4A rng2 */
	STM32MP15_CRYP2_BASE,	/* 4B cryp2 */
	ETZPC_RESERVED,	/* 4C reserved */
	ETZPC_RESERVED,	/* 4D reserved */
	ETZPC_RESERVED,	/* 4E reserved */
	ETZPC_RESERVED,	/* 4F reserved */
	ETZPC_RESERVED,	/* 50 sram1 */
	ETZPC_RESERVED,	/* 51 sram2 */
	ETZPC_RESERVED,	/* 52 sram3 */
	ETZPC_RESERVED,	/* 53 sram4 */
	ETZPC_RESERVED,	/* 54 retram */
	0x49000000,	/* 55 otg */
	0x48004000,	/* 56 sdmmc3 */
	0x48005000,	/* 57 dlybsd3 */
	0x48000000,	/* 58 dma1 */
	0x48001000,	/* 59 dma2 */
	0x48002000,	/* 5A dmamux */
	0x58002000,	/* 5B fmc */
	0x58003000,	/* 5C qspi */
	0x58004000,	/* 5D dlybq */
	0x5800a000,	/* 5E eth */
	ETZPC_RESERVED,	/* 5F reserved */
};

/* fdt helper */
static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
{
	int node;
	fdt_addr_t regs;

	for (node = fdt_first_subnode(fdt, offset);
	     node >= 0;
	     node = fdt_next_subnode(fdt, node)) {
		regs = fdtdec_get_addr(fdt, node, "reg");
		if (addr == regs) {
			if (fdtdec_get_is_enabled(fdt, node)) {
				fdt_status_disabled(fdt, node);

				return true;
			}
			return false;
		}
	}

	return false;
}

static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
{
	const u32 *array;
	int array_size, i;
	int offset, shift;
	u32 addr, status, decprot[ETZPC_DECPROT_NB];

	if (IS_ENABLED(CONFIG_STM32MP13x)) {
		array = stm32mp13_ip_addr;
		array_size = ARRAY_SIZE(stm32mp13_ip_addr);
	}

	if (IS_ENABLED(CONFIG_STM32MP15x)) {
		array = stm32mp15_ip_addr;
		array_size = ARRAY_SIZE(stm32mp15_ip_addr);
	}

	for (i = 0; i < ETZPC_DECPROT_NB; i++)
		decprot[i] = readl(ETZPC_DECPROT(i));

	for (i = 0; i < array_size; i++) {
		offset = i / NB_PROT_PER_REG;
		shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
		status = (decprot[offset] >> shift) & DECPROT_MASK;
		addr = array[i];

		log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);

		if (addr == ETZPC_RESERVED ||
		    status == DECPROT_NON_SECURED)
			continue;

		if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
			log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
				   addr, i, status);
	}

	return 0;
}

/* deactivate all the cpu except core 0 */
static void stm32_fdt_fixup_cpu(void *blob, char *name)
{
	int off;
	u32 reg;

	off = fdt_path_offset(blob, "/cpus");
	if (off < 0) {
		log_warning("%s: couldn't find /cpus node\n", __func__);
		return;
	}

	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	while (off != -FDT_ERR_NOTFOUND) {
		reg = fdtdec_get_addr(blob, off, "reg");
		if (reg != 0) {
			fdt_del_node(blob, off);
			log_notice("FDT: cpu %d node remove for %s\n",
				   reg, name);
			/* after delete we can't trust the offsets anymore */
			off = -1;
		}
		off = fdt_node_offset_by_prop_value(blob, off,
						    "device_type", "cpu", 4);
	}
}

static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
			      const char *string, const char *name)
{
	if (fdt_disable_subnode_by_address(fdt, offset, addr))
		log_notice("FDT: %s@%08x node disabled for %s\n",
			   string, addr, name);
}

static void stm32_fdt_disable_optee(void *blob)
{
	int off, node;

	/* Delete "optee" firmware node */
	off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
	if (off >= 0 && fdtdec_get_is_enabled(blob, off))
		fdt_del_node(blob, off);

	/* Delete "optee@..." reserved-memory node */
	off = fdt_path_offset(blob, "/reserved-memory/");
	if (off < 0)
		return;
	for (node = fdt_first_subnode(blob, off);
	     node >= 0;
	     node = fdt_next_subnode(blob, node)) {
		if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
			continue;

		if (fdt_del_node(blob, node))
			printf("Failed to remove optee reserved-memory node\n");
	}
}

static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
{
	switch (cpu) {
	case CPU_STM32MP131Fxx:
	case CPU_STM32MP131Dxx:
	case CPU_STM32MP131Cxx:
	case CPU_STM32MP131Axx:
		stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
		stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
		fallthrough;
	case CPU_STM32MP133Fxx:
	case CPU_STM32MP133Dxx:
	case CPU_STM32MP133Cxx:
	case CPU_STM32MP133Axx:
		stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
		stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
				  name);
		stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
		break;
	default:
		break;
	}

	switch (cpu) {
	case CPU_STM32MP135Dxx:
	case CPU_STM32MP135Axx:
	case CPU_STM32MP133Dxx:
	case CPU_STM32MP133Axx:
	case CPU_STM32MP131Dxx:
	case CPU_STM32MP131Axx:
		stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
		break;
	default:
		break;
	}
}

static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name)
{
	u32 pkg;

	switch (cpu) {
	case CPU_STM32MP151Fxx:
	case CPU_STM32MP151Dxx:
	case CPU_STM32MP151Cxx:
	case CPU_STM32MP151Axx:
		stm32_fdt_fixup_cpu(blob, name);
		/* after cpu delete we can't trust the soc offsets anymore */
		soc = fdt_path_offset(blob, "/soc");
		stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
		fallthrough;
	case CPU_STM32MP153Fxx:
	case CPU_STM32MP153Dxx:
	case CPU_STM32MP153Cxx:
	case CPU_STM32MP153Axx:
		stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
		stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
		break;
	default:
		break;
	}
	switch (cpu) {
	case CPU_STM32MP157Dxx:
	case CPU_STM32MP157Axx:
	case CPU_STM32MP153Dxx:
	case CPU_STM32MP153Axx:
	case CPU_STM32MP151Dxx:
	case CPU_STM32MP151Axx:
		stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
				  name);
		stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
				  name);
		break;
	default:
		break;
	}
	switch (get_cpu_package()) {
	case STM32MP15_PKG_AA_LBGA448:
		pkg = STM32MP_PKG_AA;
		break;
	case STM32MP15_PKG_AB_LBGA354:
		pkg = STM32MP_PKG_AB;
		break;
	case STM32MP15_PKG_AC_TFBGA361:
		pkg = STM32MP_PKG_AC;
		break;
	case STM32MP15_PKG_AD_TFBGA257:
		pkg = STM32MP_PKG_AD;
		break;
	default:
		pkg = 0;
		break;
	}
	if (pkg) {
		do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
				       "st,package", pkg, false);
		do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
				       "st,package", pkg, false);
	}
}

/*
 * This function is called right before the kernel is booted. "blob" is the
 * device tree that will be passed to the kernel.
 */
int ft_system_setup(void *blob, struct bd_info *bd)
{
	int ret = 0;
	int soc;
	u32 cpu;
	char name[SOC_NAME_SIZE];

	soc = fdt_path_offset(blob, "/soc");
	/* when absent, nothing to do */
	if (soc == -FDT_ERR_NOTFOUND)
		return 0;
	if (soc < 0)
		return soc;

	if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
		ret = stm32_fdt_fixup_etzpc(blob, soc);
		if (ret)
			return ret;
	}

	/* MPUs Part Numbers and name*/
	cpu = get_cpu_type();
	get_soc_name(name);

	if (IS_ENABLED(CONFIG_STM32MP13x))
		stm32mp13_fdt_fixup(blob, soc, cpu, name);

	if (IS_ENABLED(CONFIG_STM32MP15x)) {
		stm32mp15_fdt_fixup(blob, soc, cpu, name);

		/*
		 * TEMP: remove OP-TEE nodes in kernel device tree
		 *       copied from U-Boot device tree by optee_copy_fdt_nodes
		 *       when OP-TEE is not detected (probe failed)
		 * these OP-TEE nodes are present in <board>-u-boot.dtsi
		 * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
		 * when FIP is not used by TF-A
		 */
		if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
		    !tee_find_device(NULL, NULL, NULL, NULL))
			stm32_fdt_disable_optee(blob);
	}

	return ret;
}
Commit	Line	Data
05d36936 PD	1	// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
05d36936 PD	2	/*
164873a0	3	* Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
05d36936 PD	4	*/
05d36936 PD	5
eb653acd PD	6	#define LOG_CATEGORY LOGC_ARCH
eb653acd PD	7
05d36936	8	#include <common.h>
401d1c4f	9	#include <fdtdec.h>
05d36936	10	#include <fdt_support.h>
f7ae49fc	11	#include <log.h>
43df0a15	12	#include <tee.h>
05d36936 PD	13	#include <asm/arch/sys_proto.h>
05d36936 PD	14	#include <dt-bindings/pinctrl/stm32-pinfunc.h>
c60f3b35 PD	15	#include <linux/io.h>
	16
	17	#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
	18	#define ETZPC_DECPROT_NB 6
	19
	20	#define DECPROT_MASK 0x03
	21	#define NB_PROT_PER_REG 0x10
	22	#define DECPROT_NB_BITS 2
	23
	24	#define DECPROT_SECURED 0x00
	25	#define DECPROT_WRITE_SECURE 0x01
	26	#define DECPROT_MCU_ISOLATION 0x02
	27	#define DECPROT_NON_SECURED 0x03
	28
	29	#define ETZPC_RESERVED 0xffffffff
	30
df68a309 PD	31	#define STM32MP13_FDCAN_BASE 0x4400F000
	32	#define STM32MP13_ADC1_BASE 0x48003000
	33	#define STM32MP13_TSC_BASE 0x5000B000
	34	#define STM32MP13_CRYP_BASE 0x54002000
	35	#define STM32MP13_ETH2_BASE 0x5800E000
	36	#define STM32MP13_DCMIPP_BASE 0x5A000000
	37	#define STM32MP13_LTDC_BASE 0x5A010000
	38
ca9c9e7e PD	39	#define STM32MP15_FDCAN_BASE 0x4400e000
	40	#define STM32MP15_CRYP2_BASE 0x4c005000
	41	#define STM32MP15_CRYP1_BASE 0x54001000
	42	#define STM32MP15_GPU_BASE 0x59000000
	43	#define STM32MP15_DSI_BASE 0x5a000000
73306a12	44
df68a309 PD	45	static const u32 stm32mp13_ip_addr[] = {
	46	0x50025000, /* 0 VREFBUF APB3 */
	47	0x50021000, /* 1 LPTIM2 APB3 */
	48	0x50022000, /* 2 LPTIM3 APB3 */
	49	STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
	50	STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
	51	0x5A006000, /* 5 USBPHYCTRL APB4 */
	52	0x5A003000, /* 6 DDRCTRLPHY APB4 */
	53	ETZPC_RESERVED, /* 7 Reserved*/
	54	ETZPC_RESERVED, /* 8 Reserved*/
	55	ETZPC_RESERVED, /* 9 Reserved*/
	56	0x5C006000, /* 10 TZC APB5 */
	57	0x58001000, /* 11 MCE APB5 */
	58	0x5C000000, /* 12 IWDG1 APB5 */
	59	0x5C008000, /* 13 STGENC APB5 */
	60	ETZPC_RESERVED, /* 14 Reserved*/
	61	ETZPC_RESERVED, /* 15 Reserved*/
	62	0x4C000000, /* 16 USART1 APB6 */
	63	0x4C001000, /* 17 USART2 APB6 */
	64	0x4C002000, /* 18 SPI4 APB6 */
	65	0x4C003000, /* 19 SPI5 APB6 */
	66	0x4C004000, /* 20 I2C3 APB6 */
	67	0x4C005000, /* 21 I2C4 APB6 */
	68	0x4C006000, /* 22 I2C5 APB6 */
	69	0x4C007000, /* 23 TIM12 APB6 */
	70	0x4C008000, /* 24 TIM13 APB6 */
	71	0x4C009000, /* 25 TIM14 APB6 */
	72	0x4C00A000, /* 26 TIM15 APB6 */
	73	0x4C00B000, /* 27 TIM16 APB6 */
	74	0x4C00C000, /* 28 TIM17 APB6 */
	75	ETZPC_RESERVED, /* 29 Reserved*/
	76	ETZPC_RESERVED, /* 30 Reserved*/
	77	ETZPC_RESERVED, /* 31 Reserved*/
	78	STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
	79	0x48004000, /* 33 ADC2 AHB2 */
	80	0x49000000, /* 34 OTG AHB2 */
	81	ETZPC_RESERVED, /* 35 Reserved*/
	82	ETZPC_RESERVED, /* 36 Reserved*/
	83	STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
	84	ETZPC_RESERVED, /* 38 Reserved*/
	85	ETZPC_RESERVED, /* 39 Reserved*/
	86	0x54004000, /* 40 RNG AHB5 */
	87	0x54003000, /* 41 HASH AHB5 */
	88	STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
	89	0x54005000, /* 43 SAES AHB5 */
	90	0x54006000, /* 44 PKA AHB5 */
	91	0x54000000, /* 45 BKPSRAM AHB5 */
	92	ETZPC_RESERVED, /* 46 Reserved*/
	93	ETZPC_RESERVED, /* 47 Reserved*/
	94	0x5800A000, /* 48 ETH1 AHB6 */
	95	STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
	96	0x58005000, /* 50 SDMMC1 AHB6 */
	97	0x58007000, /* 51 SDMMC2 AHB6 */
	98	ETZPC_RESERVED, /* 52 Reserved*/
	99	ETZPC_RESERVED, /* 53 Reserved*/
	100	0x58002000, /* 54 FMC AHB6 */
	101	0x58003000, /* 55 QSPI AHB6 */
	102	ETZPC_RESERVED, /* 56 Reserved*/
	103	ETZPC_RESERVED, /* 57 Reserved*/
	104	ETZPC_RESERVED, /* 58 Reserved*/
	105	ETZPC_RESERVED, /* 59 Reserved*/
	106	0x30000000, /* 60 SRAM1 MLAHB */
	107	0x30004000, /* 61 SRAM2 MLAHB */
	108	0x30006000, /* 62 SRAM3 MLAHB */
109	ETZPC_RESERVED, /* 63 Reserved*/
110	ETZPC_RESERVED, /* 64 Reserved*/
111	ETZPC_RESERVED, /* 65 Reserved*/
112	ETZPC_RESERVED, /* 66 Reserved*/
113	ETZPC_RESERVED, /* 67 Reserved*/
114	ETZPC_RESERVED, /* 68 Reserved*/
115	ETZPC_RESERVED, /* 69 Reserved*/
116	ETZPC_RESERVED, /* 70 Reserved*/
117	ETZPC_RESERVED, /* 71 Reserved*/
118	ETZPC_RESERVED, /* 72 Reserved*/
119	ETZPC_RESERVED, /* 73 Reserved*/
120	ETZPC_RESERVED, /* 74 Reserved*/
121	ETZPC_RESERVED, /* 75 Reserved*/
122	ETZPC_RESERVED, /* 76 Reserved*/
123	ETZPC_RESERVED, /* 77 Reserved*/
124	ETZPC_RESERVED, /* 78 Reserved*/
125	ETZPC_RESERVED, /* 79 Reserved*/
126	ETZPC_RESERVED, /* 80 Reserved*/
127	ETZPC_RESERVED, /* 81 Reserved*/
128	ETZPC_RESERVED, /* 82 Reserved*/
129	ETZPC_RESERVED, /* 83 Reserved*/
130	ETZPC_RESERVED, /* 84 Reserved*/
131	ETZPC_RESERVED, /* 85 Reserved*/
132	ETZPC_RESERVED, /* 86 Reserved*/
133	ETZPC_RESERVED, /* 87 Reserved*/
134	ETZPC_RESERVED, /* 88 Reserved*/
135	ETZPC_RESERVED, /* 89 Reserved*/
136	ETZPC_RESERVED, /* 90 Reserved*/
137	ETZPC_RESERVED, /* 91 Reserved*/
138	ETZPC_RESERVED, /* 92 Reserved*/
139	ETZPC_RESERVED, /* 93 Reserved*/
140	ETZPC_RESERVED, /* 94 Reserved*/
141	ETZPC_RESERVED, /* 95 Reserved*/
142	};
143
ca9c9e7e	144	static const u32 stm32mp15_ip_addr[] = {
c60f3b35 PD	145	0x5c008000, /* 00 stgenc */
	146	0x54000000, /* 01 bkpsram */
	147	0x5c003000, /* 02 iwdg1 */
	148	0x5c000000, /* 03 usart1 */
	149	0x5c001000, /* 04 spi6 */
	150	0x5c002000, /* 05 i2c4 */
	151	ETZPC_RESERVED, /* 06 reserved */
	152	0x54003000, /* 07 rng1 */
	153	0x54002000, /* 08 hash1 */
ca9c9e7e	154	STM32MP15_CRYP1_BASE, /* 09 cryp1 */
c60f3b35 PD	155	0x5a003000, /* 0A ddrctrl */
	156	0x5a004000, /* 0B ddrphyc */
	157	0x5c009000, /* 0C i2c6 */
	158	ETZPC_RESERVED, /* 0D reserved */
	159	ETZPC_RESERVED, /* 0E reserved */
	160	ETZPC_RESERVED, /* 0F reserved */
	161	0x40000000, /* 10 tim2 */
	162	0x40001000, /* 11 tim3 */
	163	0x40002000, /* 12 tim4 */
	164	0x40003000, /* 13 tim5 */
	165	0x40004000, /* 14 tim6 */
	166	0x40005000, /* 15 tim7 */
	167	0x40006000, /* 16 tim12 */
	168	0x40007000, /* 17 tim13 */
	169	0x40008000, /* 18 tim14 */
	170	0x40009000, /* 19 lptim1 */
	171	0x4000a000, /* 1A wwdg1 */
	172	0x4000b000, /* 1B spi2 */
	173	0x4000c000, /* 1C spi3 */
	174	0x4000d000, /* 1D spdifrx */
	175	0x4000e000, /* 1E usart2 */
	176	0x4000f000, /* 1F usart3 */
	177	0x40010000, /* 20 uart4 */
	178	0x40011000, /* 21 uart5 */
	179	0x40012000, /* 22 i2c1 */
	180	0x40013000, /* 23 i2c2 */
	181	0x40014000, /* 24 i2c3 */
	182	0x40015000, /* 25 i2c5 */
	183	0x40016000, /* 26 cec */
	184	0x40017000, /* 27 dac */
	185	0x40018000, /* 28 uart7 */
	186	0x40019000, /* 29 uart8 */
	187	ETZPC_RESERVED, /* 2A reserved */
	188	ETZPC_RESERVED, /* 2B reserved */
	189	0x4001c000, /* 2C mdios */
	190	ETZPC_RESERVED, /* 2D reserved */
	191	ETZPC_RESERVED, /* 2E reserved */
	192	ETZPC_RESERVED, /* 2F reserved */
	193	0x44000000, /* 30 tim1 */
	194	0x44001000, /* 31 tim8 */
	195	ETZPC_RESERVED, /* 32 reserved */
	196	0x44003000, /* 33 usart6 */
	197	0x44004000, /* 34 spi1 */
	198	0x44005000, /* 35 spi4 */
	199	0x44006000, /* 36 tim15 */
	200	0x44007000, /* 37 tim16 */
	201	0x44008000, /* 38 tim17 */
	202	0x44009000, /* 39 spi5 */
	203	0x4400a000, /* 3A sai1 */
	204	0x4400b000, /* 3B sai2 */
	205	0x4400c000, /* 3C sai3 */
	206	0x4400d000, /* 3D dfsdm */
ca9c9e7e	207	STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
c60f3b35 PD	208	ETZPC_RESERVED, /* 3F reserved */
	209	0x50021000, /* 40 lptim2 */
	210	0x50022000, /* 41 lptim3 */
	211	0x50023000, /* 42 lptim4 */
	212	0x50024000, /* 43 lptim5 */
	213	0x50027000, /* 44 sai4 */
	214	0x50025000, /* 45 vrefbuf */
	215	0x4c006000, /* 46 dcmi */
	216	0x4c004000, /* 47 crc2 */
	217	0x48003000, /* 48 adc */
	218	0x4c002000, /* 49 hash2 */
	219	0x4c003000, /* 4A rng2 */
ca9c9e7e	220	STM32MP15_CRYP2_BASE, /* 4B cryp2 */
c60f3b35 PD	221	ETZPC_RESERVED, /* 4C reserved */
	222	ETZPC_RESERVED, /* 4D reserved */
	223	ETZPC_RESERVED, /* 4E reserved */
	224	ETZPC_RESERVED, /* 4F reserved */
	225	ETZPC_RESERVED, /* 50 sram1 */
	226	ETZPC_RESERVED, /* 51 sram2 */
	227	ETZPC_RESERVED, /* 52 sram3 */
	228	ETZPC_RESERVED, /* 53 sram4 */
	229	ETZPC_RESERVED, /* 54 retram */
	230	0x49000000, /* 55 otg */
	231	0x48004000, /* 56 sdmmc3 */
	232	0x48005000, /* 57 dlybsd3 */
	233	0x48000000, /* 58 dma1 */
	234	0x48001000, /* 59 dma2 */
	235	0x48002000, /* 5A dmamux */
	236	0x58002000, /* 5B fmc */
	237	0x58003000, /* 5C qspi */
	238	0x58004000, /* 5D dlybq */
	239	0x5800a000, /* 5E eth */
	240	ETZPC_RESERVED, /* 5F reserved */
	241	};
	242
	243	/* fdt helper */
	244	static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
	245	{
	246	int node;
73306a12	247	fdt_addr_t regs;
c60f3b35 PD	248
	249	for (node = fdt_first_subnode(fdt, offset);
	250	node >= 0;
	251	node = fdt_next_subnode(fdt, node)) {
73306a12 PD	252	regs = fdtdec_get_addr(fdt, node, "reg");
73306a12 PD	253	if (addr == regs) {
c60f3b35 PD	254	if (fdtdec_get_is_enabled(fdt, node)) {
	255	fdt_status_disabled(fdt, node);
	256
	257	return true;
	258	}
	259	return false;
	260	}
	261	}
	262
	263	return false;
	264	}
	265
73306a12	266	static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
c60f3b35 PD	267	{
	268	const u32 *array;
	269	int array_size, i;
73306a12	270	int offset, shift;
c60f3b35 PD	271	u32 addr, status, decprot[ETZPC_DECPROT_NB];
c60f3b35 PD	272
df68a309 PD	273	if (IS_ENABLED(CONFIG_STM32MP13x)) {
	274	array = stm32mp13_ip_addr;
	275	array_size = ARRAY_SIZE(stm32mp13_ip_addr);
	276	}
ca9c9e7e PD	277
	278	if (IS_ENABLED(CONFIG_STM32MP15x)) {
	279	array = stm32mp15_ip_addr;
	280	array_size = ARRAY_SIZE(stm32mp15_ip_addr);
	281	}
c60f3b35 PD	282
	283	for (i = 0; i < ETZPC_DECPROT_NB; i++)
	284	decprot[i] = readl(ETZPC_DECPROT(i));
	285
c60f3b35 PD	286	for (i = 0; i < array_size; i++) {
	287	offset = i / NB_PROT_PER_REG;
	288	shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
	289	status = (decprot[offset] >> shift) & DECPROT_MASK;
	290	addr = array[i];
	291
eb653acd	292	log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
c60f3b35 PD	293
	294	if (addr == ETZPC_RESERVED \|\|
	295	status == DECPROT_NON_SECURED)
	296	continue;
	297
	298	if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
eb653acd PD	299	log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
eb653acd PD	300	addr, i, status);
c60f3b35 PD	301	}
	302
	303	return 0;
	304	}
05d36936	305
73306a12 PD	306	/* deactivate all the cpu except core 0 */
	307	static void stm32_fdt_fixup_cpu(void blob, char name)
	308	{
	309	int off;
	310	u32 reg;
	311
	312	off = fdt_path_offset(blob, "/cpus");
	313	if (off < 0) {
eb653acd	314	log_warning("%s: couldn't find /cpus node\n", __func__);
73306a12 PD	315	return;
	316	}
	317
	318	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
	319	while (off != -FDT_ERR_NOTFOUND) {
	320	reg = fdtdec_get_addr(blob, off, "reg");
	321	if (reg != 0) {
	322	fdt_del_node(blob, off);
eb653acd PD	323	log_notice("FDT: cpu %d node remove for %s\n",
eb653acd PD	324	reg, name);
73306a12 PD	325	/* after delete we can't trust the offsets anymore */
	326	off = -1;
	327	}
	328	off = fdt_node_offset_by_prop_value(blob, off,
	329	"device_type", "cpu", 4);
	330	}
	331	}
	332
	333	static void stm32_fdt_disable(void *fdt, int offset, u32 addr,
	334	const char string, const char name)
	335	{
	336	if (fdt_disable_subnode_by_address(fdt, offset, addr))
eb653acd PD	337	log_notice("FDT: %s@%08x node disabled for %s\n",
eb653acd PD	338	string, addr, name);
73306a12 PD	339	}
73306a12 PD	340
4a1b975d PD	341	static void stm32_fdt_disable_optee(void *blob)
	342	{
	343	int off, node;
	344
164873a0	345	/* Delete "optee" firmware node */
4a1b975d PD	346	off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
4a1b975d PD	347	if (off >= 0 && fdtdec_get_is_enabled(blob, off))
164873a0	348	fdt_del_node(blob, off);
4a1b975d	349
164873a0	350	/* Delete "optee@..." reserved-memory node */
4a1b975d PD	351	off = fdt_path_offset(blob, "/reserved-memory/");
	352	if (off < 0)
	353	return;
	354	for (node = fdt_first_subnode(blob, off);
	355	node >= 0;
	356	node = fdt_next_subnode(blob, node)) {
164873a0 EC	357	if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
	358	continue;
	359
	360	if (fdt_del_node(blob, node))
	361	printf("Failed to remove optee reserved-memory node\n");
4a1b975d PD	362	}
	363	}
	364
df68a309 PD	365	static void stm32mp13_fdt_fixup(void blob, int soc, u32 cpu, char name)
	366	{
	367	switch (cpu) {
	368	case CPU_STM32MP131Fxx:
	369	case CPU_STM32MP131Dxx:
	370	case CPU_STM32MP131Cxx:
	371	case CPU_STM32MP131Axx:
	372	stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name);
	373	stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name);
	374	fallthrough;
	375	case CPU_STM32MP133Fxx:
	376	case CPU_STM32MP133Dxx:
	377	case CPU_STM32MP133Cxx:
	378	case CPU_STM32MP133Axx:
	379	stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name);
	380	stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp",
	381	name);
	382	stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name);
	383	break;
	384	default:
	385	break;
	386	}
	387
	388	switch (cpu) {
	389	case CPU_STM32MP135Dxx:
	390	case CPU_STM32MP135Axx:
	391	case CPU_STM32MP133Dxx:
	392	case CPU_STM32MP133Axx:
	393	case CPU_STM32MP131Dxx:
	394	case CPU_STM32MP131Axx:
	395	stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name);
	396	break;
	397	default:
	398	break;
	399	}
	400	}
	401
ca9c9e7e	402	static void stm32mp15_fdt_fixup(void blob, int soc, u32 cpu, char name)
05d36936	403	{
ca9c9e7e	404	u32 pkg;
73306a12 PD	405
73306a12 PD	406	switch (cpu) {
050fed8a PD	407	case CPU_STM32MP151Fxx:
050fed8a PD	408	case CPU_STM32MP151Dxx:
73306a12 PD	409	case CPU_STM32MP151Cxx:
	410	case CPU_STM32MP151Axx:
	411	stm32_fdt_fixup_cpu(blob, name);
	412	/* after cpu delete we can't trust the soc offsets anymore */
	413	soc = fdt_path_offset(blob, "/soc");
ca9c9e7e PD	414	stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name);
ca9c9e7e PD	415	fallthrough;
050fed8a PD	416	case CPU_STM32MP153Fxx:
050fed8a PD	417	case CPU_STM32MP153Dxx:
73306a12 PD	418	case CPU_STM32MP153Cxx:
73306a12 PD	419	case CPU_STM32MP153Axx:
ca9c9e7e PD	420	stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name);
ca9c9e7e PD	421	stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name);
73306a12 PD	422	break;
	423	default:
	424	break;
	425	}
73306a12	426	switch (cpu) {
050fed8a	427	case CPU_STM32MP157Dxx:
73306a12	428	case CPU_STM32MP157Axx:
050fed8a	429	case CPU_STM32MP153Dxx:
73306a12	430	case CPU_STM32MP153Axx:
050fed8a	431	case CPU_STM32MP151Dxx:
73306a12	432	case CPU_STM32MP151Axx:
ca9c9e7e PD	433	stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp",
	434	name);
	435	stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp",
	436	name);
73306a12 PD	437	break;
	438	default:
	439	break;
	440	}
05d36936	441	switch (get_cpu_package()) {
6df271a7	442	case STM32MP15_PKG_AA_LBGA448:
05d36936 PD	443	pkg = STM32MP_PKG_AA;
05d36936 PD	444	break;
6df271a7	445	case STM32MP15_PKG_AB_LBGA354:
05d36936 PD	446	pkg = STM32MP_PKG_AB;
05d36936 PD	447	break;
6df271a7	448	case STM32MP15_PKG_AC_TFBGA361:
05d36936 PD	449	pkg = STM32MP_PKG_AC;
05d36936 PD	450	break;
6df271a7	451	case STM32MP15_PKG_AD_TFBGA257:
05d36936 PD	452	pkg = STM32MP_PKG_AD;
	453	break;
	454	default:
	455	pkg = 0;
	456	break;
	457	}
	458	if (pkg) {
	459	do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl",
	460	"st,package", pkg, false);
	461	do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl",
	462	"st,package", pkg, false);
	463	}
ca9c9e7e PD	464	}
	465
	466	/*
	467	* This function is called right before the kernel is booted. "blob" is the
	468	* device tree that will be passed to the kernel.
	469	*/
	470	int ft_system_setup(void blob, struct bd_info bd)
	471	{
	472	int ret = 0;
	473	int soc;
	474	u32 cpu;
	475	char name[SOC_NAME_SIZE];
05d36936	476
ca9c9e7e PD	477	soc = fdt_path_offset(blob, "/soc");
	478	/* when absent, nothing to do */
	479	if (soc == -FDT_ERR_NOTFOUND)
	480	return 0;
	481	if (soc < 0)
	482	return soc;
	483
	484	if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
	485	ret = stm32_fdt_fixup_etzpc(blob, soc);
	486	if (ret)
	487	return ret;
	488	}
	489
	490	/* MPUs Part Numbers and name*/
	491	cpu = get_cpu_type();
	492	get_soc_name(name);
	493
df68a309 PD	494	if (IS_ENABLED(CONFIG_STM32MP13x))
	495	stm32mp13_fdt_fixup(blob, soc, cpu, name);
	496
ca9c9e7e PD	497	if (IS_ENABLED(CONFIG_STM32MP15x)) {
	498	stm32mp15_fdt_fixup(blob, soc, cpu, name);
	499
	500	/*
	501	* TEMP: remove OP-TEE nodes in kernel device tree
	502	* copied from U-Boot device tree by optee_copy_fdt_nodes
	503	* when OP-TEE is not detected (probe failed)
	504	* these OP-TEE nodes are present in <board>-u-boot.dtsi
	505	* under CONFIG_STM32MP15x_STM32IMAGE only for compatibility
	506	* when FIP is not used by TF-A
	507	*/
	508	if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) &&
	509	!tee_find_device(NULL, NULL, NULL, NULL))
	510	stm32_fdt_disable_optee(blob);
	511	}
4a1b975d	512
05d36936 PD	513	return ret;
05d36936 PD	514	}