[J-u-boot.git] / include / configs / uc101.h

/*
 * (C) Copyright 2003-2006
 * Heiko Schocher, DENX Software Engineering, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_UC101		1	/* UC101 board			*/

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM		0x02	/* Software reboot			*/

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported 			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_DOS_PARTITION


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DISPLAY
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DTT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NFS
#define CONFIG_CMD_MII
#define CONFIG_CMD_SNTP


#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (TEXT_BASE == 0xFFF00000) /* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addwdt=setenv bootargs ${bootargs} wdt=off"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

#define CONFIG_MISC_INIT_R	1

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CFG_I2C_EEPROM_ADDR		0x58
#define CFG_I2C_EEPROM_ADDR_LEN		1
#define CFG_EEPROM_PAGE_WRITE_BITS	4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
/* for LM81 */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CFG_I2C_RTC_ADDR		0x51

/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81			1	/* ON Semi's LM75		*/
#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses		*/
#define CFG_DTT_MAX_TEMP		70
#define CFG_DTT_LOW_TEMP		-30
#define CFG_DTT_HYSTERESIS		3

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		0xFF800000

#define CFG_FLASH_SIZE		0x00800000 /* 8 MByte */
#define CFG_MAX_FLASH_SECT	140	/* max num of sects on one chip */

#define CFG_ENV_ADDR		(TEXT_BASE+0x40000) /* second sector */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_CFI_AMD_RESET

/*
 * Environment settings
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x4000
#define CFG_ENV_SECT_SIZE	0x10000
#define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_DEFAULT_MBAR	0x80000000

#define CFG_SDRAM_BASE		0x00000000
#define CFG_SRAM_BASE		0x80100000	/* CS 1 */
#define CFG_DISPLAY_BASE	0x80600000	/* CS 3 */
#define	CFG_IB_MASTER		0xc0510000	/* CS 6 */
#define CFG_IB_EPLD		0xc0500000	/* CS 7 */

/* Settings for XLB = 132 MHz */
#define SDRAM_DDR	 1
#define SDRAM_MODE      0x018D0000
#define SDRAM_EMODE     0x40090000
#define SDRAM_CONTROL   0x714f0f00
#define SDRAM_CONFIG1   0x73722930
#define SDRAM_CONFIG2   0x47770000
#define SDRAM_TAPDELAY  0x10000000

/* SRAM */
#define SRAM_BASE		CFG_SRAM_BASE	/* SRAM base address	*/
#define SRAM_LEN		0x1fffff
#define SRAM_END		(SRAM_BASE + SRAM_LEN)

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE    TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII		1

/*
 * GPIO configuration
 */
#define CFG_GPS_PORT_CONFIG	0x4d558044

/*use  Hardware WDT */
#define CONFIG_HW_WATCHDOG

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00300000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 3 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x300000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#define CFG_BOOTCS_CFG		0x00045D00
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START		CFG_SRAM_BASE
#define CFG_CS1_SIZE		0x00200000
#define CFG_CS1_CFG		0x21D00

/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
#define CFG_CS3_START		CFG_DISPLAY_BASE
#define CFG_CS3_SIZE		0x00000100
#define CFG_CS3_CFG		0x00081802

/* Interbus Master 16 Bit */
#define CFG_CS6_START		CFG_IB_MASTER
#define CFG_CS6_SIZE		0x00010000
#define CFG_CS6_CFG		0x00FF3500

/* Interbus EPLD 8 Bit */
#define CFG_CS7_START		CFG_IB_EPLD
#define CFG_CS7_SIZE		0x00010000
#define CFG_CS7_CFG		0x00081800

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_IDE_PREINIT	1

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CFG_ATA_STRIDE          4

#define CONFIG_ATAPI            1

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/
#define CFG_DISP_CHR_RAM	(CFG_DISPLAY_BASE + 0x38)
#define CFG_DISP_CWORD		(CFG_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
6dedf3d4 HS	1	/*
	2	* (C) Copyright 2003-2006
	3	* Heiko Schocher, DENX Software Engineering, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	33	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	34	#define CONFIG_UC101 1 /* UC101 board */
	35
	36	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	37
	38	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	39	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	40
6dedf3d4 HS	41	#define CONFIG_BOARD_EARLY_INIT_R
6dedf3d4 HS	42
31d82672 BB	43	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	44
6dedf3d4 HS	45	/*
	46	* Serial console configuration
	47	*/
	48	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	49	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	50	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	51
	52	/* Partitions */
	53	#define CONFIG_DOS_PARTITION
	54
6c18eb98	55
079a136c JL	56	/*
	57	* BOOTP options
	58	*/
	59	#define CONFIG_BOOTP_BOOTFILESIZE
	60	#define CONFIG_BOOTP_BOOTPATH
	61	#define CONFIG_BOOTP_GATEWAY
	62	#define CONFIG_BOOTP_HOSTNAME
	63
	64
6dedf3d4	65	/*
6c18eb98	66	* Command line configuration.
6dedf3d4	67	*/
6c18eb98 JL	68	#include <config_cmd_default.h>
	69
	70	#define CONFIG_CMD_DATE
	71	#define CONFIG_CMD_DISPLAY
	72	#define CONFIG_CMD_DHCP
	73	#define CONFIG_CMD_PING
	74	#define CONFIG_CMD_EEPROM
	75	#define CONFIG_CMD_I2C
	76	#define CONFIG_CMD_DTT
	77	#define CONFIG_CMD_IDE
	78	#define CONFIG_CMD_FAT
	79	#define CONFIG_CMD_NFS
	80	#define CONFIG_CMD_MII
	81	#define CONFIG_CMD_SNTP
	82
6dedf3d4 HS	83
	84	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
	85
	86	#if (TEXT_BASE == 0xFFF00000) /* Boot low */
	87	# define CFG_LOWBOOT 1
	88	#endif
	89
	90	/*
	91	* Autobooting
	92	*/
	93	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	94
	95	#define CONFIG_PREBOOT "echo;" \
32bf3d14	96	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6dedf3d4 HS	97	"echo"
	98
	99	#undef CONFIG_BOOTARGS
	100
	101	#define CONFIG_EXTRA_ENV_SETTINGS \
	102	"netdev=eth0\0" \
	103	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	104	"nfsroot=${serverip}:${rootpath}\0" \
	105	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	106	"addwdt=setenv bootargs ${bootargs} wdt=off" \
	107	"addip=setenv bootargs ${bootargs} " \
	108	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	109	":${hostname}:${netdev}:off panic=1\0" \
	110	"flash_nfs=run nfsargs addip;" \
	111	"bootm ${kernel_addr}\0" \
	112	"net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \
	113	"rootpath=/opt/eldk/ppc_82xx\0" \
	114	""
	115
	116	#define CONFIG_BOOTCOMMAND "run net_nfs"
	117
	118	#define CONFIG_MISC_INIT_R 1
	119
	120	/*
	121	* IPB Bus clocking configuration.
	122	*/
c99512d6	123	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6dedf3d4 HS	124
	125	/*
	126	* I2C configuration
	127	*/
	128	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	129	#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
	130
	131	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	132	#define CFG_I2C_SLAVE 0x7F
	133
	134	/*
	135	* EEPROM configuration
	136	*/
	137	#define CFG_I2C_EEPROM_ADDR 0x58
	138	#define CFG_I2C_EEPROM_ADDR_LEN 1
	139	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	140	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	141	/* for LM81 */
	142	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	143
	144	/*
	145	* RTC configuration
	146	*/
	147	#define CONFIG_RTC_PCF8563
	148	#define CFG_I2C_RTC_ADDR 0x51
	149
	150	/* I2C SYSMON (LM75) */
	151	#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
	152	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
	153	#define CFG_DTT_MAX_TEMP 70
	154	#define CFG_DTT_LOW_TEMP -30
	155	#define CFG_DTT_HYSTERESIS 3
	156
	157	/*
	158	* Flash configuration
	159	*/
	160	#define CFG_FLASH_BASE 0xFF800000
	161
	162	#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
	163	#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */
	164
	165	#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
	166	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	167	(= chip selects) */
	168	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	169	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	170
00b1883a	171	#define CONFIG_FLASH_CFI_DRIVER
6dedf3d4 HS	172	#define CFG_FLASH_CFI
	173	#define CFG_FLASH_EMPTY_INFO
	174	#define CFG_FLASH_CFI_AMD_RESET
	175
	176	/*
	177	* Environment settings
	178	*/
	179	#define CFG_ENV_IS_IN_FLASH 1
	180	#define CFG_ENV_SIZE 0x4000
	181	#define CFG_ENV_SECT_SIZE 0x10000
	182	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
	183	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	184
	185	/*
	186	* Memory map
	187	*/
	188	#define CFG_MBAR 0xF0000000
	189	#define CFG_DEFAULT_MBAR 0x80000000
	190
	191	#define CFG_SDRAM_BASE 0x00000000
	192	#define CFG_SRAM_BASE 0x80100000 /* CS 1 */
	193	#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */
	194	#define CFG_IB_MASTER 0xc0510000 /* CS 6 */
	195	#define CFG_IB_EPLD 0xc0500000 /* CS 7 */
	196
	197	/* Settings for XLB = 132 MHz */
	198	#define SDRAM_DDR 1
	199	#define SDRAM_MODE 0x018D0000
	200	#define SDRAM_EMODE 0x40090000
	201	#define SDRAM_CONTROL 0x714f0f00
	202	#define SDRAM_CONFIG1 0x73722930
	203	#define SDRAM_CONFIG2 0x47770000
	204	#define SDRAM_TAPDELAY 0x10000000
	205
	206	/* SRAM */
	207	#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */
	208	#define SRAM_LEN 0x1fffff
	209	#define SRAM_END (SRAM_BASE + SRAM_LEN)
	210
	211	/* Use ON-Chip SRAM until RAM will be available */
	212	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	213	#ifdef CONFIG_POST
	214	/* preserve space for the post_word at end of on-chip SRAM */
	215	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	216	#else
	217	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	218	#endif
	219
	220
	221	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	222	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	223	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	224
	225	#define CFG_MONITOR_BASE TEXT_BASE
	226	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	227	# define CFG_RAMBOOT 1
	228	#endif
	229
	230	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	231	#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
	232	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	233
	234	/*
	235	* Ethernet configuration
236	*/
237	#define CONFIG_MPC5xxx_FEC 1
238	#define CONFIG_PHY_ADDR 0x00
239	#define CONFIG_MII 1
240
241	/*
242	* GPIO configuration
243	*/
244	#define CFG_GPS_PORT_CONFIG 0x4d558044
245
246	/use Hardware WDT /
247	#define CONFIG_HW_WATCHDOG
248
249	/*
250	* Miscellaneous configurable options
251	*/
252	#define CFG_LONGHELP /* undef to save memory */
253	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
6c18eb98	254	#if defined(CONFIG_CMD_KGDB)
6dedf3d4 HS	255	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	256	#else
	257	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	258	#endif
	259	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	260	#define CFG_MAXARGS 16 /* max number of command args */
	261	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	262
	263	/* Enable an alternate, more extensive memory test */
	264	#define CFG_ALT_MEMTEST
	265
	266	#define CFG_MEMTEST_START 0x00300000 /* memtest works on */
	267	#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */
	268
	269	#define CFG_LOAD_ADDR 0x300000 /* default load address */
	270
	271	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	272
6c18eb98 JL	273	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	274	#if defined(CONFIG_CMD_KGDB)
	275	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	276	#endif
	277
6dedf3d4	278	/*
079a136c	279	* Enable loopw command.
6dedf3d4 HS	280	*/
	281	#define CONFIG_LOOPW
	282
	283	/*
	284	* Various low-level settings
	285	*/
	286	#if defined(CONFIG_MPC5200)
	287	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	288	#define CFG_HID0_FINAL HID0_ICE
	289	#else
	290	#define CFG_HID0_INIT 0
	291	#define CFG_HID0_FINAL 0
	292	#endif
	293
	294	#define CFG_BOOTCS_START CFG_FLASH_BASE
	295	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
	296	#define CFG_BOOTCS_CFG 0x00045D00
	297	#define CFG_CS0_START CFG_FLASH_BASE
	298	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	299
	300	/* 8Mbit SRAM @0x80100000 */
	301	#define CFG_CS1_START CFG_SRAM_BASE
1ce55151	302	#define CFG_CS1_SIZE 0x00200000
6dedf3d4 HS	303	#define CFG_CS1_CFG 0x21D00
	304
	305	/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
	306	#define CFG_CS3_START CFG_DISPLAY_BASE
	307	#define CFG_CS3_SIZE 0x00000100
	308	#define CFG_CS3_CFG 0x00081802
	309
	310	/* Interbus Master 16 Bit */
	311	#define CFG_CS6_START CFG_IB_MASTER
	312	#define CFG_CS6_SIZE 0x00010000
	313	#define CFG_CS6_CFG 0x00FF3500
	314
	315	/* Interbus EPLD 8 Bit */
	316	#define CFG_CS7_START CFG_IB_EPLD
	317	#define CFG_CS7_SIZE 0x00010000
	318	#define CFG_CS7_CFG 0x00081800
	319
	320	#define CFG_CS_BURST 0x00000000
	321	#define CFG_CS_DEADCYCLE 0x33333333
	322
	323	/*-----------------------------------------------------------------------
	324	* IDE/ATA stuff Supports IDE harddisk
	325	*-----------------------------------------------------------------------
	326	*/
	327
	328	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	329
	330	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	331	#undef CONFIG_IDE_LED /* LED for ide not supported */
	332
	333	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	334	#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
	335
	336	#define CONFIG_IDE_PREINIT 1
6dedf3d4 HS	337
	338	#define CFG_ATA_IDE0_OFFSET 0x0000
	339
	340	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	341
	342	/* Offset for data I/O */
	343	#define CFG_ATA_DATA_OFFSET (0x0060)
	344
	345	/* Offset for normal register accesses */
	346	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	347
	348	/* Offset for alternate registers */
	349	#define CFG_ATA_ALT_OFFSET (0x005C)
	350
	351	/* Interval between registers */
	352	#define CFG_ATA_STRIDE 4
	353
	354	#define CONFIG_ATAPI 1
	355
	356	/---------------------------------------------------------------------/
	357	/* Display addresses */
	358	/---------------------------------------------------------------------/
	359	#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
	360	#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
	361
	362	#endif /* __CONFIG_H */