[J-u-boot.git] / include / fsl_esdhc.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * FSL SD/MMC Defines
 *-------------------------------------------------------------------
 *
 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
 */

#ifndef  __FSL_ESDHC_H__
#define	__FSL_ESDHC_H__

#include <linux/errno.h>
#include <asm/byteorder.h>

/* needed for the mmc_cfg definition */
#include <mmc.h>

#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
#include "../board/freescale/common/qixis.h"
#endif

/* FSL eSDHC-specific constants */
#define SYSCTL			0x0002e02c
#define SYSCTL_INITA		0x08000000
#define SYSCTL_TIMEOUT_MASK	0x000f0000
#define SYSCTL_CLOCK_MASK	0x0000fff0
#define SYSCTL_CKEN		0x00000008
#define SYSCTL_PEREN		0x00000004
#define SYSCTL_HCKEN		0x00000002
#define SYSCTL_IPGEN		0x00000001
#define SYSCTL_RSTA		0x01000000
#define SYSCTL_RSTC		0x02000000
#define SYSCTL_RSTD		0x04000000

#define IRQSTAT			0x0002e030
#define IRQSTAT_DMAE		(0x10000000)
#define IRQSTAT_AC12E		(0x01000000)
#define IRQSTAT_DEBE		(0x00400000)
#define IRQSTAT_DCE		(0x00200000)
#define IRQSTAT_DTOE		(0x00100000)
#define IRQSTAT_CIE		(0x00080000)
#define IRQSTAT_CEBE		(0x00040000)
#define IRQSTAT_CCE		(0x00020000)
#define IRQSTAT_CTOE		(0x00010000)
#define IRQSTAT_CINT		(0x00000100)
#define IRQSTAT_CRM		(0x00000080)
#define IRQSTAT_CINS		(0x00000040)
#define IRQSTAT_BRR		(0x00000020)
#define IRQSTAT_BWR		(0x00000010)
#define IRQSTAT_DINT		(0x00000008)
#define IRQSTAT_BGE		(0x00000004)
#define IRQSTAT_TC		(0x00000002)
#define IRQSTAT_CC		(0x00000001)

#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
				IRQSTAT_DMAE)
#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)

#define IRQSTATEN		0x0002e034
#define IRQSTATEN_DMAE		(0x10000000)
#define IRQSTATEN_AC12E		(0x01000000)
#define IRQSTATEN_DEBE		(0x00400000)
#define IRQSTATEN_DCE		(0x00200000)
#define IRQSTATEN_DTOE		(0x00100000)
#define IRQSTATEN_CIE		(0x00080000)
#define IRQSTATEN_CEBE		(0x00040000)
#define IRQSTATEN_CCE		(0x00020000)
#define IRQSTATEN_CTOE		(0x00010000)
#define IRQSTATEN_CINT		(0x00000100)
#define IRQSTATEN_CRM		(0x00000080)
#define IRQSTATEN_CINS		(0x00000040)
#define IRQSTATEN_BRR		(0x00000020)
#define IRQSTATEN_BWR		(0x00000010)
#define IRQSTATEN_DINT		(0x00000008)
#define IRQSTATEN_BGE		(0x00000004)
#define IRQSTATEN_TC		(0x00000002)
#define IRQSTATEN_CC		(0x00000001)

#define ESDHCCTL		0x0002e40c
#define ESDHCCTL_PCS		(0x00080000)

#define PRSSTAT			0x0002e024
#define PRSSTAT_DAT0		(0x01000000)
#define PRSSTAT_CLSL		(0x00800000)
#define PRSSTAT_WPSPL		(0x00080000)
#define PRSSTAT_CDPL		(0x00040000)
#define PRSSTAT_CINS		(0x00010000)
#define PRSSTAT_BREN		(0x00000800)
#define PRSSTAT_BWEN		(0x00000400)
#define PRSSTAT_SDSTB		(0X00000008)
#define PRSSTAT_DLA		(0x00000004)
#define PRSSTAT_CICHB		(0x00000002)
#define PRSSTAT_CIDHB		(0x00000001)

#define PROCTL			0x0002e028
#define PROCTL_INIT		0x00000020
#define PROCTL_DTW_4		0x00000002
#define PROCTL_DTW_8		0x00000004
#define PROCTL_D3CD		0x00000008

#define CMDARG			0x0002e008

#define XFERTYP			0x0002e00c
#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
#define XFERTYP_CMDTYP_NORMAL	0x0
#define XFERTYP_CMDTYP_SUSPEND	0x00400000
#define XFERTYP_CMDTYP_RESUME	0x00800000
#define XFERTYP_CMDTYP_ABORT	0x00c00000
#define XFERTYP_DPSEL		0x00200000
#define XFERTYP_CICEN		0x00100000
#define XFERTYP_CCCEN		0x00080000
#define XFERTYP_RSPTYP_NONE	0
#define XFERTYP_RSPTYP_136	0x00010000
#define XFERTYP_RSPTYP_48	0x00020000
#define XFERTYP_RSPTYP_48_BUSY	0x00030000
#define XFERTYP_MSBSEL		0x00000020
#define XFERTYP_DTDSEL		0x00000010
#define XFERTYP_DDREN		0x00000008
#define XFERTYP_AC12EN		0x00000004
#define XFERTYP_BCEN		0x00000002
#define XFERTYP_DMAEN		0x00000001

#define CINS_TIMEOUT		1000
#define PIO_TIMEOUT		500

#define DSADDR		0x2e004

#define CMDRSP0		0x2e010
#define CMDRSP1		0x2e014
#define CMDRSP2		0x2e018
#define CMDRSP3		0x2e01c

#define DATPORT		0x2e020

#define WML		0x2e044
#define WML_WRITE	0x00010000
#ifdef CONFIG_FSL_SDHC_V2_3
#define WML_RD_WML_MAX		0x80
#define WML_WR_WML_MAX		0x80
#define WML_RD_WML_MAX_VAL	0x0
#define WML_WR_WML_MAX_VAL	0x0
#define WML_RD_WML_MASK		0x7f
#define WML_WR_WML_MASK		0x7f0000
#else
#define WML_RD_WML_MAX		0x10
#define WML_WR_WML_MAX		0x80
#define WML_RD_WML_MAX_VAL	0x10
#define WML_WR_WML_MAX_VAL	0x80
#define WML_RD_WML_MASK	0xff
#define WML_WR_WML_MASK	0xff0000
#endif

#define BLKATTR		0x2e004
#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
#define BLKATTR_SIZE(x)	(x & 0x1fff)
#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */

#define ESDHC_HOSTCAPBLT_VS18	0x04000000
#define ESDHC_HOSTCAPBLT_VS30	0x02000000
#define ESDHC_HOSTCAPBLT_VS33	0x01000000
#define ESDHC_HOSTCAPBLT_SRS	0x00800000
#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
#define ESDHC_HOSTCAPBLT_HSS	0x00200000

struct fsl_esdhc_cfg {
	phys_addr_t esdhc_base;
	u32	sdhc_clk;
	u8	max_bus_width;
	int	wp_enable;
	int	vs18_enable; /* Use 1.8V if set to 1 */
	struct mmc_config cfg;
};

/* Select the correct accessors depending on endianess */
#if defined CONFIG_SYS_FSL_ESDHC_LE
#define esdhc_read32		in_le32
#define esdhc_write32		out_le32
#define esdhc_clrsetbits32	clrsetbits_le32
#define esdhc_clrbits32		clrbits_le32
#define esdhc_setbits32		setbits_le32
#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
#define esdhc_read32            in_be32
#define esdhc_write32           out_be32
#define esdhc_clrsetbits32      clrsetbits_be32
#define esdhc_clrbits32         clrbits_be32
#define esdhc_setbits32         setbits_be32
#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32		in_le32
#define esdhc_write32		out_le32
#define esdhc_clrsetbits32	clrsetbits_le32
#define esdhc_clrbits32		clrbits_le32
#define esdhc_setbits32		setbits_le32
#elif __BYTE_ORDER == __BIG_ENDIAN
#define esdhc_read32		in_be32
#define esdhc_write32		out_be32
#define esdhc_clrsetbits32	clrsetbits_be32
#define esdhc_clrbits32		clrbits_be32
#define esdhc_setbits32		setbits_be32
#else
#error "Endianess is not defined: please fix to continue"
#endif

#ifdef CONFIG_FSL_ESDHC
int fsl_esdhc_mmc_init(bd_t *bis);
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
void fdt_fixup_esdhc(void *blob, bd_t *bd);
#else
static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
#endif /* CONFIG_FSL_ESDHC */
void __noreturn mmc_boot(void);
void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);

#endif  /* __FSL_ESDHC_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
50586ef2 AF	2	/*
	3	* FSL SD/MMC Defines
	4	*-------------------------------------------------------------------
	5	*
32c8cfb2	6	* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
50586ef2 AF	7	*/
	8
	9	#ifndef __FSL_ESDHC_H__
	10	#define __FSL_ESDHC_H__
	11
1221ce45	12	#include <linux/errno.h>
c67bee14	13	#include <asm/byteorder.h>
b33433a6	14
93bfd616 PA	15	/* needed for the mmc_cfg definition */
	16	#include <mmc.h>
	17
5a8dbdc6 YL	18	#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
	19	#include "../board/freescale/common/qixis.h"
	20	#endif
	21
50586ef2 AF	22	/* FSL eSDHC-specific constants */
	23	#define SYSCTL 0x0002e02c
	24	#define SYSCTL_INITA 0x08000000
	25	#define SYSCTL_TIMEOUT_MASK 0x000f0000
1118cdbf	26	#define SYSCTL_CLOCK_MASK 0x0000fff0
c67bee14	27	#define SYSCTL_CKEN 0x00000008
50586ef2 AF	28	#define SYSCTL_PEREN 0x00000004
	29	#define SYSCTL_HCKEN 0x00000002
	30	#define SYSCTL_IPGEN 0x00000001
48bb3bb5	31	#define SYSCTL_RSTA 0x01000000
7a5b8029 DB	32	#define SYSCTL_RSTC 0x02000000
7a5b8029 DB	33	#define SYSCTL_RSTD 0x04000000
50586ef2 AF	34
	35	#define IRQSTAT 0x0002e030
	36	#define IRQSTAT_DMAE (0x10000000)
	37	#define IRQSTAT_AC12E (0x01000000)
	38	#define IRQSTAT_DEBE (0x00400000)
	39	#define IRQSTAT_DCE (0x00200000)
	40	#define IRQSTAT_DTOE (0x00100000)
	41	#define IRQSTAT_CIE (0x00080000)
	42	#define IRQSTAT_CEBE (0x00040000)
	43	#define IRQSTAT_CCE (0x00020000)
	44	#define IRQSTAT_CTOE (0x00010000)
	45	#define IRQSTAT_CINT (0x00000100)
	46	#define IRQSTAT_CRM (0x00000080)
	47	#define IRQSTAT_CINS (0x00000040)
	48	#define IRQSTAT_BRR (0x00000020)
	49	#define IRQSTAT_BWR (0x00000010)
	50	#define IRQSTAT_DINT (0x00000008)
	51	#define IRQSTAT_BGE (0x00000004)
	52	#define IRQSTAT_TC (0x00000002)
	53	#define IRQSTAT_CC (0x00000001)
	54
	55	#define CMD_ERR (IRQSTAT_CIE \| IRQSTAT_CEBE \| IRQSTAT_CCE)
9b74dc56 AG	56	#define DATA_ERR (IRQSTAT_DEBE \| IRQSTAT_DCE \| IRQSTAT_DTOE \| \
	57	IRQSTAT_DMAE)
	58	#define DATA_COMPLETE (IRQSTAT_TC \| IRQSTAT_DINT)
50586ef2 AF	59
	60	#define IRQSTATEN 0x0002e034
	61	#define IRQSTATEN_DMAE (0x10000000)
	62	#define IRQSTATEN_AC12E (0x01000000)
	63	#define IRQSTATEN_DEBE (0x00400000)
	64	#define IRQSTATEN_DCE (0x00200000)
	65	#define IRQSTATEN_DTOE (0x00100000)
	66	#define IRQSTATEN_CIE (0x00080000)
	67	#define IRQSTATEN_CEBE (0x00040000)
	68	#define IRQSTATEN_CCE (0x00020000)
	69	#define IRQSTATEN_CTOE (0x00010000)
	70	#define IRQSTATEN_CINT (0x00000100)
	71	#define IRQSTATEN_CRM (0x00000080)
	72	#define IRQSTATEN_CINS (0x00000040)
	73	#define IRQSTATEN_BRR (0x00000020)
	74	#define IRQSTATEN_BWR (0x00000010)
	75	#define IRQSTATEN_DINT (0x00000008)
	76	#define IRQSTATEN_BGE (0x00000004)
	77	#define IRQSTATEN_TC (0x00000002)
	78	#define IRQSTATEN_CC (0x00000001)
	79
2d9ca2c7 YL	80	#define ESDHCCTL 0x0002e40c
	81	#define ESDHCCTL_PCS (0x00080000)
	82
50586ef2	83	#define PRSSTAT 0x0002e024
7a5b8029	84	#define PRSSTAT_DAT0 (0x01000000)
50586ef2 AF	85	#define PRSSTAT_CLSL (0x00800000)
	86	#define PRSSTAT_WPSPL (0x00080000)
	87	#define PRSSTAT_CDPL (0x00040000)
	88	#define PRSSTAT_CINS (0x00010000)
	89	#define PRSSTAT_BREN (0x00000800)
77c1458d	90	#define PRSSTAT_BWEN (0x00000400)
2d9ca2c7	91	#define PRSSTAT_SDSTB (0X00000008)
50586ef2 AF	92	#define PRSSTAT_DLA (0x00000004)
	93	#define PRSSTAT_CICHB (0x00000002)
	94	#define PRSSTAT_CIDHB (0x00000001)
	95
	96	#define PROCTL 0x0002e028
	97	#define PROCTL_INIT 0x00000020
	98	#define PROCTL_DTW_4 0x00000002
	99	#define PROCTL_DTW_8 0x00000004
1f15cb8f	100	#define PROCTL_D3CD 0x00000008
50586ef2 AF	101
	102	#define CMDARG 0x0002e008
	103
	104	#define XFERTYP 0x0002e00c
	105	#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
	106	#define XFERTYP_CMDTYP_NORMAL 0x0
	107	#define XFERTYP_CMDTYP_SUSPEND 0x00400000
	108	#define XFERTYP_CMDTYP_RESUME 0x00800000
	109	#define XFERTYP_CMDTYP_ABORT 0x00c00000
	110	#define XFERTYP_DPSEL 0x00200000
	111	#define XFERTYP_CICEN 0x00100000
	112	#define XFERTYP_CCCEN 0x00080000
	113	#define XFERTYP_RSPTYP_NONE 0
	114	#define XFERTYP_RSPTYP_136 0x00010000
	115	#define XFERTYP_RSPTYP_48 0x00020000
	116	#define XFERTYP_RSPTYP_48_BUSY 0x00030000
	117	#define XFERTYP_MSBSEL 0x00000020
	118	#define XFERTYP_DTDSEL 0x00000010
0e1bf614	119	#define XFERTYP_DDREN 0x00000008
50586ef2 AF	120	#define XFERTYP_AC12EN 0x00000004
	121	#define XFERTYP_BCEN 0x00000002
	122	#define XFERTYP_DMAEN 0x00000001
	123
	124	#define CINS_TIMEOUT 1000
bcfb3653	125	#define PIO_TIMEOUT 500
50586ef2 AF	126
	127	#define DSADDR 0x2e004
	128
	129	#define CMDRSP0 0x2e010
	130	#define CMDRSP1 0x2e014
	131	#define CMDRSP2 0x2e018
	132	#define CMDRSP3 0x2e01c
	133
	134	#define DATPORT 0x2e020
	135
	136	#define WML 0x2e044
	137	#define WML_WRITE 0x00010000
32c8cfb2 PJ	138	#ifdef CONFIG_FSL_SDHC_V2_3
	139	#define WML_RD_WML_MAX 0x80
	140	#define WML_WR_WML_MAX 0x80
	141	#define WML_RD_WML_MAX_VAL 0x0
	142	#define WML_WR_WML_MAX_VAL 0x0
	143	#define WML_RD_WML_MASK 0x7f
	144	#define WML_WR_WML_MASK 0x7f0000
	145	#else
	146	#define WML_RD_WML_MAX 0x10
	147	#define WML_WR_WML_MAX 0x80
	148	#define WML_RD_WML_MAX_VAL 0x10
	149	#define WML_WR_WML_MAX_VAL 0x80
ab467c51 RZ	150	#define WML_RD_WML_MASK 0xff
ab467c51 RZ	151	#define WML_WR_WML_MASK 0xff0000
32c8cfb2	152	#endif
50586ef2 AF	153
	154	#define BLKATTR 0x2e004
	155	#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
	156	#define BLKATTR_SIZE(x) (x & 0x1fff)
	157	#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
	158
	159	#define ESDHC_HOSTCAPBLT_VS18 0x04000000
	160	#define ESDHC_HOSTCAPBLT_VS30 0x02000000
	161	#define ESDHC_HOSTCAPBLT_VS33 0x01000000
	162	#define ESDHC_HOSTCAPBLT_SRS 0x00800000
	163	#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
	164	#define ESDHC_HOSTCAPBLT_HSS 0x00200000
	165
c67bee14	166	struct fsl_esdhc_cfg {
5330c7d7	167	phys_addr_t esdhc_base;
a2ac1b3a	168	u32 sdhc_clk;
aad4659a	169	u8 max_bus_width;
15a91651	170	int wp_enable;
32a9179f	171	int vs18_enable; /* Use 1.8V if set to 1 */
93bfd616	172	struct mmc_config cfg;
c67bee14 SB	173	};
	174
	175	/* Select the correct accessors depending on endianess */
c82e9de4 WH	176	#if defined CONFIG_SYS_FSL_ESDHC_LE
	177	#define esdhc_read32 in_le32
	178	#define esdhc_write32 out_le32
	179	#define esdhc_clrsetbits32 clrsetbits_le32
	180	#define esdhc_clrbits32 clrbits_le32
	181	#define esdhc_setbits32 setbits_le32
	182	#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
	183	#define esdhc_read32 in_be32
	184	#define esdhc_write32 out_be32
	185	#define esdhc_clrsetbits32 clrsetbits_be32
	186	#define esdhc_clrbits32 clrbits_be32
	187	#define esdhc_setbits32 setbits_be32
	188	#elif __BYTE_ORDER == __LITTLE_ENDIAN
c67bee14 SB	189	#define esdhc_read32 in_le32
	190	#define esdhc_write32 out_le32
	191	#define esdhc_clrsetbits32 clrsetbits_le32
	192	#define esdhc_clrbits32 clrbits_le32
	193	#define esdhc_setbits32 setbits_le32
	194	#elif __BYTE_ORDER == __BIG_ENDIAN
	195	#define esdhc_read32 in_be32
	196	#define esdhc_write32 out_be32
	197	#define esdhc_clrsetbits32 clrsetbits_be32
	198	#define esdhc_clrbits32 clrbits_be32
	199	#define esdhc_setbits32 setbits_be32
	200	#else
	201	#error "Endianess is not defined: please fix to continue"
	202	#endif
	203
b33433a6	204	#ifdef CONFIG_FSL_ESDHC
50586ef2	205	int fsl_esdhc_mmc_init(bd_t *bis);
c67bee14	206	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg);
b33433a6 AV	207	void fdt_fixup_esdhc(void blob, bd_t bd);
	208	#else
	209	static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
	210	static inline void fdt_fixup_esdhc(void blob, bd_t bd) {}
	211	#endif /* CONFIG_FSL_ESDHC */
bb0dc108	212	void __noreturn mmc_boot(void);
1eaa742d	213	void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
50586ef2 AF	214
50586ef2 AF	215	#endif /* __FSL_ESDHC_H__ */