Merge tag 'gvt-fixes-2020-09-17' of https://github.com/intel/gvt-linux into drm-intel...

gvt-fixes-2020-09-17

- Fix kernel oops for VFIO edid on BDW (Zhenyu)

Signed-off-by: Jani Nikula <[email protected]>
From: Zhenyu Wang <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --combined drivers/gpu/drm/i915/gvt/vgpu.c
index 8fa9b31a248401ffc28a0b862827e3da6c4f2fa0,041f601b07d065373ec509fe83a3e979b854f592..f6d7e33c7099e7976bd7388858af2b869657757e
--- 1/drivers/gpu/drm/i915/gvt/vgpu.c
--- 2/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@@ -257,7 -257,6 +257,7 @@@ void intel_gvt_release_vgpu(struct inte
        intel_gvt_deactivate_vgpu(vgpu);
  
        mutex_lock(&vgpu->vgpu_lock);
 +      vgpu->d3_entered = false;
        intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
        intel_vgpu_dmabuf_cleanup(vgpu);
        mutex_unlock(&vgpu->vgpu_lock);
@@@ -368,6 -367,7 +368,7 @@@ void intel_gvt_destroy_idle_vgpu(struc
  static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
                struct intel_vgpu_creation_params *param)
  {
+       struct drm_i915_private *dev_priv = gvt->gt->i915;
        struct intel_vgpu *vgpu;
        int ret;
  
@@@ -394,7 -394,6 +395,7 @@@
        INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
        idr_init(&vgpu->object_idr);
        intel_vgpu_init_cfg_space(vgpu, param->primary);
 +      vgpu->d3_entered = false;
  
        ret = intel_vgpu_init_mmio(vgpu);
        if (ret)
@@@ -436,7 -435,10 +437,10 @@@
        if (ret)
                goto out_clean_sched_policy;
  
-       ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
+       if (IS_BROADWELL(dev_priv))
+               ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);
+       else
+               ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
        if (ret)
                goto out_clean_sched_policy;
  
@@@ -559,15 -561,10 +563,15 @@@ void intel_gvt_reset_vgpu_locked(struc
        /* full GPU reset or device model level reset */
        if (engine_mask == ALL_ENGINES || dmlr) {
                intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
 -              intel_vgpu_invalidate_ppgtt(vgpu);
 +              if (engine_mask == ALL_ENGINES)
 +                      intel_vgpu_invalidate_ppgtt(vgpu);
                /*fence will not be reset during virtual reset */
                if (dmlr) {
 -                      intel_vgpu_reset_gtt(vgpu);
 +                      if(!vgpu->d3_entered) {
 +                              intel_vgpu_invalidate_ppgtt(vgpu);
 +                              intel_vgpu_destroy_all_ppgtt_mm(vgpu);
 +                      }
 +                      intel_vgpu_reset_ggtt(vgpu, true);
                        intel_vgpu_reset_resource(vgpu);
                }
  
@@@ -579,14 -576,7 +583,14 @@@
                        intel_vgpu_reset_cfg_space(vgpu);
                        /* only reset the failsafe mode when dmlr reset */
                        vgpu->failsafe = false;
 -                      vgpu->pv_notified = false;
 +                      /*
 +                       * PCI_D0 is set before dmlr, so reset d3_entered here
 +                       * after done using.
 +                       */
 +                      if(vgpu->d3_entered)
 +                              vgpu->d3_entered = false;
 +                      else
 +                              vgpu->pv_notified = false;
                }
        }