Merge tag 'drm-msm-next-2021-10-26' of https://gitlab.freedesktop.org/drm/msm into...

* eDP support in DP sub-driver (for newer SoCs with native eDP output)
* dpu irq handling cleanup
* CRC support for making igt happy
* Support for NO_CONNECTOR bridges
* dsi: 14nm phy support for msm8953
* mdp5: support for msm8x53, sdm450, sdm632
* various smaller fixes and cleanups

Signed-off-by: Dave Airlie <[email protected]>
From: Rob Clark <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsH9EwcpqGNNRJeL99NvFFjHX3SUg+nTYu0dHG5U9+QuA@mail.gmail.com

diff --combined drivers/gpu/drm/msm/Kconfig
index f5107b6ded7b2923ae349c56febcbd3ef445327a,36e5ba3ccc287c8c5b8bb45e034b9fe3995683f8..ae11061727ff80d7141609909552bee59f444f1d
--- 1/drivers/gpu/drm/msm/Kconfig
--- 2/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@@ -3,9 -3,9 +3,9 @@@
  config DRM_MSM
        tristate "MSM DRM"
        depends on DRM
 -      depends on ARCH_QCOM || SOC_IMX5 || (ARM && COMPILE_TEST)
 +      depends on ARCH_QCOM || SOC_IMX5 || COMPILE_TEST
        depends on IOMMU_SUPPORT
 -      depends on OF && COMMON_CLK
 +      depends on (OF && COMMON_CLK) || COMPILE_TEST
        depends on QCOM_OCMEM || QCOM_OCMEM=n
        depends on QCOM_LLCC || QCOM_LLCC=n
        depends on QCOM_COMMAND_DB || QCOM_COMMAND_DB=n
@@@ -14,10 -14,12 +14,12 @@@
        select REGULATOR
        select DRM_KMS_HELPER
        select DRM_PANEL
+       select DRM_BRIDGE
+       select DRM_PANEL_BRIDGE
        select DRM_SCHED
        select SHMEM
        select TMPFS
 -      select QCOM_SCM if ARCH_QCOM
 +      select QCOM_SCM
        select WANT_DEV_COREDUMP
        select SND_SOC_HDMI_CODEC if SND_SOC
        select SYNC_FILE
@@@ -55,7 -57,7 +57,7 @@@ config DRM_MSM_GPU_SUD
  
  config DRM_MSM_HDMI_HDCP
        bool "Enable HDMI HDCP support in MSM DRM driver"
 -      depends on DRM_MSM && QCOM_SCM
 +      depends on DRM_MSM
        default y
        help
          Choose this option to enable HDCP state machine

diff --combined drivers/gpu/drm/msm/msm_gem.c
index 40a9863f5951c78f4fc4c7e67be37ec7ffece257,6b03e00cc5f2118e603c711482ff7c2bf1d76408..104fdfc140278863c62a1dc1225c253d863e727a
--- 1/drivers/gpu/drm/msm/msm_gem.c
--- 2/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@@ -5,6 -5,7 +5,7 @@@
   */
  
  #include <linux/dma-map-ops.h>
+ #include <linux/vmalloc.h>
  #include <linux/spinlock.h>
  #include <linux/shmem_fs.h>
  #include <linux/dma-buf.h>
@@@ -85,7 -86,7 +86,7 @@@ static struct page **get_pages_vram(str
  
        paddr = physaddr(obj);
        for (i = 0; i < npages; i++) {
 -              p[i] = phys_to_page(paddr);
 +              p[i] = pfn_to_page(__phys_to_pfn(paddr));
                paddr += PAGE_SIZE;
        }
  
@@@ -1132,6 -1133,7 +1133,7 @@@ static int msm_gem_new_impl(struct drm_
        msm_obj->flags = flags;
        msm_obj->madv = MSM_MADV_WILLNEED;
  
+       INIT_LIST_HEAD(&msm_obj->node);
        INIT_LIST_HEAD(&msm_obj->vmas);
  
        *obj = &msm_obj->base;
@@@ -1166,7 -1168,7 +1168,7 @@@ struct drm_gem_object *msm_gem_new(stru
  
        ret = msm_gem_new_impl(dev, size, flags, &obj);
        if (ret)
-               goto fail;
+               return ERR_PTR(ret);
  
        msm_obj = to_msm_bo(obj);
  
@@@ -1250,7 -1252,7 +1252,7 @@@ struct drm_gem_object *msm_gem_import(s
  
        ret = msm_gem_new_impl(dev, size, MSM_BO_WC, &obj);
        if (ret)
-               goto fail;
+               return ERR_PTR(ret);
  
        drm_gem_private_object_init(dev, obj, size);
  

diff --combined drivers/gpu/drm/msm/msm_gpu.h
index ee25d556c8a10c99dfbc0f03fba1c253ffbb0c95,59870095ea4109f23a37f9c7d9369a65111207e1..59cdd00b69d0401e2720b2e37b8ff8d546c0c7ac
--- 1/drivers/gpu/drm/msm/msm_gpu.h
--- 2/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@@ -112,6 -112,13 +112,13 @@@ struct msm_gpu_devfreq 
         * it is inactive.
         */
        unsigned long idle_freq;
+ 
+       /**
+        * idle_work:
+        *
+        * Used to delay clamping to idle freq on active->idle transition.
+        */
+       struct msm_hrtimer_work idle_work;
  };
  
  struct msm_gpu {
@@@ -203,10 -210,6 +210,10 @@@
        uint32_t suspend_count;
  
        struct msm_gpu_state *crashstate;
 +
 +      /* Enable clamping to idle freq when inactive: */
 +      bool clamp_to_idle;
 +
        /* True if the hardware supports expanded apriv (a650 and newer) */
        bool hw_apriv;
  

diff --combined drivers/gpu/drm/msm/msm_gpu_devfreq.c
index 20006d060b5b5564532710a727bfa08caed96818,d32b729b4616238fde17f3e2105c7a09d1d2ea96..8b7473f69cb8fe6bf86a86a097dfd0396e5b4207
--- 1/drivers/gpu/drm/msm/msm_gpu_devfreq.c
--- 2/drivers/gpu/drm/msm/msm_gpu_devfreq.c
+++ b/drivers/gpu/drm/msm/msm_gpu_devfreq.c
@@@ -88,8 -88,12 +88,12 @@@ static struct devfreq_dev_profile msm_d
        .get_cur_freq = msm_devfreq_get_cur_freq,
  };
  
+ static void msm_devfreq_idle_work(struct kthread_work *work);
+ 
  void msm_devfreq_init(struct msm_gpu *gpu)
  {
+       struct msm_gpu_devfreq *df = &gpu->devfreq;
+ 
        /* We need target support to do devfreq */
        if (!gpu->funcs->gpu_busy)
                return;
@@@ -105,25 -109,27 +109,27 @@@
        msm_devfreq_profile.freq_table = NULL;
        msm_devfreq_profile.max_state = 0;
  
-       gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
+       df->devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
                        &msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
                        NULL);
  
-       if (IS_ERR(gpu->devfreq.devfreq)) {
+       if (IS_ERR(df->devfreq)) {
                DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
-               gpu->devfreq.devfreq = NULL;
+               df->devfreq = NULL;
                return;
        }
  
-       devfreq_suspend_device(gpu->devfreq.devfreq);
+       devfreq_suspend_device(df->devfreq);
  
-       gpu->cooling = of_devfreq_cooling_register(gpu->pdev->dev.of_node,
-                       gpu->devfreq.devfreq);
+       gpu->cooling = of_devfreq_cooling_register(gpu->pdev->dev.of_node, df->devfreq);
        if (IS_ERR(gpu->cooling)) {
                DRM_DEV_ERROR(&gpu->pdev->dev,
                                "Couldn't register GPU cooling device\n");
                gpu->cooling = NULL;
        }
+ 
+       msm_hrtimer_work_init(&df->idle_work, gpu->worker, msm_devfreq_idle_work,
+                             CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  }
  
  void msm_devfreq_cleanup(struct msm_gpu *gpu)
@@@ -154,6 -160,11 +160,11 @@@ void msm_devfreq_active(struct msm_gpu 
        if (!df->devfreq)
                return;
  
+       /*
+        * Cancel any pending transition to idle frequency:
+        */
+       hrtimer_cancel(&df->idle_work.timer);
+ 
        /*
         * Hold devfreq lock to synchronize with get_dev_status()/
         * target() callbacks
@@@ -184,9 -195,12 +195,12 @@@
        mutex_unlock(&df->devfreq->lock);
  }
  
- void msm_devfreq_idle(struct msm_gpu *gpu)
+ 
+ static void msm_devfreq_idle_work(struct kthread_work *work)
  {
-       struct msm_gpu_devfreq *df = &gpu->devfreq;
+       struct msm_gpu_devfreq *df = container_of(work,
+                       struct msm_gpu_devfreq, idle_work.work);
+       struct msm_gpu *gpu = container_of(df, struct msm_gpu, devfreq);
        unsigned long idle_freq, target_freq = 0;
  
        if (!df->devfreq)
@@@ -200,11 -214,18 +214,19 @@@
  
        idle_freq = get_freq(gpu);
  
 -      msm_devfreq_target(&gpu->pdev->dev, &target_freq, 0);
 +      if (gpu->clamp_to_idle)
 +              msm_devfreq_target(&gpu->pdev->dev, &target_freq, 0);
  
        df->idle_time = ktime_get();
        df->idle_freq = idle_freq;
  
        mutex_unlock(&df->devfreq->lock);
  }
+ 
+ void msm_devfreq_idle(struct msm_gpu *gpu)
+ {
+       struct msm_gpu_devfreq *df = &gpu->devfreq;
+ 
+       msm_hrtimer_queue_work(&df->idle_work, ms_to_ktime(1),
+                              HRTIMER_MODE_ABS);
+ }