Merge patch series "riscv: Extension parsing fixes"

Charlie Jenkins <[email protected]> says:

This series contains two minor fixes for the extension parsing in
cpufeature.c.

Some T-Head boards without vector 1.0 support report "v" in the isa
string in their DT which will cause the kernel to run vector code. The
code to blacklist "v" from these boards was doing so by using
riscv_cached_mvendorid() which has not been populated at the time of
extension parsing. This fix instead greedily reads the mvendorid CSR of
the boot hart to determine if the cpu is from T-Head.

The other fix is for an incorrect indexing bug. riscv extensions
sometimes imply other extensions. When adding these "subset" extensions
to the hardware capabilities array, they need to be checked if they are
valid. The current code only checks if the extension that is including
other extensions is valid and not the subset extensions.

These patches were previously included in:
https://lore.kernel.org/lkml/20240420-dev-charlie-support_thead_vector_6_9-v3-0-67cff4271d1d@rivosinc.com/

* b4-shazam-merge:
  riscv: cpufeature: Fix extension subset checking
  riscv: cpufeature: Fix thead vector hwcap removal

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

diff --combined arch/riscv/include/asm/sbi.h
index 9186e7984672cde84e20194884c2db19e83aa4d6,0fab508a65b3c9a68daf9cafd75ff658855e0f63..1079e214fe855e8fcabcbcc8b9e6687efd68eb1e
--- 1/arch/riscv/include/asm/sbi.h
--- 2/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@@ -131,8 -131,6 +131,8 @@@ enum sbi_ext_pmu_fid 
        SBI_EXT_PMU_COUNTER_START,
        SBI_EXT_PMU_COUNTER_STOP,
        SBI_EXT_PMU_COUNTER_FW_READ,
 +      SBI_EXT_PMU_COUNTER_FW_READ_HI,
 +      SBI_EXT_PMU_SNAPSHOT_SET_SHMEM,
  };
  
  union sbi_pmu_ctr_info {
@@@ -149,13 -147,6 +149,13 @@@
        };
  };
  
 +/* Data structure to contain the pmu snapshot data */
 +struct riscv_pmu_snapshot_data {
 +      u64 ctr_overflow_mask;
 +      u64 ctr_values[64];
 +      u64 reserved[447];
 +};
 +
  #define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(47, 0)
  #define RISCV_PMU_RAW_EVENT_IDX 0x20000
  
@@@ -241,22 -232,20 +241,22 @@@ enum sbi_pmu_ctr_type 
  #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
  
  /* Flags defined for config matching function */
 -#define SBI_PMU_CFG_FLAG_SKIP_MATCH   (1 << 0)
 -#define SBI_PMU_CFG_FLAG_CLEAR_VALUE  (1 << 1)
 -#define SBI_PMU_CFG_FLAG_AUTO_START   (1 << 2)
 -#define SBI_PMU_CFG_FLAG_SET_VUINH    (1 << 3)
 -#define SBI_PMU_CFG_FLAG_SET_VSINH    (1 << 4)
 -#define SBI_PMU_CFG_FLAG_SET_UINH     (1 << 5)
 -#define SBI_PMU_CFG_FLAG_SET_SINH     (1 << 6)
 -#define SBI_PMU_CFG_FLAG_SET_MINH     (1 << 7)
 +#define SBI_PMU_CFG_FLAG_SKIP_MATCH   BIT(0)
 +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE  BIT(1)
 +#define SBI_PMU_CFG_FLAG_AUTO_START   BIT(2)
 +#define SBI_PMU_CFG_FLAG_SET_VUINH    BIT(3)
 +#define SBI_PMU_CFG_FLAG_SET_VSINH    BIT(4)
 +#define SBI_PMU_CFG_FLAG_SET_UINH     BIT(5)
 +#define SBI_PMU_CFG_FLAG_SET_SINH     BIT(6)
 +#define SBI_PMU_CFG_FLAG_SET_MINH     BIT(7)
  
  /* Flags defined for counter start function */
 -#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
 +#define SBI_PMU_START_FLAG_SET_INIT_VALUE BIT(0)
 +#define SBI_PMU_START_FLAG_INIT_SNAPSHOT BIT(1)
  
  /* Flags defined for counter stop function */
 -#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
 +#define SBI_PMU_STOP_FLAG_RESET BIT(0)
 +#define SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT BIT(1)
  
  enum sbi_ext_dbcn_fid {
        SBI_EXT_DBCN_CONSOLE_WRITE = 0,
@@@ -277,7 -266,7 +277,7 @@@ struct sbi_sta_struct 
        u8 pad[47];
  } __packed;
  
 -#define SBI_STA_SHMEM_DISABLE         -1
 +#define SBI_SHMEM_DISABLE             -1
  
  /* SBI spec version fields */
  #define SBI_SPEC_VERSION_DEFAULT      0x1
@@@ -295,7 -284,6 +295,7 @@@
  #define SBI_ERR_ALREADY_AVAILABLE -6
  #define SBI_ERR_ALREADY_STARTED -7
  #define SBI_ERR_ALREADY_STOPPED -8
 +#define SBI_ERR_NO_SHMEM      -9
  
  extern unsigned long sbi_spec_version;
  struct sbiret {
@@@ -367,8 -355,8 +367,8 @@@ static inline unsigned long sbi_minor_v
  static inline unsigned long sbi_mk_version(unsigned long major,
                                            unsigned long minor)
  {
 -      return ((major & SBI_SPEC_VERSION_MAJOR_MASK) <<
 -              SBI_SPEC_VERSION_MAJOR_SHIFT) | minor;
 +      return ((major & SBI_SPEC_VERSION_MAJOR_MASK) << SBI_SPEC_VERSION_MAJOR_SHIFT)
 +              | (minor & SBI_SPEC_VERSION_MINOR_MASK);
  }
  
  int sbi_err_map_linux_errno(int err);
@@@ -382,17 -370,15 +382,19 @@@ static inline int sbi_remote_fence_i(co
  static inline void sbi_init(void) {}
  #endif /* CONFIG_RISCV_SBI */
  
+ unsigned long riscv_get_mvendorid(void);
+ unsigned long riscv_get_marchid(void);
  unsigned long riscv_cached_mvendorid(unsigned int cpu_id);
  unsigned long riscv_cached_marchid(unsigned int cpu_id);
  unsigned long riscv_cached_mimpid(unsigned int cpu_id);
  
  #if IS_ENABLED(CONFIG_SMP) && IS_ENABLED(CONFIG_RISCV_SBI)
 +DECLARE_STATIC_KEY_FALSE(riscv_sbi_for_rfence);
 +#define riscv_use_sbi_for_rfence() \
 +      static_branch_unlikely(&riscv_sbi_for_rfence)
  void sbi_ipi_init(void);
  #else
 +static inline bool riscv_use_sbi_for_rfence(void) { return false; }
  static inline void sbi_ipi_init(void) { }
  #endif